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STLD

1. The document discusses how to realize digital logic circuits using multiplexers and demultiplexers. It contains 5 questions about implementing functions using 4 to 1 and 8 to 1 multiplexers, designing a 64 line demultiplexer, detecting decimal codes from an excess 3 code, designing an excess 3 adder, and drawing a single bit comparator and decimal to BCD encoder.

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58 views

STLD

1. The document discusses how to realize digital logic circuits using multiplexers and demultiplexers. It contains 5 questions about implementing functions using 4 to 1 and 8 to 1 multiplexers, designing a 64 line demultiplexer, detecting decimal codes from an excess 3 code, designing an excess 3 adder, and drawing a single bit comparator and decimal to BCD encoder.

Uploaded by

api-3697093
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Stld set no:4 (4th

unit assignment)
1.(a) show how a 16 to 1 mux can be realized using 4 to 1 muxes.
(b) implement the function f(a,b,c)=a.b+b’c using the 4 to 1 mux.

2.(a )Design 64 line output demultiplexer using lower order demultiplexer


Such as 4 to 16 and 2 to 4 demultiplexers.
(b) Give the NAND gate realization for a full adder.

3. A circuit receives a 4 bit Excess 3 code. Design a minimal circuit to


detect the decimal numbers 0,1,4,6,7 and 8.

4.(a) Design a excess 3 adder using 4 bit parallel binary adder and logic
gates
(b)Draw the logic diagram of a single bit comparator.

5.(a) Implement the following Boolean function using a 8:1 multiplexer


Considering ‘D’ as the input and A,B,C as selection lines.
f(ABCD)=AB’+BD+B’CD’
(b) Draw the gate level diagram of a Decimal to BCD encoder.

Thnx n regrds……dpnkr

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