CHAPTER 1

INTRODUCTION
Cars on the same direction in highway usually keep a safe distance one another with a similar speed. However, due to the drivers distraction, long-time driving fatigue, flake out, or even a sudden deceleration of the previous car, a serious collision accident may occur if the driver can not react in time to brake. On the other hand, drivers need the mirrors to know other approaching cars from two-side or from the rear end. Even the driver check around carefully, he cannot take an immediate respond, except push the horn, to a sudden approaching car and an accident is thus unavoidable. Therefore, developing a front-obstacle warning system and a rear end collision avoidance system subject to all directions are important in collision avoidance. For the front-end collision avoidance subsystem, Ultrasonic sensor is adopted to measure the distance with respect to the previous car. For rear-end end collision avoidance subsystem, the currently available ultrasonic sensors for vehicles are adopted for approaching cars with relatively low speed. While the rough reading of distance data cannot be applied directly, an intelligent approach is proposed to process the raw distance readout of sensors to produce appropriate warning signals. When there are more electrical control devices in the modem cars, such as power train management system, antilock braking system (ABS), and acceleration skid control (ASC) system, etc, the functionality and wiring of these electric control units (!XU) are getting more complicated. Therefore, it is of great concern to upgrade the traditional wire harness to a smart &car network. In 198Os, a Germany car component provider Robert Bosch Co. introduced an in-car network; the controller area network (CAN) bus, to replace the complex and expensive traditional in-car wiring [5]. In this study, a highlevel protocol CAN open is adopted to interconnect those CAN nodes with reliable communications among sensors.

The block diagram of system which includes sensor, ADC, LCD, LPC2129, buzzer, fuel sensor and speed sensor is as shown in fig 1.1. The system mainly consists of front-end-sub-system and rear-end-sub-system.

Front End Ultrasonic sensor

A D C

Fuel Sensor

L P C 2 1 2 9

CAN 1

CAN 2

L P C 2 1 2 9

A D C

Back End Ultrasonic sensor

Buzzer Speed Sensor

Figure 1.1: BLOCK DIAGRAM for the can based accident avoidance system

1.1 The front-end sub-system:

This subsystem for generating warning signals for the front-end collision avoidance is constructed by measuring the distance with SICK laser radar (LMS22130206). The collision avoidance of the front-end car usually operated under a relatively high speed. Therefore, the laser radar is required to detect the front car in a relative long distance as far as 50-80 m with a high resolution as 1 cm. The warning signal is for derivers attention to avoid the collision by the braking action actively.

1.2 The rear-end sub-system:

In the other hand, the real-end collision avoidance would be inherently in shorter distance with a slow approaching speed. Besides, only passively action, which a warning

signal can be generated for the approaching car drivers, can be taken. Therefore, rear-end collision avoidance warning sub-system is constructed with the available ultrasonic sensors which have been widely implemented on commercial vehicles. The distance between the driving car and the approaching cars can be measured only with a rough distance readout every 5 on and a limited range as 20- 150 cm as in Table 1. They show that an intelligent approach to process those readout of the sensor is required to provide reliable warning signal. Output Code corresponding the distance of the ultrasonic sensors(LMS221-30206) Distance Code Physical Distance(cm) 30 35 40 45 .. 130 135 140 145 150 5 15 25 35 . 205 215 225 235 245

Table 1.1 The warning subsystem is developed to be less independent of the approaching speed so that an appropriate precaution time can be provided for the approaching car to prevent the rear-end collision passively.

1.3 Statement of the problem

In this project we aim at Designing of CAN based Accident avoidance system using two Philips LPC2129 32 bit microcontroller which is having ARM7TDMI processor with many onboard interfaces like memory, LCD, I/O , CAN controller, serial

port ,I2C interface, UART, 10 bit ADC, and standard JTAG interface. These two microcontroller are connected by CAN bus for transmission of data between them.

1.4 Organization of the report

Including this introductory chapter, the report is organized as follows The second chapter discusses the ARM7TDMI PROCESSOR. The third chapter discusses the CONTROLLER AREA NETWORK PROTOCOL. The forth chapter discusses the Analog to Digital Converter. The fifth chapter discusses UART in ARM; The sixth chapter discusses the Hardware and Software Tools. In the seventh chapter discusses about the RESULTS. In the eighth CONCLUSION and in ninth chapter FUTURE ENHANCEMENT are given.

CHAPTER 2

ARM7TDMI PROCESSOR
The ARM7TDMI core is a member of the ARM family of general-purpose 32-bit Microprocessors. The ARM [4] family offers high performance for very low power Consumption and small size. The ARM architecture as shown in fig 2.2 is based on Reduced Instruction Set Computer (RISC) principles. The RISC instruction set and related decode mechanism are much simple than those of Complex Instruction Set Computer (CISC) designs. This simplicity gives: A high instruction throughput An excellent real-time interrupt response A small, cost-effective, processor macrocell.

2.1 The instruction pipeline

The ARM7TDMI core uses a pipeline to increase the speed of the flow of instructions to the processor. This enables several operations to take place simultaneously, and the processing and memory systems to operate continuously. A three-stage pipeline is used as shown in fig 2.1, so instructions are executed in three stages: Fetch Decode Execute.

Figure 2.1: The instruction pipeline

During normal operation, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The program counter points to the instruction being fetched rather than to the instruction being executed. This is important because it means that the Program Counter (PC) value used in an executing instruction is always two instructions ahead of the address.

2.2 Memory access

The ARM7TDMI core has Von Neumann architecture, with a single 32-bit data bus carrying both instructions and data. Only load, store, and swap instructions can access data from memory. Data can be: 8-bit (bytes) 16-bit (half words) 32-bit (words). Words must be aligned to 4-byte boundaries. Half words must be aligned to 2-byte boundaries.

2.3 Memory interface

The ARM7TDMI processor memory interface has been designed to allow performance potential to be realized, while minimizing the use of memory. Speed-critical control signals are pipelined to enable system control functions to be implemented in standard low-power logic. These control signals facilitate the exploitation of the fastburst access modes supported by many on-chip and off-chip memory technologies.

USER/System R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15(PC)

FIQ R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12__FIQ R13_FIQ R14_FIQ R15(PC)

Figure 2.2:

SUPERVISOR ABORT R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_SVC R14_SVC R15(PC) R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12

IRQ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12

UNDEFINED R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12

R13_ABT R13_IRQ R13_UND R14_ABT R14_IRQ R14_UND R15(PC) R15(PC) R15(PC)

ARM7TDMI processor block diagram

CPSR

CPSR

CPSR

CPSR

CPSR

CPSR

SPSR_FIQ SPSR_SVC

SPSR_ABT SPSR_IRQ SPSR_UND

Table 2.1: ARM7TDMI REGISTER SET AND OPERATING MODES

The ARM7TDMI core has four basic types of memory cycle: Idle cycle

 Non sequential cycle Sequential cycle Coprocessor registers transfer cycle.

2.4 Architecture
The ARM7TDMI processor has two instruction sets: The 32-bit ARM instruction set The 16-bit Thumb instruction set. The ARM7TDMI processor is an implementation of the ARMv4T architecture.

2.5 Instruction compression

Microprocessor architectures traditionally have the same width for instructions and data. In comparison with 16-bit architectures, 32-bit architectures exhibit higher performance when manipulating 32-bit data and can address a large address space much more efficiently. 16-bit architectures typically have higher code density than 32-bit architectures, but approximately half the performance. Thumb implements a 16-bit instruction set on a 32-bit architecture to provide: Higher performance than a 16-bit architecture Higher code density than a 32-bit architecture.

2.6 The Thumb instruction set

The Thumb instruction set is a subset of the most commonly used 32-bit ARM instructions. Thumb instructions are each 16 bits long, and have a corresponding 32-bit ARM instruction that has the same effect on the processor model. Thumb instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and Thumb states.

On execution, 16-bit Thumb instructions are transparently decompressed to full 32-bit ARM instructions in real time without performance loss.

Thumb has all the advantages of a 32-bit core: 32-bit address space 32-bit registers 32-bit shifter, and Arithmetic Logic Unit (ALU) 32-bit memory transfer. Thumb therefore offers a long branch range, powerful arithmetic operations, and a large address space. Thumb code is typically 65% of the size of ARM code, and provides 160% of the performance of ARM code when running from a 16-bit memory system. Thumb, therefore, makes the ARM7TDMI core ideally suited to embedded applications with restricted memory bandwidth, where code density and footprint is important. The availability of both 16-bit Thumb and 32-bit ARM instruction sets gives designers the flexibility to emphasize performance or code size on a subroutine level, according to the requirements of their applications. For example, critical loops for applications such as fast interrupts and DSP algorithms can be coded using the full ARM instruction set then linked with Thumb code.

CHAPTER 3

CONTROLLER AREA NETWORK PROTOCOL

Controller Area Network (CAN) is an advanced serial bus system that efficiently supports distributed control system with a very high level of security. Robert Bosch, Germany[1][2][3] initially developed it for the use in motor vehicles in the late 1980s.Its domain of application ranges from high-speed network to low cost multiplex wiring. To improve the behavior of the vehicle, it was necessary for the different control system (and their sensor) to exchange information. This was usually done by discrete interconnection of the different system (i.e. point -to - point wiring). The requirement for the information exchange has then grown to such an extent that a cable network with a length up to several miles and many connectors were required. This leads to growing problems concerning material cost, production time and reliability. The solution to this problem was the connection of the Control system via a serial bus system. With the use of CAN, point - to - point wiring is replaced by one serial bus connecting to all control systems. This is accomplished by adding some CAN specific hardware to each control unit that provides the rules " or the protocol for transmitting and receiving information via the bus. The CAN protocol uses the data link layer and the physical layer in the ISO_OSI model.

3.1 Overview of CAN protocol

CAN is a multi - master bus with an open, linear structure with one logic bus line. The number of nodes is not limited by the protocol.

In CAN protocol, two versions are available. They are version 2.0A CAN and version 2.0B CAN. Version 2.0A is original CAN specifications specify an 11 bit identifier which allows 2^11(=2048) different message identifiers and is known as

standard CAN. Version 2.0B CAN contain 29 bit identifiers which allows 2^29 (over 536 million) message identifiers. CAN has the following properties: Prioritization of messages. Guarantee of latency times. Configuration flexibility. Multicast reception with time synchronization. System wide data consistency. Error detection and error signaling. called Carrier

The CAN protocol handle bus accesses according to the concept

Sense Multiple Access with arbitration on message priority ". This arbitration Concept avoids collisions of messages whose transmission was started by more than one node simultaneously and makes sure the most important message is sent first without time loss. If two or more bus nodes start their transmission at the same time after having found the bus to be idle, collision of the messages is avoided by bitwise arbitration. Each node sends the bits of its message identifier and monitors the bus level.

3.2 Basic concepts

Some of the basic concepts which are necessary to understand the CAN operation. They are as follows.

3.2.1 Messages

Information on the bus is sent in fixed format messages of different but limited length. When the bus is free any connected unit may start to transmit a new message.

3.2.2 Information routing

In CAN systems a can node does not make use of any information about the system configuration (e.g. station addresses).this has several important consequences.

3.2.3 System flexibility

Nodes can be added to the CAN network without requiring any change in the

software or hardware of any node and application layer.

3.2.4 Message routing

The content of a message is named by an IDENTIFIER. The identifier does not indicate the destination of the message but describes the meaning of the data ,so that all nodes in the network are able to decide by message filtering whether the data is to be acted upon by them or not.

3.2.5 Multicasting
As a consequence of the concept of message filtering any number of nodes can receive and simultaneously act upon the same message.

3.2.6 Data consistency

Within a CAN network it is guaranteed that a message is simultaneously accepted either by all nodes or by no node. Thus data consistency of a system is achieved by the concepts of multicast and by error handling.

3.2.7 Bit rate

The speed of CAN may be different in different systems. However, in a given system the bit rate is uniform and fixed.

3.2.8 Priorities
The identifier defines a static message priority during bus access.

3.2.9 Remote data request

By sending a remote frame a node requiring data may request another node to send the corresponding data frame. The data frame and the corresponding remote frame named by the same identifier.

3.2.10 Multimaster
When the bus is free any may start to transmit a message. The unit with the message of highest priority to be transmitted gains bus access.

3.2.11 Arbitration
Whenever the bus is free, any unit may start to transmit a message. If two or more units start transmitting messages at the same time, the bus access conflict is resolved by bit wise arbitration using the identifier. The mechanism of arbitration grantees that neither information nor time is lost. If a data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame. During arbitration every transmitter compares the level of the bit

transmitted with the level that is monitored on the bus. If these levels are equal the unit may continue to send. When a recessive level is sent and a dominant level is monitored, the unit has lost arbitration and must withdraw without sending one more bit.

3.3 Bus characteristics

Figure 3.1: Bus characteristics There are two bus states, called "dominant" and "recessive". The bus logic uses a "Wired-AND" mechanism, that is, "dominant bits" (equivalent to the logic level "Zero") overwrite the "recessive" bits (equivalent to the logic level "One).

3.3.1 Bus access and arbitration

The CAN protocol handles bus accesses according to the concept called Carrier Sense Multiple Access with Arbitration on Message Priority. This arbitration concept avoids collisions of messages whose transmission was started by more than one node simultaneously and makes sure the most important message is sent first without time loss.

Figure 3.2: BUS ACCESS AND ARBITRATION

In the picture above you see the trace of the transmit pins of three bus nodes called A, B and C, and the resulting bus state according to the wired-AND principle. If two or more bus nodes start their transmission at the same time after having found the bus to be idle, collision of the messages is avoided by bitwise arbitration. Each node sends the bits of its message identifier and monitors the bus level. At a certain time nodes A and C send a dominant identifier bit. Node B sends a recessive identifier bit but reads back a dominant one. Node B loses bus arbitration and switches to receive mode. Some bits later node C loses arbitration against node A. This means that the message identifier of node A has a lower binary value and therefore a higher priority than the messages of nodes B and C. In this way, the bus node with the highest priority message wins arbitration without losing time by having to repeat the message. Nodes B and C automatically try to repeat their transmission once the bus returns to the idle state. Node B loses against node C, so the message of node C is transmitted next, followed by node Bs message. It is not permitted for different nodes to send messages with the same identifier as arbitration could fail leading to collisions and errors

3.4 Message transfer

Message transfer is manifested and controlled by two frame types.

3.4.1 A data frame

As shown in fig 3.3carries data from a transmitter to the receivers. It is composed of seven different bit fields. Start of frame, Arbitration field, control field, data field, crc field, Ack field, End of frame.

3.4.2 A Remote frame

As shown in fig3.4 is transmitted by a bus unit to request the transmission of the data frame with the same identifier. It is composed of six different bit fields. Start of frame, Arbitration field, control field, crc field, Ack field, End of frame. A "Data Frame" is generated by a CAN node when the node wishes to transmit data. The Standard CAN Data Frame is shown above. The frame begins with a dominant Start of Frame bit for hard synchronization of all nodes.

Figure 3.3: Data Frame

The Start of Frame bit is followed by the Arbitration Field consisting of 12 bits. The 11-bit Identifier, which reflects the contents and priority of the message, and the Remote Transmission Request bit. The Remote transmission request bit is used to distinguish a Data Frame (RTR = dominant) from a Remote Frame (RTR = recessive).The next field is the Control Field, consisting of 6 bits. The first bit of this field is called the IDE bit (Identifier Extension) and is at dominant state to specify that the frame is a Standard Frame. The following bit is reserved and defined as a dominant bit. The remaining 4 bits of the Control Field are the Data Length Code (DLC) and specify the number of bytes of data contained in the message (0 - 8 bytes). The data being sent follows in the Data Field which is of the length defined by the DLC above (0, 8, 16, 56 or 64 bits).The Cyclic Redundancy Field (CRC field) follows and is used to detect possible transmission errors. The CRC Field consists of a 15 bit CRC sequence, completed by the recessive CRC Delimiter bit. The next field is the Acknowledge Field. During the ACK Slot bit the transmitting node sends out a recessive bit. Any node that has received an error free frame acknowledges the correct reception of the frame by sending back a dominant bit (regardless of whether the node is configured to accept that specific message or not). From this it can be seen that CAN belongs to the "in-bit-response" group of protocols. The recessive Acknowledge Delimiter completes the Acknowledge Slot and may not be overwritten by a dominant bit. Seven recessive bits (End of Frame) end the Data Frame.

Figure 3.4: Remote Frame

Generally data transmission is performed on an autonomous basis with the data source node (e.g. a sensor) sending out a Data Frame. It is also possible, however, for a destination node to request the data from the source by sending a Remote Frame. There are 2 differences between a Data Frame and a Remote Frame. Firstly the RTR-bit is transmitted as a dominant bit in the Data Frame and secondly in the Remote Frame there is no Data Field. In the very unlikely event of a Data Frame and a Remote Frame with the same identifier being transmitted at the same time. The Data Frame wins arbitration due to the dominant RTR bit following the identifier. In this way, the node that transmitted the Remote Frame receives the desired data immediately.

3.5 CAN Controller operation

The CAN controller having error detection and handling capacity in efficient way, it also makes sleep mode of operation and produces interrupts

3.5.1 Error Handling

The CAN Controllers count and handle transmit and receive errors as specified in CAN Spec 2.0B. The Transmit and Receive Error Counters are incremented for each detected error and are decremented when operation is error-free. If the Transmit Error counter contains 255 and another error occurs, the CAN Controller is forced into a state called Bus-Off. In this state, the following register bits are set: BS in CANSR, BEI and EI in CANIR if these are enabled, and RM in CANMOD. RM resets and disables much of the CAN Controller. Also at this time the Transmit Error Counter is set to 127 and the Receive Error Counter is cleared. Software must next clear the RM bit. Thereafter the Transmit Error

Counter will count down 128 occurrences of the Bus Free condition (11 consecutive recessive bits). Software can monitor this countdown by reading the Tx Error Counter. When this countdown is complete, the CAN Controller clears BS and ES in CANSR, and sets EI in CANSR if EIE in IER is 1. The Tx and Rx error counters can be written if RM in CANMOD is 1. Writing 255 to the Tx Error Counter forces the CAN Controller to Bus-Off state. If Bus-Off (BS in CANSR) is 1, writing any value 0 through 254 to the Tx Error Counter clears Bus-Off. When software clears RM in CANMOD thereafter, only one Bus Free condition (11 consecutive recessive bits) is needed before operation resumes.

3.5.2 Sleep Mode

The CAN Controller will enter sleep mode if the SM bit in the CAN Mode register is 1, no CAN interrupt is pending, and there is no activity on the CAN bus. Software can only set SM when RM in the CAN Mode register is 0; it can also set the WUIE bit in the CAN Interrupt Enable register to enable an interrupt on any wake-up condition. The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b) software clearing SM in the CAN Mode register. A sleeping CAN Controller, that wakes up in response to bus activity, is not able to receive an initial message, until after it detects Bus free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus is active when software sets SM, the wakeup is immediate.

3.5.3 Interrupts
Each CAN Controller produces 3 interrupt requests, Receive, Transmit, and other status. The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers. Each Receive and Transmit interrupt request from each controller is assigned

its own channel in the Vectored Interrupt Controller (VIC), and can have its own interrupt service routine. The other status interrupts from all of the CAN

controllers, and the Acceptance Filter LUTerr condition, are OR-ed into one VIC channel.

3.5.4 Transmit Priority

If the TPM bit in the CANMOD register is 0, multiple enabled Tx Buffers contend for the right to send their messages based on the value of their CAN Identifier (TID). If TPM is 1, they contend based on the PRIO fields in bits 7:0 of their CANTFS registers. In both cases the smallest binary value has priority. If two (or three) transmitenabled buffers have the same smallest value, the lowest-numbered buffer sends first. The CAN controller selects among multiple enabled Tx Buffers dynamically, just before it sends each message.

CHAPTER 4

ANALOG TO DIGITAL CONVERTER

The ADC0808, ADC0809 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter shown in fig 4.1 uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can directly access any of 8-single-ended analog signals. The device eliminates the need for external zero and full scale adjustments. Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE outputs. The design

of the ADC0808, ADC0809 has been optimized by incorporating the most desirable aspects of several A/D conversion techniques. The ADC0808, ADC0809 offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy

and repeatability, and consumes minimal power. These features make this device
ideally suited to applications from process and machine control to consumer and automotive applications. For 16-channel multiplexer with common output (sample/hold port) see ADC0816 data sheet. (See AN-247 for more information.).

4.1 Features
Easy interface to all microprocessors Operates ratio metrically or with 5 VDC or a span adjusted voltage reference No zero or full-scale adjust required 8-channel multiplexer with address logic 0V to 5V input range with single 5V power supply Outputs meet TTL voltage level specifications Standard hermetic or molded 28-pin DIP package

28-pin molded chip carrier package ADC0808 equivalent to MM74C949 ADC0809 equivalent to MM74C949-1

Figure 4.1: Block diagram of ADC

4.2 Functional Description

The some of the blocks in ADC and their functional description is given below.

4.2.1

Multiplexer
The device contains an 8-channel single-ended analog signal multiplexer. A

particular input channel is selected by using the address decoder. Table I shows the input states for the address lines to select any channel. The address is latched into the decoder on the low-to-high transition of the address latch enable signal.

Table 4.1

4.2.2 The Converter

The heart of this single chip data acquisition system is its 8-bit analog-to-digital converter. The converter is designed to give fast, accurate, and repeatable conversions over a wide range of temperatures. The converter is partitioned into 3 major sections: the 256R ladder network [5], the successive approximation register, and the comparator. The converter's digital outputs are positive true. The 256R ladder network approach (Figure 4.2) was chosen over the conventional R/2R ladder because of its inherent monotonic, which guarantees no missing digital codes. Monotonic is particularly important in closed loop feedback control systems. A non-monotonic relationship can cause oscillations that will be catastrophic for the system. Additionally, the 256R network does not cause load variations on the reference voltage. The bottom resistor and the top resistor of the ladder network are not the same value as the remainder of the network. The difference in these resistors causes the output characteristic to be symmetrical with the zero and full-scale points of the transfer curve. The first output transition occurs when the analog signal has reached +1/2 LSB and succeeding output transitions occur every 1 LSB later up to fullscale. The successive approximation register (SAR) performs 8 iterations to approximate the input voltage. For any SAR type converter, n-iterations are required for an n-bit converter. Figure shows a typical example of a 3-bit converter. In the ADC0808, ADC0809, the approximation technique is extended to 8 bits using the 256R network.

Figure 4.2:

The A/D converter's successive approximation register (SAR) is reset on the positive edge of the start conversion (SC) pulse. The conversion is begun on the falling edge of the start conversion pulse. A conversion in process will be interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by tying the end of conversion (EOC) output to the SC input. If used in this mode, an external start conversion pulse should be applied after power up. End-of-conversion will go low between and 8 clock pulses after the rising edge of start conversion. The most important section of the A/D converter is the comparator. It is this section which is responsible for the ultimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the repeatability of the device. A chopper-stabilized comparator provides the most effective method of satisfying all the converter requirements.

The chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then fed through a high gain AC amplifier and has the DC level restored. This technique limits the drift component of the amplifier since the drift is a DC component which is not passed by the AC amplifier. This makes the entire A/D converter extremely insensitive to temperature, long term drift and input offset errors.

Figure 4.3 ADC analysis

4.3 Analog to Digital Converter in ARM

The A/D converter present on some LPC2000 variants is a 10-bit successive approximation converter, with a conversion time of 2.44 microseconds or just shy of 410 KSps.

The A/D converter has either 4 or 8 multiplexed inputs depending on the variant

Figure 4.4: A/D 4 or 8 channel of 10 bit resolution

The A/D control register establishes the configuration of the converter & controls the start of conversion. The first step in configuring the converter is to set up the peripheral clock. As with all the other peripherals, the A/D clock is derived from the PCLK. This PCLK must be divided down to equal 4.5MHz. This is a maximum value and if PCLK cannot be divided down to equal 4.5MHz then the nearest value below 4.5MHz which can be achieved should be selected.

Figure 4.5: A/D control register

PCLK is divided by the value stored in the CLKDIV field plus one. Hence the equation for the A/D clock is as follows: CLKDIV = ( PCLK/Adclk) 1 As well as being able to stop the clock to the A/D converter in the peripheral power down register, the A/D has the ability to fully power down. This reduces the overall power consumption and the on-chip noise created by the A/D. On reset, the A/D is in power down mode, so as well as setting the clock rate the A/D must be switched on. This is controlled by the PDN bit in ADCR.

Logic one in this field enables the converter. Unlike other peripherals the A/D converter can make measurements of the external pins when they are configured as GPIO pins. However, by using the pinselect block to make the external pins dedicated to the A/D converter the overall conversion accuracy is increased Prior to a conversion the resolution of the result may be defined by programming the CLKS field. The A/D has a maximum resolution of 10 bits but can be programmed to give any resolution down to 3 bits. The conversion resolution is equal to the number of clock cycles per conversion minus one. Hence for a 10-bit result the A/D requires 11 ADCLK cycles and four for a 3bit result. Once you have configured the A/D resolution, a conversion can be made. The A/D has two conversion modes, hardware and software. The hardware mode allows you to select a number of channels and then set the A/D running. In this mode a conversion is made for each channel in turn until the converter is stopped. At the end of each conversion the result is available in the A/D data register.

Figure 4.6 A/D data register

At the end of a conversion the Done bit is set and an interrupt may also be generated. The conversion result is stored in the V/Vdda field as a ratio of the voltage on the analogue channel divided by the voltage on the analogue power supply pin. The number of the channel for which the conversion was made is also stored alongside the result. This value is stored in the CHN field. Finally, if the result of a conversion is not read before the next result is due, it will be overwritten by the fresh result and the OVERUN bit is set to one.

Table 4: The A/D may be started by a software event or it may be started by several hardware triggers

The A/D has a second software conversion mode. In this case, a channel is selected for conversion using the SEL bits and the conversion is started under software control by writing 0x01 to the START field. This causes the A/D to perform single conversion and store the results in the ADDR in the same fashion as the hardware mode. The end of conversion can be signaled by an interrupt, or by polling the done bit in the ADDR. In the software conversion mode it is possible to start a conversion when a match event occurs on timer zero or timer one. Or when a selected edge occurs on P0.16 or P0.22, the edge can be rising or falling, as selected by the EDGE field in the ADCR.

CHAPTER 5

UART IN ARM
The LPC2xxx devices currently have two on-chip UARTS. They are both identical to use, except UART1 has additional modem support. Both peripherals conform

to the 550 industry standard specification. Both have a built-in baud rate generator and 16 byte transmit and receive FIFOs.

Figure 5.1: max232

First the pinselect block must be programmed to switch the processor pins from GPIO to the UART functions. Next the UART line control register is used to configure the format of the transmitter data character.

Figure 5.3: UART line control register

The character format is set to 8 bits, no parity and one stop bit. In the LCR there is an additional bit called DLAB, which is the divisor latch access bit. In order to be able to program the baud rate generator this bit must be set.

The baud rate generator is a sixteen bit prescaler which divides down Pclk to generate the UART clock which must run at 16 times the baud rate. Hence the formula used to calculate the UART baud rate is: Divisor = Pclk/16 x BAUD In our case at 15MHz: Divisor = 15,000,000/16 x 9600 = (approx) 97 or 0x62 This gives a true baud rate of 9665. Often it is not possible to get an exact baud rate for the UARTs however they will work with up to around a 5% error in the bit timing. So you have some leeway with the UART timings if you need to adjust the Pclk to get exact timings on other peripherals such as the CAN bit timings. The divisor value is held in two registers, Divisor latch MSB (DLM) and Divisor latch LSB (DLL). The first eight bits of both registers holds each half of the divisor as shown below. Finally the DLAB bit in the LCR register must be set back to zero to protect the contents of the divisor registers.

Figure 5.4: UART baud rate

Once the UART is initialized, characters can be transmitted by writing to the Transmit Holding Register. Similarly, characters may be received by reading from the Receive Buffer Register. In fact both these registers occupy the same memory location,

writing a character places the character in the transmit FIFO and reading from this location loads a character from the Receive FIFO. The two routines shown below demonstrate handling of transmit and receive characters.

CHAPTER 6

HARDWARE AND SOFTWARE TOOLS

HARDWARE COMPONENTS USED

Power Supply Micro controller Protocol Devices MCP2551

5v DC, 12v DC. LPC2129-philips. CAN BUS. ULTRASONIC SENSORS in front-rear end,

SOFTWARE USED
Embedded C. Philips Flash utility Keil vision 3(IDE) C ARM Compiler (v2.32a) VB Software

6.1 Hardware Tools

The Hardware includes LPC2129microcontroller, LV-Maxsonar ultrasonic sensor, MCP2551.The detailed study of these components is given below.

6.1.1 LPC 2129 Device description

The LPC2119/2129/2194/2292/2294 are based on a 16/32 bit ARM7TDMI-STM CPU with real-time emulation and embedded trace support, together with 128/256 kilobytes (kB) of embedded high speed flash memory. A 128-bit wide internal memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate.

Figure 6.1: LPC2129 internal Block diagram

For critical code size applications, the alternative 16-bit Thumb Mode reduces code by more than 30% with minimal performance penalty. With their compact 64 and 144 pin packages, low power consumption, various 32-bit timers, combination of 4channel 10-bit ADC and 2/4 advanced CAN channels or 8-channel 10-bit ADC and 2/4 advanced CAN channels (64 and 144 pin packages respectively), and up to 9 external interrupt pins these microcontrollers are particularly suitable for industrial control, medical systems, access control and point-of-sale. Number of available GPIOs goes up to 46 in 64 pin package. In 144 pin packages number of available GPIOs tops 76 (with external memory in use) through 112 (single-chip application). Being equipped wide range of serial communications interfaces, they are also very well suited for communication gateways, protocol converters and embedded soft modems as well as many other general-purpose applications. Number of Components Used: Two KNOWX ARM BOARDS

Features of LPC2129

16/32-bit ARM7TDMI-S microcontroller in a 64 or 144 pin package. 16 kB on-chip Static RAM 128/256 kB on-chip Flash Program Memory. 128-bit wide interface/accelerator enables high speed 60 MHz operation. External 8, 16 or 32-bit bus (144 pin package only) In-System Programming (ISP) and In-Application Programming (IAP) via onchip boot-loader software. Flash programming takes 1 ms per 512 byte line. Single sector or full chip erase takes 400 ms.

Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of instruction execution. Two/four interconnected CAN interfaces with advanced acceptance filters. Four/eight channel (64/144 pin package) 10-bit A/D converter with conversion time as low as 2.44 ms. Two 32-bit timers (with 4 capture and 4 compare channels), PWM unit (6 outputs), Real Time Clock and Watchdog. Multiple serial interfaces including two UARTs (16C550), Fast I2C (400 kbits/s) and two SPIs. 60 MHz maximum CPU clock available from programmable on-chip PhaseLocked Loop. Vectored Interrupt Controller with configurable priorities and vector addresses. Up to forty-six (64 pin) and hundred-twelve (144 pin package) 5 V tolerant general purpose I/O pins. Up to 12 independent external interrupt pins available (EIN and CAP functions).

On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz. Two low power modes, Idle and Power-down. Processor wake-up from Power-down mode via external interrupt

6.1.2 LV-MaxSonar- EZ1 ULTRASONIC SENSOR

Figure 6.2: Pictorial view of LV-Maxsonar-ultresonic sonsor

Device description
With 2.5V - 5.5V power the LV-MaxSonar- EZ1 provides very short to longrange detection and ranging, in an incredibly small package. The LV-MaxSonar-EZ1 detects objects from 0-inches to 254-inches (6.45-meters) and provides sonar range information from 6-inches out to 254-inches with 1-inch resolution. Objects from 0inches to 6-inches range as 6-inches. The interface output formats included are pulse width output, analog voltage output, and serial digital output. Number of Components Used: Two

Features
Continuously variable gain for beam control and side lobe suppression Object detection includes zero range objects 2.5V to 5.5V supply with 2mA typical current draw Readings can occur up to every 50mS, (20-Hz rate) Free run operation can continually measure and output range information Triggered operation provides the range reading as desired All interfaces are active simultaneously Serial, 0 to Vcc

9600Baud, 81N Analog, (Vcc/512) / inch Pulse width, (147uS/inch) Learns ringdown pattern when commanded to start ranging Designed for protected indoor environments Sensor operates at 42KHz High output square wave sensor drive (double Vcc)

LV-MaxSonar-EZ1 Pin Out

GND Return for the DC power supply. GND (& Vcc) must be ripple and noise free for best operation. +5 V Vcc Operates on 2.5V - 5.5V. Recommended current capability of 3mA for 5V, and 2mA for 3V. TX The TX output delivers asynchronous serial with an RS232 format, except voltages are 0-Vcc. The output is an ASCII capital R, followed by three ASCII character digits representing the range in inches up to a maximum of 255, followed by a carriage return (ASCII 13). The baud rate is 9600, 8 bits, no parity, with one stop bit. Although the voltage of 0-Vcc is outside the RS232 standard, most RS232 devices have sufficient margin to read 0-Vcc serial data. If standard voltage level RS232 is desired, invert, and connect an RS232 converter such as a MAX232. Brown dot parts: When BW pin is held high the TX output sends a single pulse, suitable for low noise chaining (no serial data). RX This pin is internally pulled high. The EZ1 will continually measure range and output if the RX pin is left unconnected or held high. If held low the EZ1 will stop ranging. Bring high 20uS orMore for range reading

Figure6.3: Pin description of LV-Maxsonar sensor

ANOutputs analog voltage with a scaling factor of (Vcc/512) per inch. A supply of 5V yields ~9.8mV/in. and 3.3V yields ~6.4mV/in. The output is buffered and corresponds to the most recent range data. PW This pin outputs a pulse width representation of range. To calculate distance use the scale factor of 147uS per inch. BW *Leave open or hold low for serial output on the TX output.

6.1.3 MCP2551 Device description:

The MCP2551 is a high-speed CAN, fault-tolerant device that serves as the interface between a CAN protocol controller and the physical bus. The MCP2551 provides differential transmit and receive capability for the CAN protocol controller and

is fully compatible with the ISO-11898 standard, including 24V requirements. It will operate at speeds of up to 1Mb/s.Typically, each node in a CAN system must have a device to convert the digital signals generated by a CAN controller to signals suitable for transmission over the bus cabling (differential output). It also provides a buffer between the CAN controller and the high-voltage spikes that can be generated on the CAN bus by outside sources (EMI, ESD, electrical transients, etc.). Number of Components Used: Two

Figure (a)

Figure (b) Figure 6.4: (a) IC package and (b)block diagram

Transmitter Function
The CAN bus has two states: Dominant and Recessive. A dominant state occurs when the differential voltage between CANH and CANL is greater than a defined voltage (e.g.,1.2V). A recessive state occurs when the differential voltage is less than a defined voltage (typically 0V). The dominant and recessive states correspond to the low and high state of the TXD input pin, respectively. However, a dominant state initiated by another CAN node will override a recessive state on the CAN bus.

Maximum number of nodes

The MCP2551 CAN outputs will drive a minimum load of 45, allowing a maximum of 112 nodes to be connected (given a minimum differential input resistance of 20 k and a nominal termination resistor value of 120).

Receiver Function
The RXD output pin reflects the differential bus voltage between CANH and CANL. The low and high states of the RXD output pin correspond to the dominant and recessive states of the CAN bus, respectively.

Features
Supports 1 Mb/s operation Implements ISO-11898 standard physical layer requirements Suitable for 12V and 24V systems Externally-controlled slope for reduced RFI emissions Detection of ground fault (permanent dominant) on TXD input Power-on reset and voltage brown-out protection

An unpowered node or brown-out event will not disturb the CAN bus Low current standby operation Protection against damage due to short-circuit conditions (positive or negative battery voltage). Protection against high-voltage transients Automatic thermal shutdown protection Up to 112 nodes can be connected High noise immunity due to differential bus implementation Temperature ranges: Industrial (I): -40C to +85C Extended (E): -40C to +125C

6.1.4 Kalman Filter

The Kalman filter is a set of mathematical equations that provides an efficient computational (recursive) means to estimate the state of a process, in a way that minimizes the mean of the squared error. The filter is very powerful in several aspects: it supports estimations of past, present, and even future states, and it can do so even when the precise nature of the modeled system is unknown. In statistics, the Kalman filter is a mathematical method named after Rudolf E. Kalman. Its purpose is to use measurements that are observed over time that contain noise (random variations) and other inaccuracies, and produce values that tend to be closer to the true values of the measurements and their associated calculated values. The Kalman filter has many applications in technology, and is an essential part of the development of space and military technology. Perhaps the most commonly used type of very simple Kalman filter is the phase-locked loop, which is now ubiquitous in FM radios and most electronic communications equipment. Extensions and generalizations to the method have also been developed.

The Kalman filter produces estimates of the true values of measurements and their associated calculated values by predicting a value, estimating the uncertainty of the predicted value, and computing a weighted average of the predicted value and the measured value. The most weight is given to the value with the least uncertainty. The estimates produced by the method tend to be closer to the true values than the original measurements because the weighted average has a better estimated uncertainty than either of the values that went into the weighted average. From a theoretical standpoint, the Kalman filter is an algorithm for efficiently doing exact inference in a linear dynamical system, which is a Bayesian model similar to a hidden Markov model but where the state space of the latent variables is continuous and where all latent and observed variables have a Gaussian distribution (often a multivariate Gaussian distribution). The Kalman filter uses a system's dynamics model (i.e., physical laws of motion), known control inputs to that system, and measurements (such as from sensors) to form an estimate of the system's varying quantities (its state) that is better than the estimate obtained by using any one measurement alone. As such, it is a common sensor fusion algorithm. All measurements and calculations based on models are estimates to some degree. Noisy sensor data, approximations in the equations that describe how a system changes, and external factors that are not accounted for introduce some uncertainty about the inferred values for a system's state. The Kalman filter averages a prediction of a system's state with a new measurement using a weighted average. The purpose of the weights is that values with better (i.e., smaller) estimated uncertainty is "trusted" more. The weights are calculated from the covariance, a measure of the estimated uncertainty of the prediction of the system's state. The result of the weighted average is a new state estimate that lies in between the predicted and measured state, and has a better estimated uncertainty than either alone. This process is repeated every time step, with the new

estimate and its covariance informing the prediction used in the following iteration. This means that the Kalman filter works recursively and requires only the last "best guess" not the entire history - of a system's state to calculate a new state. When performing the actual calculations for the filter (as discussed below), the state estimate and covariances are coded into matrices to handle the multiple dimensions involved in a single set of calculations. This allows for representation of linear relationships between different state variables (such as position, velocity, and acceleration) in any of the transition models or covariances. The Kalman filter is used in sensor fusion and data fusion. Typically real time systems produce multiple sequential measurements rather than making a single measurement to obtain the state of the system. These multiple measurements are then combined mathematically to generate the system's state at that time instant. As an example application, consider the problem of determining the precise location of a truck. The truck can be equipped with a GPS unit that provides an estimate of the position within a few meters. The GPS estimate is likely to be noisy; readings 'jump around' rapidly, though always remaining within a few meters of the real position. The truck's position can also be estimated by integrating its speed and direction over time, determined by keeping track of the amount the accelerator is depressed and how much the steering wheel is turned. This is a technique known as dead reckoning. Typically, dead reckoning will provide a very smooth estimate of the truck's position, but it will drift over time as small errors accumulate. Additionally, the truck is expected to follow the laws of physics, so its position should be expected to change proportionally to its velocity. In this example, the Kalman filter can be thought of as operating in two distinct phases: predict and update. In the prediction phase, the truck's old position will be modified according to the physical laws of motion (the dynamic or "state transition" model) plus any changes produced by the accelerator pedal and steering wheel. Not only

will a new position estimate be calculated, but a new covariance will be calculated as well. Perhaps the covariance is proportional to the speed of the truck because we are more uncertain about the accuracy of the dead reckoning estimate at high speeds but very certain about the position when moving slowly. Next, in the update phase, a measurement of the truck's position is taken from the GPS unit. Along with this measurement comes some amount of uncertainty, and its covariance relative to that of the prediction from the previous phase determines how much the new measurement will affect the updated prediction. Ideally, if the dead reckoning estimates tend to drift away from the real position, the GPS measurement should pull the position estimate back towards the real position but not disturb it to the point of becoming rapidly changing and noisy. Data fusion using a Kalman filter can assist computers to track objects in videos with low latency. The tracking of objects is a dynamic problem, using data from sensor and camera images that always suffer from noise. This can sometimes be reduced by using higher quality cameras and sensors but can never be eliminated, so it is often desirable to use a noise reduction method. The iterative predictor-corrector nature of the Kalman filter can be helpful, because at each time instance only one constraint on the state variable need be considered. This process is repeated, considering a different constraint at every time instance. All the measured data are accumulated over time and help in predicting the state. Video can also be pre-processed, perhaps using a segmentation technique, to reduce the computation and hence latency. The Kalman filter is a recursive estimator. This means that only the estimated state from the previous time step and the current measurement are needed to compute the estimate for the current state. In contrast to batch estimation techniques, no history of observations and/or estimates is required. In what follows, the notation

\hat{\textbf{x}}_{n|m} represents the estimate of \textbf{x} at time n given observations up to, and including at time m.

The state of the filter is represented by two variables: * \hat{\textbf{x}}_{k|k}, the a posteriori state estimate at time k given observations up to and including at time k; * \textbf{P}_{k|k}, the a posteriori error covariance matrix (a measure of the estimated accuracy of the state estimate). The Kalman filter can be written as a single equation, however it is most often conceptualized as two distinct phases: Predict and Update. The predict phase uses the state estimate from the previous timestep to produce an estimate of the state at the current timestep. This predicted state estimate is also known as the a priori state estimate because, although it is an estimate of the state at the current timestep, it does not include observation information from the current timestep. In the update phase, the current a priori prediction is combined with current observation information to refine the state estimate. This improved estimate is termed the a posteriori state estimate. Typically, the two phases alternate, with the prediction advancing the state until the next scheduled observation, and the update incorporating the observation. However, this is not necessary; if an observation is unavailable for some reason, the update may be skipped and multiple prediction steps performed. Likewise, if multiple independent observations are available at the same time, multiple update steps may be performed (typically with different observation matrices Hk).

Predict
Predicted (a priori) state estimate \hat{\textbf{x}}_{k|k-1} = \textbf{F}_{k}\hat{\textbf{x}}_{k-1|k-1} + \textbf{B}_{k} \textbf{u}_{k} Predicted (a priori) estimate covariance

\textbf{P}_{k|k-1} = \textbf{F}_{k} \textbf{P}_{k-1|k-1} \textbf{F}_{k}^{\text{T}} + \textbf{Q}_{k} [edit] Update Innovation or measurement residual \tilde{\textbf{y}}_k = \textbf{z}_k - \textbf{H}_k\hat{\textbf{x}}_{k|k-1} Innovation (or residual) covariance \textbf{S}_k = \textbf{H}_k \textbf{P}_{k|k-1} \textbf{H}_k^\text{T} + \textbf{R}_k Optimal Kalman gain \textbf{K}_k = \textbf{P}_{k|k1}\textbf{H}_k^\text{T}\textbf{S}_k^{-1} Updated (a posteriori) state estimate \hat{\textbf{x}}_{k|k} = \hat{\textbf{x}}_{k|k-1} + \textbf{K}_k\tilde{\textbf{y}}_k Updated (a posteriori) estimate covariance \textbf{H}_k) \textbf{P}_{k|k-1} The formula for the updated estimate and covariance above is only valid for the optimal Kalman gain.Usage of other gain values require a more complex formula found in the derivations section. \textbf{P}_{k|k} = (I - \textbf{K}_k

6.2 Software Development

In this module we will be using an Integrated Development Environment from Keil Electronic. This IDE is called u VISION (pronounced Micro Vision) and versions already exist for other popular microcontrollers including the 8051 and the Infineon C16X family. u VISION successfully integrates project management, editor, compiler and debugger in one seamless front-end. Although we are concentrating on the LPC2000 family in this book, the Keil ARM tools can be used for any other ARM7 based microcontroller.

6.2.1 The Compiler

The u VISION development environment can be used with several different compiler tools. These include the ARM ADS compiler, the GNU compiler and Keils own ARM compiler. The Keil u VISION ( u VISION) IDE is designed to support several compilers, the Gnu C compiler, The ARM development suite and the Keil ARM compiler. Before compiling make sure you have the GNU compiler selected. This is done by activating the project workspace, right clicking and selecting manage components. In this dialog select the Folders/extensions tab and make sure the Keil ARM tools box is selected

6.2.2 Keil Toolset

Step1: Open Kiel UVISION3.

Step2: Add user manual.

Step3: Create new file.

step4: Select LPC2129.

step5: Add code to source file and build target

step6: Using simulator.

Step7:

Using PHILIPS LPC2000 Flash Utility dump the hex file of

the code.

CHAPTER 7

APPLICATIONS
7.1 Real time application
Used as a Warning System to avoid Collision in National Highways. Used by Police to Track the speed of the approaching vehicles. Used to detect an object in Extreme conditions like Fog and misty areas. Can be implemented in Robotic Applications. Can be used in large vehicles like Trucks and buses Can be implemented in Aircraft and aerospace electronics Can be used in Passenger and cargo trains Can be implemented in Maritime electronics..

CHAPTER 8

RESULTS

Design Flow 8.1 Transmitter Part

2 Ultrasonic sensors are connected to ADC. Communication is through CAN1.

8.2 Receiver Part

Communication is through CAN2. After receiving the CAN values, it will display on LCD. If exceeds certain limit, warnings will be given.

8.3 Execution Model

First select the pins of ADC, CAN and UART channels using PINSEL0 and PINSEL1 registers in LPC2129. Configure 9600 baud rate for serial ports with 8 bit communication mode and 125 Kbps for CAN channel If time is required then we can use internal RTC by setting control registers. ADC in ARM7 can be configured by using ADCR register and data can be converted in to ADDR register. Now connect two ultrasonic sensors to the ADC of ARM7 controllers and place them at front and rear ends. Whatever the data is coming from these sensors monitor it and send continously using CAN1 channel to CAN2 through bus. Based on the data coming to CAN2 channel through the bus, the controller will decide what operation should perform.

If any object is very near to the vehicle then the vehicle will be stopped automatically. By using Kalman algorithm we can find out the relative speed between the near by vehicles and monitor it continously. All these information we are displaying on the lcd and at the same time we can send to a PC.

7.3 PICTORIAL VIEW

CHAPTER 9

CONCLUSION
This project CAN BASED ACCIDENT AVOIDANCE SYSTEM is intended for secure and smooth journey. The car/ vehicle itself is aware of its movement. If the driver himself is not concentrating on driving or any other parameters, which may cause damage to vehicle as well a life, this intelligent car/ vehicle warn the driver regarding the danger ahead. As the value of a human life is countless times more than the cost of this project, we are proud to be behind the success of this project.

CHAPTER 10

FUTURE ENHANCEMENT
As for the rear end, side-end end collision avoidance subsystem can be adopted with the use of the currently available ultrasonic sensors for vehicles. Further, the relative speed between two cars can be estimated by applying a one-dimension Kalman filter [5] with great efficiency. From experimental data, a D/V curve can be further obtained to reliably generate a warning signal in advance of the accidental collision. As the car in traffic with pretty low speed or in a waiting state at the intersection, the warning signals should be terminated after a certain time since no collision warning is required under such circumstances.

SOURCE CODE
#include <LPC21xx.H> void CAN1_TX(unsigned int); void CAN2_RX(void); void Delay(unsigned int itime) //Here we are generating { unsigned int i,j; for(i=0;i<itime;i++) for(j=0;j<1500;j++); } //=============================================== void lcd_init() { lcd_cmd(0x20); lcd_cmd(0x28); lcd_cmd(0x0C); lcd_cmd(0x01); lcd_cmd(0x06); lcd_cmd(0x80); } void lcd_cmd(unsigned char cmd) { unsigned char temp; temp = cmd; cmd &= 0xF0; cmd = cmd << 6; IOCLR0 = 0x00003C00; IOSET0 = cmd; IOCLR1 = 0x03000000; IOSET1 = 0x02000000; Delay(50); IOCLR1 = 0x02000000; Delay(50); cmd = temp; cmd &= 0x0F; cmd = cmd << 10; IOCLR0 = 0x00003C00; IOSET0 = cmd; IOCLR1 = 0x03000000; ms delay

//Display on/off control //Clear Display //Entry Mode set //sets the display position to starting

//left shifted by 6 times //Clear the Data Pins //Register Select Clear For Command //Enable Set //Enable Clear

//left shifted by 10 times //Clear the Data Pins //Register Select Clear For Command

IOSET1 = 0x02000000; Delay(50); IOCLR1 = 0x02000000; Delay(50);

//Enable Set //Enable Clear

} //=============================================== //THIS IS THE FUNCTION FOR WRITE THE DATAS IN DATA REG void lcd_char(unsigned int ch) { unsigned char temp; temp = ch; ch &= 0xF0; ch = ch << 6; //left shifted by 6 times IOCLR0 = 0x00003C00; //Clear the Data Pins IOSET0 = ch; IOCLR1 = 0x03000000; //Register Select Set For Data IOSET1 = 0x03000000; //Enable Set Delay(5); IOCLR1 = 0x02000000; //Enable Clear Delay(5); ch = temp; ch &= 0x0F; ch = ch << 10; //left shifted by 10 times IOCLR0 = 0x00003C00; //Clear the Data Pins IOSET0 = ch; IOCLR1 = 0x03000000; //Register Select Set For Data IOSET1 = 0x03000000; //Enable Set Delay(5); IOCLR1 = 0x02000000; //Enable Clear Delay(5); } //=============================================== //DISPLAY STRING OF DATA ON LCD void lcd_print(unsigned char *str) { while(*str) lcd_char(*str++); //Display String Data On LCD } /*******************************************************/ void Delay1(unsigned int itime) { unsigned int i,k=0; for(i=0;i<itime;i++) for(k=0;k<1000;k++); }

/*******************************************************/ int main(void) { unsigned int ch; IODIR0=0x00003C00; IODIR1=0x03000000; PINSEL1=0x00054000; lcd_init(); lcd_print("CAN ACCIDENT"); lcd_cmd(0xC0); lcd_print("AVOIDENCE SYSTEM"); Delay1(2000); Delay1(2000); Delay1(2000); Delay1(2000); lcd_cmd(0x01); /******************CAN1 intialization****************/ C1MOD=1;/*Reset CAN1 controller*/ C1BTR=0x001C001D;/*Set baud Rate for CAN*/ C1MOD=0;/*Enable CAN1 controller*/ lcd_cmd(0x01); lcd_print("CAN1 ENABLED"); Delay1(200); Delay1(200); Delay1(200); /******************CAN2 intialization***************/ C2MOD=1;/*Reset CAN2 controller*/ C2BTR=0x001C001D;/*Set baud Rate for CAN2*/ C2MOD=0;/*Enable CAN2 controller*/ lcd_cmd(0x01); lcd_print("CAN2 ENABLED"); Delay1(2000); Delay1(2000); Delay1(2000);

lcd_cmd(0x01); while(1) { if(IOPIN0 & 0x20000000 ) ch=0x01; else ch=0x02; if(ch==0x01 || ch==0x02) { CAN1_TX(ch); CAN2_RX(); } } }

//po.29

void CAN1_TX(unsigned int ch) { if(C1SR & 0x00000004) { C1TFI1=0x00040000;/*Set TX data length*/ C1TID1=C1RID;/*Set TX Identifier*/ C1TDA1 =ch; /*Load the Data to TX1 buffer*/ C1CMR=0x21; /*send the Data*/ Delay1(2000); } } void CAN2_RX() { int value; C2CMR=0X04; lcd_cmd(0x01); value=C2RDA; if(value==0x01) { lcd_cmd(0x01); lcd_cmd(0x80); lcd_print("OBSTACLE FAR"); lcd_cmd(0xC0); lcd_print(" ROAD CLEAR "); Delay1(2000);

Delay1(2000); Delay1(2000); } if(value==0x02) { lcd_cmd(0x01); lcd_cmd(0x80); lcd_print(" OBSTACLE NEAR"); lcd_cmd(0xC0); lcd_print(" GO SLOW "); Delay1(2000); Delay1(2000); Delay1(2000); } }

12.REFERENCES Books
[1]. ARM7TDMI datasheet ARM [2]. LPC2119/2129/2194/2292/2294 User Manual Philips [3]. ARM System on chip architecture Steve Furber [4]. Architecture Reference Manual David Seal [5]. ARM System developers guide Andrew N. Sloss, Domonic Symes, [6]. Chris Wright [7]. Micro C/OS-II Jean J. Labrosse GCC The complete reference Arthur Griffith

Websites
[1]. http://www.arm.com [2]. http://www.philips.com [3]. http://www.lpc2000.com [4]. http://www.semiconductors.philips.com/ [5]. http://ieeexplore.ieee.org [6]. http://ww.hitex.co.uk [7]. http://www.keil.co.uk [8]. http://www.ucos-ii.com [9]. http://www.ristancase.com [10]. http://gcc.gnu.org/onlinedocs/gcc/Evaluation Boards And Modules [11]. http://www.knox.com