mnemonic

InstructionSetSummary

13.2 InstructionSetSummary
Table138liststheC3xinstructionsetinalphabeticalorder.Eachtableentry providestheinstructionmnemonic,description,andoperation.

Table138. InstructionSetSummary
Mnemonic ABSF ABSI ADDC ADDC3 ADDF ADDF3 ADDI ADDI3 AND AND3 ANDN ANDN3 ASH Description Absolutevalueofafloatingpointnumber Absolutevalueofaninteger Addintegerswithcarry Addintegerswithcarry(3operand) Addfloatingpointvalues Addfloatingpointvalues(3operand) Addintegers Addintegers(3operand) BitwiselogicalAND BitwiselogicalAND(3operand) BitwiselogicalANDwithcomplement BitwiselogicalANDN(3operand) Arithmeticshift Operation |src| Rn |src|Dreg src+Dreg+C Dreg src1+src2+C Dreg src+Rn Rn src1+src2 Rn src+Dreg Dreg src1+src2+Dreg DregANDsrcDreg src1ANDsrc2Dreg DregANDsrcDreg src1ANDsrc2Dreg Ifcount0: (ShiftedDregleftbycount) Dreg Else: (ShiftedDregrightby|count|)Dreg ASH3 Arithmeticshift(3operand) Ifcount0: (Shiftedsrcleftbycount)Dreg Else: (Shiftedsrcrightby|count|)Dreg
Legend: ARn C Csrc count cond Daddr Dreg GIE N PC RC auxiliaryregistern(AR7AR0) carrybit conditionalbranchaddressingmodes shiftvalue(generaladdressingmodes) conditioncode destinationmemoryaddress registeraddress(anyregister) globalinterruptenableregister anytrapvector027 programcounter repeatcounterregister RE RM Rn RS SP Sreg ST src src1 src2 TOS repeatinterruptregister repeatmodebit registeraddress(R7R0) repeatstartregister stackpointer registeraddress(anyregister) statusregister generaladdressingmodes 3operandaddressingmodes 3operandaddressingmodes topofstack

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Table138. InstructionSetSummary(Continued)
Mnemonic Bcond Description Branchconditionally(standard) Operation Ifcond=true: IfCsrcisaregister,CsrcPC IfCsrcisavalue,Csrc+PCPC Else,PC+1PC BcondD Branchconditionally(delayed) Ifcond=true: IfCsrcisaregister,CsrcPC IfCsrcisavalue,Csrc+PC+3PC Else,PC+1PC BR BRD CALL Branchunconditionally(standard) Branchunconditionally(delayed) Callsubroutine Value PC Value PC PC+1TOS ValuePC CALLcond Callsubroutineconditionally Ifcond=true: PC+1 TOS IfCsrcisaregister,CsrcPC IfCsrcisavalue,Csrc+PC PC Else,PC+1PC CMPF CMPF3 Comparefloatingpointvalues Comparefloatingpointvalues (3operand) CMPI CMPI3
Legend:

SetflagsonRnsrc Setflagsonsrc1src2

Compareintegers Compareintegers(3operand)
ARn C Csrc count cond Daddr Dreg GIE N PC RC auxiliaryregistern(AR7AR0) carrybit conditionalbranchaddressingmodes shiftvalue(generaladdressingmodes) conditioncode destinationmemoryaddress registeraddress(anyregister) globalinterruptenableregister anytrapvector027 programcounter repeatcounterregister

SetflagsonDregsrc Setflagsonsrc1src2
RE RM Rn RS SP Sreg ST src src1 src2 TOS repeatinterruptregister repeatmodebit registeraddress(R7R0) repeatstartregister stackpointer registeraddress(anyregister) statusregister generaladdressingmodes 3operandaddressingmodes 3operandaddressingmodes topofstack

AssemblyLanguageInstructions

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mnemonic

InstructionSetSummary

Table138. InstructionSetSummary(Continued)
Mnemonic DBcond Description Decrementandbranchconditionally (standard) Operation ARn1ARn Ifcond=trueandARn0: IfCsrcisaregister,CsrcPC IfCsrcisavalue,Csrc+PC+1PC Else,PC+1PC DBcondD Decrementandbranchconditionally (delayed) ARn1ARn Ifcond=trueandARn 0: IfCsrcisaregister,CsrcPC IfCsrcisavalue,Csrc+PC+3PC Else,PC+1PC FIX FLOAT IACK IDLE Convertfloatingpointvaluetointeger Convertintegertofloatingpointvalue Interruptacknowledge Idleuntilinterrupt Fix(src)Dreg Float(src)Rn Dummyreadofsrc IACKtoggledlow,thenhigh PC+1 PC Idleuntilnextinterrupt IDLE2 LDE LDF LDFcond Lowpoweridle Loadfloatingpointexponent Loadfloatingpointvalue Loadfloatingpointvalueconditionally Idleuntilnextinterruptstoppinginternalclocks src(exponent) Rn(exponent) srcRn Ifcond=true,srcRn Else,Rnisnotchanged LDFI LDI
Legend:

Loadfloatingpointvalue,interlocked Loadinteger
ARn C Csrc count cond Daddr Dreg GIE N PC RC auxiliaryregistern(AR7AR0) carrybit conditionalbranchaddressingmodes shiftvalue(generaladdressingmodes) conditioncode destinationmemoryaddress registeraddress(anyregister) globalinterruptenableregister anytrapvector027 programcounter repeatcounterregister

SignalinterlockedoperationsrcRn srcDreg
RE RM Rn RS SP Sreg ST src src1 src2 TOS repeatinterruptregister repeatmodebit registeraddress(R7R0) repeatstartregister stackpointer registeraddress(anyregister) statusregister generaladdressingmodes 3operandaddressingmodes 3operandaddressingmodes topofstack

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Table138. InstructionSetSummary(Continued)
Mnemonic LDIcond Description Loadintegerconditionally Operation Ifcond=true,srcDreg Else,Dregisnotchanged LDII LDM LDP LOPOWER LSH Loadinteger,interlocked Loadfloatingpointmantissa Loaddatapagepointer Divideclockby16 Logicalshift SignalinterlockedoperationsrcDreg src(mantissa)Rn(mantissa) srcdatapagepointer H1/16H1 Ifcount0: (Dregleftshiftedbycount) Dreg Else: (Dregrightshiftedby|count|)Dreg LSH3 Logicalshift(3operand) Ifcount0: (srcleftshiftedbycount)Dreg Else: (srcrightshiftedby|count|)Dreg MAXSPEED MPYF MPYF3 MPYI MPYI3 NEGB NEGF NEGI
Legend:

Restoreclocktoregularspeed Multiplyfloatingpointvalues Multiplyfloatingpointvalue(3operand) Multiplyintegers Multiplyintegers(3operand) Negateintegerwithborrow Negatefloatingpointvalue Negateinteger

H1/16H1 srcRnRn src1 src2Rn srcDregDreg src1src2Dreg 0srcCDreg 0srcRn 0srcDreg

RE RM Rn RS SP Sreg ST src src1 src2 TOS repeatinterruptregister repeatmodebit registeraddress(R7R0) repeatstartregister stackpointer registeraddress(anyregister) statusregister generaladdressingmodes 3operandaddressingmodes 3operandaddressingmodes topofstack

ARn C Csrc count cond Daddr Dreg GIE N PC RC

auxiliaryregistern(AR7AR0) carrybit conditionalbranchaddressingmodes shiftvalue(generaladdressingmodes) conditioncode destinationmemoryaddress registeraddress(anyregister) globalinterruptenableregister anytrapvector027 programcounter repeatcounterregister

AssemblyLanguageInstructions

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mnemonic

InstructionSetSummary

Table138. InstructionSetSummary(Continued)
Mnemonic NOP NORM NOT OR OR3 POP POPF PUSH PUSHF RETIcond Description Nooperation Normalizefloatingpointvalue Bitwiselogicalcomplement BitwiselogicalOR BitwiselogicalOR(3operand) Popintegerfromstack Popfloatingpointvaluefromstack Pushintegeronstack Pushfloatingpointvalueonstack Returnfrominterruptconditionally Operation ModifyARnifspecified Normalize(src)Rn srcDreg DregORsrcDreg src1ORsrc2Dreg *SPDreg *SPRn Sreg *++SP Rn *++SP Ifcond=trueormissing: *SP PC 1 ST(GIE) Else,continue RETScond Returnfromsubroutineconditionally Ifcond=trueormissing: *SP PC Else,continue RND ROL ROLC ROR RORC
Legend:

Roundfloatingpointvalue Rotateleft Rotateleftthroughcarry Rotateright Rotaterightthroughcarry

ARn C Csrc count cond Daddr Dreg GIE N PC RC auxiliaryregistern(AR7AR0) carrybit conditionalbranchaddressingmodes shiftvalue(generaladdressingmodes) conditioncode destinationmemoryaddress registeraddress(anyregister) globalinterruptenableregister anytrapvector027 programcounter repeatcounterregister

Round(src) Rn Dregrotatedleft1bit Dreg Dregrotatedleft1bitthroughcarryDreg Dregrotatedright1bit Dreg Dregrotatedright1bitthroughcarry Dreg

RE RM Rn RS SP Sreg ST src src1 src2 TOS repeatinterruptregister repeatmodebit registeraddress(R7R0) repeatstartregister stackpointer registeraddress(anyregister) statusregister generaladdressingmodes 3operandaddressingmodes 3operandaddressingmodes topofstack

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Table138. InstructionSetSummary(Continued)
Mnemonic RPTB Description Repeatblockofinstructions Operation src RE 1 ST(RM) NextPCRS RPTS Repeatsingleinstruction src RC 1ST(RM) NextPCRS NextPCRE SIGI Signal,interlocked Signalinterlockedoperation Waitforinterlockacknowledge Clearinterlock STF STFI Storefloatingpointvalue Storefloatingpointvalue,interlocked RnDaddr RnDaddr Signalendofinterlockedoperation STI STII Storeinteger Storeinteger,interlocked SregDaddr SregDaddr Signalendofinterlockedoperation SUBB SUBB3 SUBC Subtractintegerswithborrow Subtractintegerswithborrow(3operand) Subtractintegersconditionally DregsrcCDreg src1src2CDreg IfDregsrc0: [(Dreg src)<<1]OR1Dreg Else,Dreg<<1Dreg SUBF SUBF3
Legend:

Subtractfloatingpointvalues Subtractfloatingpointvalues(3operand)
ARn C Csrc count cond Daddr Dreg GIE N PC RC auxiliaryregistern(AR7AR0) carrybit conditionalbranchaddressingmodes shiftvalue(generaladdressingmodes) conditioncode destinationmemoryaddress registeraddress(anyregister) globalinterruptenableregister anytrapvector027 programcounter repeatcounterregister

RnsrcRn src1src2Rn
RE RM Rn RS SP Sreg ST src src1 src2 TOS repeatinterruptregister repeatmodebit registeraddress(R7R0) repeatstartregister stackpointer registeraddress(anyregister) statusregister generaladdressingmodes 3operandaddressingmodes 3operandaddressingmodes topofstack

AssemblyLanguageInstructions

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mnemonic

InstructionSetSummary

Table138. InstructionSetSummary(Continued)
Mnemonic SUBI SUBI3 SUBRB SUBRF SUBRI SWI TRAPcond Description Subtractintegers Subtractintegers(3operand) Subtractreverseintegerwithborrow Subtractreversefloatingpointvalue Subtractreverseinteger Softwareinterrupt Trapconditionally Operation DregsrcDreg src1src2Dreg srcDregCDreg srcRn Rn srcDregDreg Performemulatorinterruptsequence Ifcond=trueormissing: NextPC*++SP TrapvectorNPC 0ST(GIE) Else,continue TSTB TSTB3 XOR XOR3
Legend:

Testbitfields Testbitfields(3operand) BitwiseexclusiveOR BitwiseexclusiveOR(3operand)

ARn C Csrc count cond Daddr Dreg GIE N PC RC auxiliaryregistern(AR7AR0) carrybit conditionalbranchaddressingmodes shiftvalue(generaladdressingmodes) conditioncode destinationmemoryaddress registeraddress(anyregister) globalinterruptenableregister anytrapvector027 programcounter repeatcounterregister

DregANDsrc src1ANDsrc2 DregXORsrcDreg src1XORsrc2Dreg

RE RM Rn RS SP Sreg ST src src1 src2 TOS repeatinterruptregister repeatmodebit registeraddress(R7R0) repeatstartregister stackpointer registeraddress(anyregister) statusregister generaladdressingmodes 3operandaddressingmodes 3operandaddressingmodes topofstack

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13.3 ParallelInstructionSetSummary
Table139 lists the C3x instruction set in alphabetical order. Each table entryshowstheinstructionmnemonic,description,andoperation.Referto Section13.1forafunctionallistingoftheinstructionsandindividualinstruc tiondescriptions.

Table139. ParallelInstructionSetSummary
(a) Parallelarithmeticwithstoreinstructions Mnemonic ABSF || STF ABSI || STI ADDF3 || STF ADDI3 || STI AND3 || STI ASH3 || STI || Arithmeticshift BitwiselogicalAND || Addinteger || Addfloatingpointvalue || Absolutevalueofaninteger || Description Absolutevalueofafloatingpoint || Operation |src2|dst1 src3dst2 |src2|dst1 src3dst2 src1+src2dst1 src3dst2 src1+src2dst1 src3dst2 src1ANDsrc2dst1 src3dst2 (src2<<count) dst1 src3dst2 (src2>>|count|)dst1 || FIX || STI FLOAT || STF
Legend: count registeraddr(R7R0) dst1 registeraddr(R7R0) dst2 indirectaddr(disp=0,1,IR0,IR1) op1,op2,op4,andop5 Anytwooftheseoperandsmustbe specifiedusingregisteraddr;theremaining twomustbespecifiedusingindirect. op3 op6 src1 src2 src3

Ifcount0:

Else: src3dst2 src3dst2 Float(src2)dst1 || src3dst2

Convertfloatingpointvaluetointeger

Fix (src2)dst1 ||

Convertintegertofloatingpointvalue

registeraddr(R0orR1) registeraddr(R2orR3) registeraddr(R7R0) indirectaddr(disp=0,1,IR0,IR1) registeraddr(R7R0)

ArchitecturalOverview

1317

mnemonic

ParallelInstructionSetSummary

Table139.ParallelInstructionSetSummary(Continued)
(a) Parallelarithmeticwithstoreinstructions(Continued) Mnemonic LDF || STF LDI || STI LSH3 || STI || Logicalshift Loadinteger || Description Loadfloatingpointvalue || Operation src2dst1 src3 dst2 src2 dst1 src3dst2 src2<<countdst1 src3dst2 src2>>|count|dst1 || MPYF3 || STF MPYI3 || STI NEGF || STF NEGI || STI NOT || STI OR3 || STI STF || STF STI || STI
count registeraddr(R7R0) dst1 registeraddr(R7R0) dst2 indirectaddr(disp=0,1,IR0,IR1) op1,op2,op4,andop5 Anytwooftheseoperandsmustbe specifiedusingregisteraddr;theremaining twomustbespecifiedusingindirect. op3 op6 src1 src2 src3 Legend:

Ifcount0:

Else: src3dst2 src1xsrc2dst1 || Multiplyinteger || Negatefloatingpointvalue || Negateinteger || Complement || BitwiselogicalOR || Storefloatingpointvalue || Storeinteger || src3dst2 src1xsrc2dst1 src3dst2 0 src2dst1 src3dst2 0src2dst1 src3 dst2 src1dst1 src3dst2 src1ORsrc2 dst1 src3dst2 src1dst1 src3dst2 src1dst1 src3dst2

Multiplyfloatingpointvalue

registeraddr(R0orR1) registeraddr(R2orR3) registeraddr(R7R0) indirectaddr(disp=0,1,IR0,IR1) registeraddr(R7R0)

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Table139.ParallelInstructionSetSummary(Continued)
(a) Parallelarithmeticwithstoreinstructions(Continued) Mnemonic SUBF3 || STF SUBI3 || STI XOR3 || STI BitwiseexclusiveOR || Subtractinteger || Description Subtractfloatingpointvalue || Operation src1src2dst1 src3dst2 src1src2dst1 src3dst2 src1XORsrc2dst1 src3dst2

(b) Parallelloadinstructions Mnemonic LDF || LDF LDI || LDI Loadinteger || Description Loadfloatingpointvalue || Operation src2dst1 src4dst2 src2dst1 src4dst2

(c) Parallelmultiplyandadd/subtractinstructions Mnemonic MPYF3 || ADDF3 MPYF3 || SUBF3 MPYI3 || ADDI3 MPYI3 || SUBI3
Legend: count registeraddr(R7R0) dst1 registeraddr(R7R0) dst2 indirectaddr(disp=0,1,IR0,IR1) op1,op2,op4,andop5 Anytwooftheseoperandsmustbe specifiedusingregisteraddr;theremaining twomustbespecifiedusingindirect. op3 op6 src1 src2 src3

Description Multiplyandaddfloatingpointvalue

Operation op1xop2op3 || op4+op5op6 op1xop2op3 || op4op5op6 op1xop2op3 || op4+op5op6 op1xop2op3 || op4op5op6

Multiplyandsubtractfloatingpointvalue

Multiplyandaddinteger

Multiplyandsubtractinteger

registeraddr(R0orR1) registeraddr(R2orR3) registeraddr(R7R0) indirectaddr(disp=0,1,IR0,IR1) registeraddr(R7R0)

AssemblyLanguageInstructions

1319