Logic Design Lab
Logic Design Lab
(Common to EC/TC/EE/IT/BM/ML)
Sub Code : 10ESL38 Hrs/ Week : 03 Total Hrs. : IA Marks : 25 Exam Hours : 03 Exam Marks : 50
NOTE: Use discrete components to test and verify the logic gates. LabView can be used for designing the gates along with the above. 1. Simplification, realization of Boolean expressions using logic gates/Universal gates. 2. Realization of Half/Full adder and Half/Full Subtractors using logic gates. 3. (i) Realization of parallel adder/Subtractors using 7483 chip (ii) BCD to Excess-3 code conversion and vice versa. 4. Realization of Binary to Gray code conversion and vice versa 5. MUX/DEMUX use of 74153, 74139 for arithmetic circuits and code converter. 6. Realization of One/Two bit comparator and study of 7485 magnitude comparator. 7. Use of a) Decoder chip to drive LED display and b) Priority encoder. 8. Truth table verification of Flip-Flops: (i) JK Master slave (ii) T type and (iii) D type. 9. Realization of 3 bit counters as a sequential circuit and MOD N counter design (7476, 7490, 74192, 74193). 10. Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using 74S95. 11. Wiring and testing Ring counter/Johnson counter. 12. Wiring and testing of Sequence generator.