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VHDL

The document describes VHDL code implementations for basic digital logic circuits including a half adder, full adder using two half adders, ripple carry adder, and carry lookahead adder. Testbenches are also provided to simulate and test the behavior of each circuit.

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sachinpn
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184 views

VHDL

The document describes VHDL code implementations for basic digital logic circuits including a half adder, full adder using two half adders, ripple carry adder, and carry lookahead adder. Testbenches are also provided to simulate and test the behavior of each circuit.

Uploaded by

sachinpn
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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VHDL

y Write VHDL program to model the following and simulate it using MODELSIM 1) Half adder LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HA IS PORT(A,B:IN STD_LOGIC; S,C:OUT STD_LOGIC); END HA; ARCHITECTURE HA_A OF HA IS BEGIN S<=A XOR B; C<= A AND B; END HA_A; TESTBENCH LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TB_HA IS END TB_HA; ARCHITECTURE TB_HA1 OF TB_HA IS COMPONENT HA PORT(A,B: IN STD_LOGIC; S,C:OUT STD_LOGIC); END COMPONENT; SIGNAL A_T,B_T,C_T,S_T:STD_LOGIC; BEGIN H: COMPONENT HA PORT MAP (A_T,B_T,S_T,C_T); A_T<='0','1' AFTER 20NS,'0' AFTER 40NS; B_T<='0','1' AFTER 10NS,'0' AFTER 20NS,'1' AFTER 30NS; END TB_HA1;

2)

Full Adder using two half adders LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FA IS PORT(A,B,CIN:IN STD_LOGIC; S,C:OUT STD_LOGIC); END FA; ARCHITECTURE FA_A OF FA IS COMPONENT HA IS PORT (A,B:IN STD_LOGIC; S,C:OUT STD_LOGIC); END COMPONENT; COMPONENT OR_GATE IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; SIGNAL S1,C1,C2:STD_LOGIC; BEGIN H1:COMPONENT HA PORT MAP(A,B,S1,C1); H2:COMPONENT HA PORT MAP(S1,CIN,S,C2); H3:COMPONENT OR_GATE PORT MAP(C1,C2,C); END FA_A; TESTBENCH LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TB_RCA IS END TB_RCA; ARCHITECTURE TB_RCA1 OF TB_RCA IS COMPONENT RCA PORT(A,B:IN STD_LOGIC_VECTOR(1 DOWNTO 0); S:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); C:OUT STD_LOGIC); END COMPONENT; SIGNAL A_T,B_T,S_T: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL C_T: STD_LOGIC; BEGIN

H: COMPONENT RCA PORT MAP(A_T,B_T,S_T,C_T); A_T<= "01"; B_T<= "01"; END TB_RCA1;

3) Ripple Carry Adder LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY RCA IS PORT(A,B:IN STD_LOGIC_VECTOR(1 DOWNTO 0); S:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); C:OUT STD_LOGIC); END RCA; ARCHITECTURE RCA_A OF RCA IS COMPONENT HA IS PORT (A,B:IN STD_LOGIC; S,C:OUT STD_LOGIC); END COMPONENT; COMPONENT FA IS PORT(A,B,CIN:IN STD_LOGIC; S,C:OUT STD_LOGIC); END COMPONENT; SIGNAL C1:STD_LOGIC; BEGIN H1:COMPONENT HA PORT MAP(A(0),B(0),S(0),C1); H2:COMPONENT FA PORT MAP(A(1),B(1),C1,S(1),C); END RCA_A;

TESTBENCH 3

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TB_RCA IS END TB_RCA; ARCHITECTURE TB_RCA1 OF TB_RCA IS COMPONENT RCA PORT(A,B:IN STD_LOGIC_VECTOR(1 DOWNTO 0); S:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); C:OUT STD_LOGIC); END COMPONENT; SIGNAL A_T,B_T,S_T: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL C_T: STD_LOGIC; BEGIN H: COMPONENT RCA PORT MAP(A_T,B_T,S_T,C_T); A_T<= "01"; B_T<= "01"; END TB_RCA1;

4) Carry look ahead adder LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CLADDER IS PORT(A,B:IN STD_LOGIC_VECTOR(1 DOWNTO 0); SUM:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); CAR:OUT STD_LOGIC); END CLADDER; ARCHITECTURE CL OF CLADDER IS BEGIN 4

PROCESS(A,B) VARIABLE C:STD_LOGIC_VECTOR(2 DOWNTO 0); VARIABLE P,G:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN P:=A XOR B; G:=A AND B; C(0):='0'; FOR I IN 0 TO 1 LOOP SUM(I)<=P(I) XOR C(I); C(I+1):=(P(I) AND C(I)) OR G(I); END LOOP; CAR<=C(2); END PROCESS; END CL; TEST BENCH LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TB_RCADR IS END TB_RCADR; ARCHITECTURE TB12 OF TB_RCADR IS COMPONENT CLADDER PORT(A,B:IN STD_LOGIC_VECTOR(1 DOWNTO 0); SUM:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); CAR:OUT STD_LOGIC); END COMPONENT; SIGNAL C1:STD_LOGIC; SIGNAL A1,B1,S1:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN H1:COMPONENT CLADDER PORT MAP(A1,B1,S1,C1); A1 <="10", "00"AFTER 30 NS,"11"AFTER 60 NS; B1 <="00", "01"AFTER 20 NS, "10"AFTER 40 NS, "01" AFTER 60 NS; END TB12;

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