RF circuit design: Basics

Akira Matsuzawa Tokyo Institute of Technology

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Contents
Building blocks in RF system and basic performances Device characteristics in RF application Low noise amplifier design Mixer design Oscillator design

Basic RF circuit block

RF systems are composed of limited circuits blocks. LNA, Mixer, and Oscillator will be discussed in my talk. Receiver 1) Low Impedance Noise Matching Amp.

2) Mixer Filter

Transmitter Power Amp.

3) Oscillator

Basic functions of RF building blocks

Amplifier, frequency converter (mixer +oscillator), and filer are basic function blocks in RF system.

2) Mixer+ Oscillator Undesired Down conversion dB 3) Filter Frequency conversion dB Desired 1) Amplifier

Log (f)

Up conversion

Log (f)

RF Amplifier
Gain: Amplify small signal or generate large signal. Noise: Smaller noise and larger SNR. Linearity: Smaller non-linearity.
Non-linearity generates undesired frequency components.
2 3 vout (t ) = 1vin (t ) + 2 vin (t ) + 3vin (t ) + .....

(cos(1t ) + cos(2t ))2 = 2 + cos(21t ) + cos(22t ) + cos((1 2 )t ) + cos((1 + 2 )t )

(cos(1t ) + cos(2t ))

1 1 = cos((21 2 )t ) + cos((22 1 )t ) + .... 2 2

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Input and output characteristics

Distortion and noise are important factors in RF amplifier, as well as power and gain. Pout OIP3 1dB Pout (1dB) Fundamental
Slope=1

IP3

IMD3 SFDR
Slope=3

Noise Floor

SNR min

SNR min

SFDR BDR NoiseMDS Floor

CP1dB

Pin IIP3
6

Dynamic range
Noise Floor = 174dBm + NF + 10 log BW
kT limitation Bandwidth

SFDR: Spurious free dynamic range The input power range over which third order inter-modulation products are below the minimum detectable signal level.

SFDR =

2 (IIP3 Noise Floor ) SNR min 3

BDR: Blocking dynamic range

BDR = P1dB Noise Floor SNR min

MDS: Minimum detectable signal level= Noise Floor +SNRmin

Non-linearity
CP1dB: The input level at which the small signal gain has dropped by 1dB.
CP1dB = 0.145

1 3

IMD3: The third order inter modulation term

IP3: The metric third order intercept point. It is the point where the amplitude of third order inter modulation is equal to the that of fundamental.

AIP 3 =

4 1 3 3

IIP3: Input referred intercept point OIP3: Output referred intercept point

Pout IMD3 = 2 (IIP3 Pin )

MOS transistor
Intrinsic gate voltage and gm are the most important factors in RF CMOS.

Drain Gate G
Body

rg vg Cgd Cgs gmvg

rds

D Cds S, B

Source MOS Transistor

Equivalent Circuit

Cutoff frequency: fT
For higher fT, increase gm and decrease Cin.
Ii Io G D Cin Ii Vi gmVi fT: Frequency at which the current gain is unity.

Ii = Iio sin(t ) Iio Vi = cos(t ) Cin

Input current Gate voltage

gmIio cos(t ) Io = gmVi = Cin

Output current

gm fT = 2Cin

Proportional to gm Inversely proportional to Cin

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Amplifier gain
For higher voltage gain, increase gm, fT, ro (Q), and decrease input and gate resistance Ig rs Vs Vg
Cin

Id
gmVg

Log (G)

g =

1 rsCin
G

T =
T r 0 rs

gm Cin

ro

G=gmr0

0 =
For the larger gain 1

gmro r0 = T rsCin rs

Fundamentally larger gmr0 G gmro Higher fT and lower rs

Ids Veff 2

Log (f)

ro

Larger Ids or ro Larger Q

Veff is difficult to reduce

Distortion and Cin increase

Q Qro = Q0L = 0C
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Characteristics of gm (Basic)
Gm is proportional to the Ids and inversely proportional to the Veff. Veff is proportional to square root of Ids and inversely proportional to square root of (W/L) ratio. Square law region

Ids =

(Vgs VT ) = Veff 2n L 2n L dI COX W gm ds = Veff dVgs n L

2

COX W

COX W

1 Ids gm , = gm = Veff Ids Veff 2 2

gm =

2 COX W Ids n L

Veff =

2n

1 L Ids Cox W
W/L ratio

Veff

Ids = L Jds W

Scaling

Veff is proportional to square root of drain current density. 12

Non-ideal effects to square low region

At larger Veff and lower Veff, two non-ideal effects are not negligible . Low Veff
Sub-threshold region
25.083 30

Gm/Ids (S/A)

Vgs Ids = Iso exp nU T Ids gm = nU T

( Weak inversion) gm 1 eff 0.4 , 10 , Veff ( ) = ( ) eff 0.2 , 5 , Veff Ids nU T

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gm 1 = = const Ids nUT

20

15

gm 2 = Ids Veff

10

High Veff

Mobility degradation
1.302

0 , 0 + 0 1 + Veff vcL

0.2 0.2

0.2

0.4

0.6

0.8 1

Veff (V)

Veff

This effect becomes larger at large Veff and short channel length.
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Distortion
Lower Veff gives higher gm, bur results in higher distortion. To obtain lower distortion ( higher IIP3), we must increase Veff. Higher gm and lower distortion means higher Ids.

Ids = a1Veff + a 2Veff + a 3Veff

2

1 d 3 Ids + a3 6 dVeff 3
100

4 a1 IIP 3 = 3 a3
10

gm/Ids (S/A)

L=0.1um L=0.2um L=0.4um IIP3

10

1 -0.1

0.1 0 0.1 0.2 0.3 0.4 0.5

Veff (V)

Veff (V) 14

IIP3 (V)

LC resonator
LC resonator can be regarded as resistance at the resonance frequency.

C L r0

Substrate

0 =

1 LC

Q ro = Q 0 L = 0C
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Substrate effect
Substrate should be treated as resistive network. This substrate resistance causes RF power loss and noise generation.
Shielding can reduce this effect. Gate PAD
Shield layer Gate PAD

S D S D S

RF power loss and noise generation

S D S D S

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Power loss in substrate

Very low resistance or high resistance realizes low power loss.
C Rp

Gp Equivalent
p 1 + 1
2

Cp

Higher C and moderate Rsub results in higher power loss.

1 R p

= C

Gp(mS)

1 + 1 R pC

Cp(pF) 1

MOS: 10cm GaAs: 1Gcm

10

100 Rp(

0.1 1K 10K

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GHz operation by CMOS

The cutoff frequency of MOS becomes higher than that of Bipolar. Over several GHz operations have attained in CMOS technology
0.13um
100G 50G

fT : CMOS fT : Bipolar (w/o SiGe) fT /10 (CMOS ) RF circuits

0.18um 0.25um 0.35um

gm fT 2Cin
vsat fTpeak 2Leff

Frequency (Hz)

20G 10G 5G 2G 1G 500M 200M

Cellular Phone

CDMA

5GHz W-LAN

fT /60 (CMOS ) Digital circuits

IEEE 1394 D R/C for HDD

100M

1995

2000

2005

Year
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Effect of parasitic capacitance to fT

fT of actual circuit is reduced by a parasitic capacitance. There is an optimum gate width to obtain highest fT.
gm fT 2 (Cgs + Cgd + Cp )
Cp Vi Cin
fti 0.2 , W , 5 .10 gmVi fti 0.2 , W , 5 .10 fti 0.2 , W , 5 .10 3 3 3 10 60 6 .10 10 5.786 .10

Cp=0
10 4 .10 40

Ids=5mA L=0.2um

fT (GHz)

,0

Cp=0.1pF

, 0.1 .10 , 0.5 .10

12 12 10 2 .10 20

(1) (2)
Cp=0.5pF

Cin=Cgs+Cgd Region(1); Increased by increasing1.576 .109 gm Region(2); Decreased by increasing Cin

00 0
10 200 400 W 600 800 1000 1 .10 3

W(um)

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fT: MOS vs. Bipolar

Even if fT of MOS is the same as that of Bipolar, fT of MOS is easily lowered by a parasitic capacitance. Because, gm of MOS is to of that of Bipolar at the same current.
Small parasitic capacitance is a key for RF CMOS design. MOS

Ids gm Veff 2
Veff min = 2nU T
n: 1.4

gm fT 2Cin

Bipolar

Ic gm UT
UT kT 26mV q

Veff/2: 50-100mV (actual ckt.)

gmCMOS < CinCMOS <

1 1 , gmBip Same operating current 2 4 1 1 , CinBip 2 4

Same fT
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VT mismatch
VT mismatch degrades accuracy; ADC, OP amp, and Mixer. Larger gate area is needed for small VT mismatch. Scaling and proper channel structure improves mismatch.
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VT (:mV)

Tox VT LW
Larger gate area

0.4um Nch Tox Scaling 0.13um Nch Boron w. Halo* 0.4um Pch Channel engineering 0.13um Nch In w/o Halo*

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0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

1 ( m 1 ) LW

* Morifuji, et al., IEDM 2000.

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VT mismatch: Fluctuation of doping

Courtesy of Prof. Taniguchi, Osaka Univ.

VT =

Qdepl Cox

= Atox

LWd depl N A LW 1 NA

= Atox

NA LW

AVT

tox LW

Q d depl
- - - - - - - --

AVT = 1V

ddepl L = W = 0.25 m, tox = 5nm VT = 20mV

T.Mizuno, J.Okamura and A.Toriumi, Experimental study o f threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs, IEEE Trans. On Electron Devices, ED-41, 2216 (1994)
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1/f noise
1/f noise of MOS is larger than that of bipolar. For the lower 1/f noise, the larger gate area is needed.
2 Vnf =

Svf f , LW f

2 Svf Tox

Nch/Pch 0.4um
Input referred noise voltage (V2/Hz) Input referred noise voltage (V2/Hz)
1E-13 1E-14 1E-15 nMOS 1E-16 1E-17 1E-18 1E-19 1E+02 pMOS W/L=800/0.4 Vdd=3V Id=1mA 1E-13 1E-14 1E-15 1E-16 1E-17 1E-18 1E-19 1E+02

Nch 0.4um/1.0um
nMOS Vdd=3V Id=1mA

L=0.4um

L=1.0um

Bipolar 1E+03 1E+04 1E+05 1E+06 1E+07

Bipolar 1E+03 1E+04 1E+05 1E+06 1E+07

Frequency (Hz)

Frequency (Hz) 23

Noise figure: General

The lower Rnv and Gni realizes the better for a lower noise figure. Zs Vn,rs Vng
Noiseless Circuit

Vs

Ing

Zs = Rs + jXs

Vng 2 = 4kTRnv , Ing 2 = 4kTGni

F= Vn2,rs + (Vng + ZsIng ) Vn2,rs
Vng Rnv = Gni Ing
2

= 1+

Rnv + Rs

Zs Gni Rs

1+

Rnv + RsGni Rs

Rsopt =

F min 1 + 2 RnvGni
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Noise figure: MOS transistor

Rnv F 1+ + RsGni Rs
Rnv = Rg + Rgs
W 1 Rg = Rsr tot L 3N 2
2

1 Rgs 5 gm
Rsopt

Gni

gm 0 5 T

1 gm 0 + Rs F 1+ Rs5 gm 5 T

1 T 1 = gm 0 Cgs 0

F min 1+ 2

0 T
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Low noise amplifier design

Narrowband LNA uses inductor degeneration for impedance matching. Impedance matching

1 gm Zin s(Ls + Lg ) + + L s T L s sCgs Cgs

0 =
1 Cgs (Ls + Lg )
Z0 Lg Cpi Cgs rgs Ls rg M1 M2

Rsub

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Low NF design
rgs + rg rgs + rg 0 F 1+ + 4gmZ 0 1 + Z0 Z0 T
2

rgs

1 5 gm
Wtot 1 L 3N 2

Low noise figure

1) Lower the gate resistance Dived the gate or lower the gate sheet resistance 2) Reduce substrate loss Reduce parasitic capacitance Use shield technique to the input bonding PAD. Use high resistive substrate, if possible. 3) Increase drain current 4) Increase Z0, if possible.
D S

rg = Rsr

rg = Rsr

Wtot L

Rsr: Sheet resistance NThe # of division Divide the gate

S D S D S

(Veff ) 1 rgs 5 gm 10 Ids

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Ids and Veff optimization

Adjust the Ids and Veff for optimization of gain, noise and distortion.
Dynamic range of LNA is proportional to Ids.

IIP3LNA DRLNA gmZ 0Veff IdsZ 0 IIP3 Veff F 1

Higher Ids NF dB Gain 3rd distortion
Veff Ids W
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Lower Ids

Veff

NF progress in MOS LNA

NF of MOS LNA is reaching 1dB.
8.0 7.0 6.0 5.0

NF (dB)

4.0 3.0 2.0 1.0 0.0 1 0.5 0.35 0.25 0.1

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Gate length (m)

Mixer
Mixer converts frequency, but image signal is converted to the same frequency.

Vs = As cos(st )

Vs

Vo

Vo = As

cos((s LO )t )

If VLO>>4Veff (Full swing)

VLO = ALO cos(LOt )

RF spectrum FLO dB Fimage Fdes dB IF spectrum

VLO

Freq FIF FIF FIF

Freq
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Image-reject mixers
The quadrature mixing realizes image-suppression. Gain and phase matching is needed.
LPF Vin (t)

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Vout(t)

cos(LOt )

sin (LOt )
LPF

45

Vin (t ) = Ades cos(dest ) + Aim cos(imt ) Vout (t ) = AdesAc cos(IFt ) + AimAcIR cos(IFt )
Ac: Conversion gain, IR: Image rejection IR=0 if I/Q phase difference is 90 and Channel conversion gains are equal.
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Gain mismatch and phase error

Pspur 1 + 2 2 cos = Pdesired 1 + 2 + 2 cos

: Gain ratio :Phase error

A. Rofougaran, et al., IEEE J.S.C. Vol.33, No.4, April 1998. PP. 515-534.

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Passive FET mixer

MOS can realize a passive mixer easily. Ultimately low power, but take care of isolation. Passive FET mixer
Vin

Lo Vo Lo

Lo Vo Lo

Low power High linearity No 1/F noise No conversion gain No isolation, Bi-directional

Vin
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Active mixers
Single balanced mixer Double balanced mixer
Very small direct feed through and even order distortion

Vo Lo

ZL

ZL Vo M2 M3 Lo Lo M1 Zs Vo

ZL

ZL Vo

M2 M3 Lo Vin M1 Zs Vin

M2 M3

Vin

Lo

M1 Zs

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Active mixer design

The larger Ids is needed for high dynamic range and shorter switching time for low 1/f noise. Mixer gain

Gmix =
2 on

gm1ZL , or =

2 ZL Zs

when Zs is used
R : Resistive component in ZL

L Thermal noise v = 8kTRL1 + 2IRL + gm1RL 8kTR 2gm1 L ALO 2 v on Veff 2 SSBvin = 2 2 kT 2 kT 2 Ids gm1 2 gm1RL A larger dynamic range needs larger current IIP3 Veff 1/F noise

1) Switch transistor (M2, M3)

vn , o =

4Ts vn , sw TLO
1 Cgs

Ts

TLO

1 2 vn , sw WL

Phase modulation

Shorter switching time or larger Ts/TLo ratio 2) Load transistors Directly produces
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Oscillator
There is an optimum Ids for low phase noise.
Vdd Vo
L L

Vo -1/gm

-1/gm

r0
ro = Q 0 L = Q 0C

Vc M2 Vb

1) Amplitude condition M3
Oscillation amplitude

Vosc =

4 Iro

I M1 (a)

Vdd VddoC = Iopt = 2 ro Q

2 , ro I>

Headroom limit

2Vdd

2) Oscillation condition

gm 2,3 >

oCVeff , 2,3
Q
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Phase noise of oscillator

Phase-frequency relation and resonator characteristics determine phase noise.
1 2QL = Bw 0
R
Z ( j )

v(t ) = A cos[ 0t + (t )]

m =
Bw

d = j dt

m
S (m)

: Offset angular frequency :Noise spectrum density on offset angular frequency :Noise spectrum density on phase Phase error between in and out :Noise spectrum density on phase error

0.7R

2 S (m) = m S (m )

d = 2QL

=
d

m
Bw

2QL

0
2

S (m )
S (m )
m < Bw

0 S (m) = 2QL S (m )
2

0 1 0 2 S (m ) = S (m) = 2QL 2QLm S (m ) m

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Phase noise of oscillator

Z ( 0 + m ) j
L Q C

-1/gm

-1/gm

r0

Q=

r0 0L

0L m 2 0

m << 0
(Filter action)

1 2Q = Bw 0
R
Z ( j )

r 0 0 Z ( 0 + m ) 2Qm
2 2 0 vn in 2 = Z = 4kTro 2Qm f f 2

0.7R

Bw

Noise spectrum density

2kT L{m} = 10 log Psig

Phase noise

0 2Qm

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Frequency characteristics of Phase noise in oscillator

1/f noise and thermal noise is converted to 1/f3 and1/f2, respectively.

S (m )
Phase noise spectrum

0 1 a 3 2QL m

S (m ) =

1 0 S (m) = 2QL m S (m )

-9dB/oct
(Slope =-3)

0 2 FkT 1 2QL Ps 2 m

S (m ) =

2 FkT Ps

-6dB/oct
(Slope=-2)

2 FkT Ps
Thermal

1/f noise

Thermal

co

Bw =

2QL

m
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Up and down converted noise

Noises around N*fo are up and down converted to fo.

Vnoise (V / Hz )
2o 3o

o
Noise shaping

P (dBm)

Up-conv.

Down-conv.

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FoM and minimum phase noise

FoM is basically proportional to Q2.
f 0 1 FoM = fm L( fm)VddI
1 1 L ( fm ) = 2 2 Q
2

Fm: Offset frequency L(fm): Phase noise at offset freq.

fo FkT 1 1 fm PRF = 2 Q 2

fo FkT fm V 2 o 2ro

F: Noise factor

8roI 8 F = 2+ + ro gm1 Vo 9

Iopt =

Vdd
2 ro

VddoC
Q
at Iopt

Vdd = 2QoLind

4 Q2 1 FoM = Q2 kT 2 + 4 + 32 Vdd 9 Veff ,1

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Oscillator design
Careful optimization reduces the oscillator phase noise.
2 fo + L min( fm) = kT Vdd 2Q Vdd Veff ,1 fm

oLind 1

Phase noise

Oscillation amplitude

1 2 L min( fm) = kT 2 Iopt 2Q

2 fo 1 + Vdd Veff ,1 fm
Iopt =

2Vdd

Vdd
2 ro

Vo Vc

VddoC
Q

Vo

Vdd 2QoLind
Iopt Bias current

M2 Vb

M3

I M1

Larger Vdd Large Veff1, but take care of Vo reduction Large L1, W1 to reduce 1/f noise Enough W/L for M2, M3 Higher Q Larger QLind for Lower Iopt
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CMOS oscillator circuits

E. Hegazi, ISSCC 2001 Basic Low power (gm is higher) Low noise by filtering

Vo Vo Vo
L L

Vo

Vo
L L

Vo

Vc Vc
C C

Vc

Hi-Z at 2fo Cs Vb Vb Vb (a) (b) (c)

43

Lx

Cx

Filtering of 2fo component in OSC.

Noise filtering of 2fo component reduces the OSC phase noise to -10dB.
E. Hegazi, ISSCC 2001

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Oscillator phase noise progress

Phase noise in CMOS oscillator becomes lower than that of bipolar.
CMOS Si-bipolar/BiCMOS SiGe-BiCMOS [dBc/Hz](@GHz,10mW,600kHz)

-90.0 -100.0 -110.0 -120.0 -130.0 -140.0 -150.0

SSB Phase Noise

1994 1995 1996 1997 1998 1999 2000 2001 2002 Year
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Acknowledgment and references

Acknowledgment
I would like to thank Prof. Asad Abidi in UCLA for his advices.

References
Asad A. Abidi, Power-Conscious design of Wireless circuits and systems, pp.665-695, Trade-offs in Analog Circuit Design, Kluwer Academic Publishers, 2002. (Edited by Chris Toumanzou, George Moschytz, and Barrie Gilbert) Thomas. H. Lee, The design of CMOS RF ICs, Cambridge University Press, Jan. 1998. Bezad, Razavi, RF micro-electronics, Prentice Hall, Nov. 1999. Domine Leenaerts, Johan van der Tang, and Ciero Vaucher, Circuit Design for RF Transceivers, Kluwer Academic Publishers, 2001. Charles Chien, Digital Radio Systems on A chip, Kluwer Academic Publishers, 2001. E. Hegazi, et. Al., A Filtering Technique to Lower Oscillator Phase Noise, ISSCC 2001, 23.4, Feb. 2001.

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