Lenovo g530 n500 - Compal La-4212p Jiwa3 Jiwa4 - Rev 1

A
ZZZ1
ZZZ2
PCB
PCB
DAZ@
ZZZ3
Power Switch
DAZ@
ZZZ4
ZZZ5
Left LED
Right LED
Touch Sensor
DAZ@
DAZ@
DAZ@
ZZZ6
JIWA3/A4
Compal confidential
Schematics Document
Mobile Penryn uFCPGA

Intel Cantiga_GM/PM+ICH9-M
Wednesday, May 14, 2008

REV:1.0
4
Compal Secret Data
Security Classification
2007/10/15
Issued Date
[email protected]
gratuito - free of charge.
A
2008/10/15
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
Title
Compal Electronics, Inc.

Cover Sheet
Size Document Number

Custom
Rev
1.0
JIWA3/A4_LA4212P
Date:
Sheet
E
of
53
Compal confidential
ZZZ1
Swithch & CAP SENSE LEDs Board
Right LED Board
File Name :
Left LED Board
15W_PCB_LA4212P
VRAM 16*16
VRAM 32*16
Mobile Penryn
uFCPGA-478 CPU
page20,21
PCI-E X16
nVIDIA NB9M
page22
H_A#(3..35)
FSB
H_D#(0..63)
Level Shifter
PS8101T page23
page23
DDR2 -667 (1.8V)

DDR2 -800 (1.8V)
Intel Cantiga GMCH

PCBGA 1329
DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
page 14,15
Dual Channel
LVDS I/F
page25
LVDS
Connector
667/800/1066MHz
PCI-E
CRT & TV OUT
Clock Gen.
SLG8SP556VTR
ICS9LPRS387AKLFT
page5,6,7
page16,19
HDMI
CONN
page 8,9,10,11,12,13
2
DMI
page24
C-Line
AMP&Audio Jack
page24
AZALIA
PCI Express
Mini card Slotpage32
1
6*PCI-E BUS
12*USB2.0
Intel ICH9-M
Audio Codec
AMOM_CX20561
mBGA-676
page26,27,28,29
BCM5906
10/100/LAN
Card Reader
page33
JMB 385
4*SATA serial
New Card
page36
MODEM_CX20548
page30
Camera Conn
LPC BUS
page40
page40
BlueTooth Conn
page32
EC
ENE KB926
RJ45 CONN
page34
C version
Card reader(XD/SD
MMC/MS/MS-Pro
HD SD)
page36
SUB Board
page32,36
USB conn X4
Int.KBD
Touch Pad
page43
page35
BIOS
page37
SATA HDD
Connector
page38
page37
SATA CDROM
Connector page39
*Right LED
*Left LED
*SWITCH & CAP sensor
Compal Secret Data
2007/10/15
Issued Date
[email protected]
A
page39
2008/10/15
Deciphered Date
B
Title

MB Block Diagram

Custom
Date:
Rev
1.0
JIWA3/A4_LA-4212P
Monday, May 12, 2008
Sheet
E
of
53
Voltage Rails
Power Plane
SMBUS Control Table

Description
S1
S3
S5
VIN
Adapter power supply (19V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
+0.9VS
0.9V switched power rail for DDR terminator
ON
OFF
OFF
+1.05VS
1.05V switched power rail
ON
OFF
+1.5VS
ON
+1.8V
1.8V power rail for DDR
+1.8VS
+2.5VS
SOURCE
THERMAL
SENSOR
(CPU)
SODIMM
CLK CHIP
MINI CARD
LCD
CAP BRD
X
V
X
X
X
X
X
X
X
X
X
V
ICH9
Cantiga
SMB_EC_CK2
SMB_EC_DA2
KB926
OFF
OFF
SMB_CK_CLK1
SMB_CK_DAT1
ON
ON
OFF
ON
OFF
OFF
ON
OFF
OFF
LCD_CLK
LCD_DAT
+3VALW
3.3V always on power rail
ON
ON
ON*
+3VS
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
SERIAL
EEPROM
V
X
OFF
+VALW
+V
+VS
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
Full ON
BATT
V
X
KB926
SIGNAL
INVERTER
X
X
SMB_EC_CK1
SMB_EC_DA1
STATE
Clock
ON
PM@
GM@
X76@
CARD@
WLAN@
HDMI@
HDMI_PM@
HDMI_GM@
BT@
Compal Secret Data
2007/10/15
Issued Date
[email protected]
A
2008/10/15
Deciphered Date
B
Title

MB Notes List
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
E
of
53
SIGNAL
STATE
Voltage Rails
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
+VALW
+V
+VS
Clock
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
Power Plane
Description
S1
S3
S5
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
VIN
Adapter power supply (19V)
N/A
N/A
N/A
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+VGA_CORE
Core voltage for GPU
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
+1.1VS
ON
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
+1.8V
1.8V power rail for DDR
ON
ON
OFF
+1.8VS
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3VS
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
Full ON
POWER SQUENCE
The ramp time for any rail must be more than 40us
EDP at Tj = 97C*
Power Supply Rail
NB9M-GS
(V)
NVVDD
2
Variable
GDDR3
12.68A
NB9M-GE
DDR2
11.57A
GDDR3
DDR2
10.52A
9.59A
FB_DLLAVDD
1.1
25mA
FB_PLLAVDD
1.1
10mA
IFPC_IOVDD
1.1
385mA
IFPD_IOVDD
1.1
385mA
IFPE_IOVDD
1.1
385mA
IFPF_IOVDD
1.1
385mA
PEX_IOVDD/Q
1.1
1400mA
PEX_PLLVDD
1.1
110mA
PLLVDD
1.1
65mA
SP_PLLVDD
1.1
25mA
VID_PLLVDD
1.1
50mA
TOTAL
1.1
3.225A
(+3VS)
PEX_VDD can ramp up any time
(1.1VS) PEX_VDD
tNVVDD>=0
(+VGA_CORE)
tFBVDDQ>=0
(1.8VS)
1.8
IFPA_IOVDD
1.8
50mA
IFPB_IOVDD
1.8
50mA
IFPAB_PLLVDD
1.8
100mA
IFPCD_PLLVDD
1.8
160mA
IFPEF_PLLVDD
1.8
160mA
TOTAL
1.8
3.6A
1720mA
2.24A
3010mA
3.53A
DACA_VDD
3.3
130mA
DACB_VDD
3.3
255mA
DACC_VDD
3.3
130mA
MIOA_VDDQ
3.3
10mA
MIOB_VDDQ
3.3
10mA
VDD33
3.3
110mA
3.3
0.645A
TOTAL
NVVDD
tNV-FB
FBVDD/Q
3080mA
VDD33
FBVDDQ
1680mA
2.2A
Compal Secret Data
2007/10/15
Issued Date
[email protected]
A
2008/10/15
Deciphered Date
B
Title

VGA Notes List
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
E
of
53
XDP Reserve
+3VS
XDP_DBRESET#
R43
<27> H_STPCLK#
<27> H_INTR
<27>
H_NMI
<27>
H_SMI#
A6
A5
C4
A20M#
FERR#
IGNNE#
H_STPCLK# D5
H_INTR
C6
H_NMI
B4
H_SMI#
A3
STPCLK#
LINT0
LINT1
SMI#
M4
N5
T2
V3
B2
D2
D22
D3
F6
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD pins on the CPU

should be left as NO
CONNECT
IERR#
INIT#
D20
B3
H_IERR#
H_INIT#
LOCK#
H4
H_LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
C1
F3
F4
G3
G2
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
HIT#
HITM#
G6
E4
H_HIT#
H_HITM#
CONTROL
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H_BR0#
54.9_0402_1%
54.9_0402_1%
XDP_TDO
R12
1 @
54.9_0402_1%
R13
54.9_0402_1%
reserved by XDP_BPM#5
R83
56_0402_5%
XDP_TRST#
R16
54.9_0402_1%
XDP_TCK
R15
54.9_0402_1%
<8>
H_INIT#
<27>
H_LOCK# <8>
H_RESET# <8>
H_RS#0 <8>
H_RS#1 <8>
H_RS#2 <8>
H_TRDY# <8>
+3VS
+3VS
H_HIT# <8>
H_HITM# <8>
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
H_PROCHOT#
D21
A24
B25
H_THERMDA
H_THERMDC
C7
H_THERMTRIP#
A22
A21
CLK_CPU_BCLK
CLK_CPU_BCLK#
H CLK
BCLK[0]
BCLK[1]
H_DEFER# <8>
H_DRDY# <8>
H_DBSY# <8>
C95
1
XDP_DBRESET# <28>
1
68_0402_5%
+3VS
+VCCP
R95
10K_0402_5%
1
C89
U5
EC_SMB_CK2
SDATA
EC_SMB_DA2
D- ALERT/THERM2
VDD
H_THERMDA
D+
H_THERMDC
2
2200P_0402_50V7K
THERM#
3
4
THERM
XDP_BPM#5 reserve a via for debuging
2
R84
THERMAL
ICH
H_A20M#
H_FERR#
H_IGNNE#
<27> H_A20M#
<27> H_FERR#
<27> H_IGNNE#
H_BR0#
<8>
<8>
<8>
R14
R94
1
2
10K_0402_5%
SCLK
GND
EC_SMB_CK2 <16,35,41>
EC_SMB_DA2 <16,35,41>
S IC EMC1402-1-ACZL-TR MSOP 8P
Address:100_1100
H_PROCHOT#
H_THERMTRIP# <8,27>
FAN1 Conn
CLK_CPU_BCLK <22>
CLK_CPU_BCLK# <22>
+5VS
+5VS
C594
1
H_THERMDA, H_THERMDC routing together,

Trace width / Spacing = 10 / 10 mil
<35>
EN_FAN1
+VCC_FAN1
EN_FAN1
1
R726
Penryn
10U_0805_10V4Z
2
U24
1 VEN
GND
2 VIN
GND
3 VO
GND
1K_0402_5%
4 VSET
GND
1
G990P11U_SO8
C808
0.1U_0402_16V4Z
2
<8> H_ADSTB#1
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
XDP/ITP SIGNALS
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
H_DEFER#
H_DRDY#
H_DBSY#
F1
BR0#
ADDR GROUP_1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H5
F21
E1
H_ADS#
H_BNR#
H_BPRI#
R11
XDP_TMS
D17
@ 1SS355TE-17_SOD323-2
8
7
6
5
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
H_ADS#
H_BNR#
H_BPRI#
XDP_TDI
K3
H2
K2
J3
L1
DEFER#
DRDY#
DBSY#
H1
E2
G5
+VCCP
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
ADS#
BNR#
BPRI#
0.1U_0402_16V4Z
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP_0
<8> H_ADSTB#0
<8>
H_REQ#0
<8>
H_REQ#1
<8>
H_REQ#2
<8>
H_REQ#3
<8>
H_REQ#4
<8> H_A#[17..35]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
RESERVED
<8> H_A#[3..16]
+VCCP
ME@
JCPUA
2 @ 1K_0402_5%
@
1
D16
BAS16_SOT23-3
2
C595
1U_0603_10V4Z
1
2
+3VS
C597
0.1U_0402_16V4Z
1
2
R469
10K_0402_5%
40mil
JP13
+VCC_FAN1
1
2
3
<35> FAN_SPEED1
C596
1000P_0402_50V7K
4
5
1
2
3
GND
GND
A
E&T_3801-F03N-01R
ME@
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
Deciphered Date
2008/10/15
4
Title

Penryn (1/3)
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
of
53
+CPU_CORE
+CPU_CORE
ME@
JCPUC
Trace Close CPU < 0.5'
2 @ 1K_0402_5%
2 @ 1K_0402_5%
T16
T15
T14
T17
T10
1
1
<22> CPU_BSEL0
<22> CPU_BSEL1
<22> CPU_BSEL2
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
+CPU_GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
COMP[0]
COMP[1]
COMP[2]
COMP[3]
R26
U26
AA1
Y1
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
MISC
COMP0
COMP1
COMP2
COMP3
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
<8>
H_DSTBN#2 <8>
H_DSTBP#2 <8>
H_DINV#2 <8>
H_D#[48..63] <8>
H_DSTBN#3 <8>
H_DSTBP#3 <8>
H_DINV#3 <8>
R63 1
R64 1
R10 1
R9 1
2
2
2
2
27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
H_DPRSTP# <8,27,51>
H_DPSLP# <27>
H_DPWR# <8>
H_PWRGOOD <27>
H_CPUSLP# <8>
H_PSI#
<51>
Penryn
Width=4 mil ,
Spacing: 15mil
(55Ohm)
TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)

COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA[01]
VCCA[02]
B26
C26
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VCCSENSE
AF7
VCCSENSE
VSSSENSE
AE7
VSSSENSE
For testing purpose only

+VCCP
R47
2
2
R8
0_0402_5%
1
1
0_0402_5%
Near pin B26

20mils
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
<51>
<51>
<51>
<51>
<51>
<51>
<51>
0.01U_0402_16V7K
R45
R46
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
C599
<8> H_DSTBN#1
<8> H_DSTBP#1
<8>
H_DINV#1
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
DATA GRP 1
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DATA GRP 0
<8> H_DSTBN#0
<8> H_DSTBP#0
<8>
H_DINV#0
<8> H_D#[16..31]
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
DATA GRP 2
H_D#[32..47]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
10U_0805_10V4Z
C598
ME@
JCPUB
H_D#[0..15]
DATA GRP 3
<8>
+1.5VS
VCCSENSE <51>
VSSSENSE <51>
Penryn
.
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
BCLK
533
133
BSEL2
BSEL1
BSEL0
667
166
800
200
1067
266
Length match within 25 mils.

The trace width/space/other is
16/7/25.
FSB
+VCCP
R471
1K_0402_1%
+CPU_GTLREF
Layout note: Z0=55 ohm

0.5" max for GTLREF.
Compal Secret Data

2007/10/15
Issued Date
[email protected]
5
Deciphered Date
2008/10/15
4
Title
VCCSENSE
R24
100_0402_1%
1
2
VSSSENSE
Close to CPU pin

within 500mils.
Close to CPU pin AD26

within 500mils.
R23
100_0402_1%
2
Layout Note:
Route VCCSENSE and VSSSENSE traces at
27.4 Ohms with 50 mil spacing.
Place PU and PD within 1 inch of CPU.
Length matched to within 25 mils.
R470
2K_0402_1%
+CPU_CORE

Penryn (2/3)
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
of
53
ME@
JCPUD
+CPU_CORE
1
Place these capacitors on L8
(North side,Secondary Layer)
1
C13
10U_0805_6.3V6M
1
C39
10U_0805_6.3V6M
1
C36
10U_0805_6.3V6M
1
C30
10U_0805_6.3V6M
1
C27
10U_0805_6.3V6M
1
C19
10U_0805_6.3V6M
1
C14
10U_0805_6.3V6M
C12
10U_0805_6.3V6M
+CPU_CORE
1
(North side,Secondary Layer)
1
C28
10U_0805_6.3V6M
1
C24
10U_0805_6.3V6M
1
C40
10U_0805_6.3V6M
1
C37
10U_0805_6.3V6M
1
C31
10U_0805_6.3V6M
1
C26
10U_0805_6.3V6M
1
C20
10U_0805_6.3V6M
C15
10U_0805_6.3V6M
+CPU_CORE
1
(Sorth side,Secondary Layer)
1
C583
10U_0805_6.3V6M
1
C585
10U_0805_6.3V6M
1
C586
10U_0805_6.3V6M
1
C589
10U_0805_6.3V6M
1
C591
10U_0805_6.3V6M
1
C593
10U_0805_6.3V6M
1
C582
10U_0805_6.3V6M
C584
10U_0805_6.3V6M
+CPU_CORE
1
(Sorth side,Secondary Layer)
1
C588
10U_0805_6.3V6M
1
C587
10U_0805_6.3V6M
1
C590
10U_0805_6.3V6M
1
C592
10U_0805_6.3V6M
1
C35
10U_0805_6.3V6M
1
C29
10U_0805_6.3V6M
1
C25
10U_0805_6.3V6M
C33
10U_0805_6.3V6M
Mid Frequence Decoupling
South Side Secondary
1
+
1
+
1
+
2 @
C16
330U_V_2.5VK_R9
+CPU_CORE
C41
330U_V_2.5VK_R9
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
C17
330U_V_2.5VK_R9
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
C47
330U_V_2.5VK_R9
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
1
+
North Side Secondary
ESR <= 1.5m ohm

Capacitor > 1980uF
+VCCP
Penryn
.
C8
220U_D2_4VM
1
C11
0.1U_0402_16V4Z
1
C10
0.1U_0402_16V4Z
1
C51
0.1U_0402_16V4Z
1
C50
0.1U_0402_16V4Z
1
C48
0.1U_0402_16V4Z
C9
0.1U_0402_16V4Z
Place these inside

socket cavity on L8
(North side
Secondary)
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
Deciphered Date
2008/10/15
4
Title

Penryn (3/3)
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
of
53
<5>
<5>
<5>
<5>
<5>
H_RS#0
H_RS#1
H_RS#2
<5>
<5>
<5>
CLK
R206
10K_0402_5%
R217
10K_0402_5%
PM_EXTTS#0
PM_EXTTS#1
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_POK_R
PLT_RST#_R
H_THERMTRIP#
DPRSLPVR
<28> PM_BMBUSY#
<6,27,51> H_DPRSTP#
<14> PM_EXTTS#0
<15> PM_EXTTS#1
PLT_RST#
+1.8V
Near B3 pin
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
BA17
AY16
AV16
AR13
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
SA_ODT_0
SA_ODT_1
SB_ODT_O
SB_ODT_1
BD17
AY17
BF15
AY13
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SM_RCOMP
SM_RCOMP#
BG22
BH21
SMRCOMP
SMRCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
BF28
BH28
SMRCOMP_VOH
SMRCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
AV42
AR36
BF17
BC36
+DDR_MCH_REF
SM_PWROK
SM_REXT
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
B38
A38
E41
F41
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#
PEG_CLK
PEG_CLK#
F43
E43
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
AE41
AE37
AE47
AH39
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
AE40
AE38
AE48
AH40
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
AE35
AE43
AE46
AH42
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
AD35
AE44
AF46
AH43
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
B33
B32
G33
F33
E33
GFX_VR_EN
C34
T90
T89
T65
T64
T63
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
<14>
<14>
<15>
<15>
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
<14>
<14>
<15>
<15>
M_ODT0
M_ODT1
M_ODT2
M_ODT3
PAD
PAD
PAD
PAD
PAD
R497
<14>
<14>
<15>
<15>
+1.8V
BC28
AY28
AY36
BB36
R498
80.6_0402_1%
<14>
<14>
<15>
<15>20mil
For Crestline: 20ohm

For Calero: 80.6ohm
For Cantiga: 80.6ohm
2 80.6_0402_1%
R148 1
1
2 10K_0402_5%
2
R111 499_0402_1%
DDR3
CLK_MCH_DREFCLK <22>
CLK_MCH_DREFCLK# <22>
MCH_SSCDREFCLK <22>
MCH_SSCDREFCLK# <22>
CLK_MCH_3GPLL <22>
CLK_MCH_3GPLL# <22>
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
<28>
<28>
<28>
<28>
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
<28>
<28>
<28>
<28>
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
<28>
<28>
<28>
<28>
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
<28>
<28>
<28>
<28>
MCH_HDA_BCLK
connect to power CPU_CORE

1
C646
10P_0402_50V8J
@
T91
+VCCP
AH37
AH36
AN36
AJ35
AH34
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
CL_CLK0
CL_DATA0
CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
CL_RST#
CL_VREF
R143
<28>
<28>
<28>
<28>
1K_0402_1%
0.1U_0402_16V4Z 1
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
N28
M28
G36
E36
K36
H36
TSATN#
B12
HDMICLK_NB
HDMIDAT_NB
MCH_CLKREQ#
MCH_ICH_SYNC#
T52
T51
B28
B30
B29
C29
A28
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
R80
R82
R79
R85
R81
check list 511ohm 1%

ISPD only 510ohm 5%
TSATN# <35>
+VCCP
2
56_0402_5%
MCH_HDA_BCLK
MCH_HDA_RST#
MCH_HDA_SDIN
MCH_HDA_SDOUT
MCH_HDA_SYNC
R147
499_0402_1%
C238
HDMICLK_NB <23>
2
HDMIDAT_NB <23>
MCH_CLKREQ# <22>
MCH_ICH_SYNC# <28>
R105
CANTIGA ES_FCBGA1329
R162
1
10K_0402_5%
2
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
For AMT function
+DDR_MCH_REF
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
1
1
1
1
1
GM@
GM@
GM@
GM@
GM@
2
2
2
2
2
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
HDA_BITCLK_CODEC <16,27,30>
HDA_RST_CODEC# <16,27,30>
HDA_SDIN0 <27>
HDA_SDOUT_CODEC <16,27,30>
HDA_SYNC_CODEC <16,27,30>
Notice: Please check HDA power rail to select HDA controller.
GM@
+DDR_MCH_REF
R160
10K_0402_5%
C273
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C616
1
R482
221_0603_1%
2
1
R484
2
H_SWNG
100_0402_1%
R89
24.9_0402_1%
2
1
C623
1
R493
1K_0402_1%
2
1
R488
2
2K_0402_1%
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
R29
B7
N33
P32
AT40
AT11
T20
R32
NC
<16,26,32,33,36,40>
PM_POK_R
1
0_0402_5%
0309 add
1
@ 0_0402_5%
PLT_RST#_R
2
100_0402_5%
2
R177
2
R178
1
R103
VGATE
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
AR24
AR21
AU24
AV20
<14>
<14>
<15>
<15>
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
+3VS
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
<6>
<6>
<6>
<6>
T48
T47
T45
T41
T50
T49
T39
T43
T38
T37
T46
T42
T55
T53
T54
+VCCP
within 100 mils from NB
RSVD22
RSVD23
RSVD24
RSVD25
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
<28,51>
BG23
BF23
BH18
BF18
AP24
AT21
AV24
AU20
<6>
<6>
<6>
<6>
+VCCP
T87
T88
T34
T35
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
CFG5
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
<28,35> ICH_POK
RSVD20
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
Route H_SCOMP and H_SCOMP# with trace width

spacing and impedance (55 ohm) same as FSB data traces
AY21
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
1
1K_0402_1%
<5,27> H_THERMTRIP#
<28,51> DPRSLPVR
H_RCOMP
T40
R500
<22> MCH_CLKSEL0
<22> MCH_CLKSEL1
<22> MCH_CLKSEL2
<6>
<6>
<6>
<6>
layout note:
0.1U_0402_16V4Z
H_VREF
RSVD15
RSVD16
RSVD17
DMI
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
B31
B2
M1
H_ADS#
<5>
H_ADSTB#0 <5>
H_ADSTB#1 <5>
H_BNR#
<5>
H_BPRI# <5>
H_BR0#
<5>
H_DEFER# <5>
H_DBSY# <5>
CLK_MCH_BCLK <22>
CLK_MCH_BCLK# <22>
H_DPWR# <6>
H_DRDY# <5>
H_HIT#
<5>
H_HITM# <5>
H_LOCK# <5>
H_TRDY# <5>
GM@
T56
T84
T83
DDR CLK/ CONTROL/
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
GRAPHICS VID
H_AVREF
H_DVREF
H_RS#0
H_RS#1
H_RS#2
H_RS#_0
H_RS#_1
H_RS#_2
B6
F12
C8
H_CPURST#
H_CPUSLP#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
B15
K13
F13
B13
B14
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24
L9
M8
AA6
AE5
C640
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
0.01U_0402_25V7K
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
SMRCOMP_VOL
C636
L10
M7
AA5
AE6
1K_0402_1%
R501
3.01K_0402_1%
NA lead free
0.01U_0402_25V7K
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
2.2U_0603_6.3V4Z
C641
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
SMRCOMP_VOH
2.2U_0603_6.3V4Z
C635
J8
L3
Y13
Y1
R502
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
T69
T70
T58
T66
T23
T25
T27
T30
T26
T62
T61
T67
T68
T44
PM
A11
B11
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
+1.8V
ME
H_VREF
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
<5>
MISC
H_RESET#
H_CPUSLP#
C12
E11
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
HDA
H_RESET#
H_CPUSLP#
H_SWING
H_RCOMP
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
C5
E3
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
CFG
H_SWNG
H_RCOMP
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
RSVD
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
<5>
<6>
H_A#[3..35]
U26A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_D#[0..63]
HOST
<6>
COMPENSATION
U26B
Compal Secret Data
Issued Date
[email protected]
5
2007/10/15
Deciphered Date
2008/10/15
4
Title

Cantiga GMCH(1/6)-GTL
Size
C
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet

1
of
53
<15> DDR_B_D[0..63]
BD21
BG18
AT25
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
SA_RAS#
SA_CAS#
SA_WE#
BB20
BD20
AY20
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_BS#0 <14>
DDR_A_BS#1 <14>
DDR_A_BS#2 <14>
DDR_A_RAS# <14>
DDR_A_CAS# <14>
DDR_A_WE# <14>
SYSTEM
MEMORY
DDR_A_DM[0..7]
<14>
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
DDR_A_MA[0..14]
<14>
<14>
<14>
U26E
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_BS_0
SB_BS_1
SB_BS_2
BC16
BB17
BB33
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
SB_RAS#
SB_CAS#
SB_WE#
AU17
BG16
BF14
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
SA_BS_0
SA_BS_1
SA_BS_2
MEMORY
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
DDR
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12
SYSTEM
U26D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR
<14> DDR_A_D[0..63]
DDR_B_BS#0 <15>
DDR_B_BS#1 <15>
DDR_B_BS#2 <15>
DDR_B_RAS# <15>
DDR_B_CAS# <15>
DDR_B_WE# <15>
DDR_B_DM[0..7]
<15>
DDR_B_DQS[0..7]
<15>
DDR_B_DQS#[0..7]
DDR_B_MA[0..14]
<15>
<15>
GM@
GM@
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
Deciphered Date
2008/10/15
4
Title

Cantiga GMCH (2/6)-DDRII
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
of
53
Strap Pin Table

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved
CFG[2:0] FSB Freq select
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_N[0..15] <16>
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_P[0..15] <16>
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_N[0..15] <16>
PCIE_GTX_C_MRX_P[0..15]
CFG[4:3]
Reserved
CFG5 (DMI select)
0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable
CFG6
Place the resistor within 500mils

(1.27mm)of the (G)MCH
PEGCOMP trace width
and spacing is 20/25 mils.
U26C
<24> LVDS_ACLK#
<24> LVDS_ACLK
<24> LVDS_A0#
<24> LVDS_A1#
<24> LVDS_A2#
C41
C40
B37
A37
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDS_A0#
LVDS_A1#
LVDS_A2#
T93
H47
E46
G40
A40
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
T94
H48
D45
F40
B40
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
T72
A41
H38
G37
J37
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
T73
B42
G38
F37
K37
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
LVDS_A0
LVDS_A1
LVDS_A2
<24> LVDS_A0
<24> LVDS_A1
<24> LVDS_A2
Layout Note: Place 150

Ohmtermination resistors
close to GMCH
LVDS_ACLK#
LVDS_ACLK
LVDS
Note: All LVDS data

signals/and it's compliments
should be routed
Differentially
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
1
2.37K_0402_1%
PEG_COMPI
PEG_COMPO
GRAPHICS
2
R167
C44
B43
E37
E38
R213 1
R159 1
LVDS_SCL
LVDS_SDA
GM_ENVDD
<24> LVDS_SCL
<24> LVDS_SDA
<24> GM_ENVDD
For Cantiga:2.37kohm
For Crestline:2.4kohm
For Calero: 1.5Kohm
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
GM@
2
75_0402_5%
TVA_DAC
R121
GM@ 1
75_0402_5%
TVB_DAC
R122
75_0402_5%
TVC_DAC
GM@
TVA_DAC
TVB_DAC
TVC_DAC
GMCH_CRT_R
<25> GMCH_CRT_B
150_0402_1%
GMCH_CRT_G
<25> GMCH_CRT_G
150_0402_1%
GMCH_CRT_B
2
<25> GMCH_CRT_R
150_0402_1%
TVA_DAC
TVB_DAC
TVC_DAC
H24
TV_RTN
C31
E32
TV_DCONSEL_0
TV_DCONSEL_1
GMCH_CRT_B
E28
CRT_BLUE
GMCH_CRT_G
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
GMCH_CRT_CLK H32
GMCH_CRT_DATA J32
J29
E29
<25> GMCH_CRT_CLK
<25> GMCH_CRT_DATA
1
2
R203
30_0402_1%
<25> GMCH_CRT_HSYNC
GMCH_CRT_R
20mil
GM@
1
R204
<25> GMCH_CRT_VSYNC
L29
2
30_0402_1%
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
T37
T36
PEGCOMP
CFG7 (Intel Management

Engine Crypto strap)
+VCC_PEG
49.9_0402_1%
R1631
2
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15
C277
C303
C317
C315
C325
C343
C358
C349
C368
C354
C371
C356
C372
C364
C375
C348
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15
C271
C296
C314
C311
C322
C336
C352
C344
C363
C346
C366
C351
C367
C359
C373
C347
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15
Please check Power

source if want
support IAMT
1 =(TLS)chiper suite with confidentiality
CFG8
Reserved
CFG9
0 = Reverse Lane,15->0, 14->1
(PCIE Graphics Lane Reversal)
1 = Normal Operation,Lane Number in order
CFG10 (PCIE Lookback enable)
0 = Enable
1 = Disable
CFG11
Reserved
CFG[13:12] (XOR/ALLZ)
00
01
10
11
CFG[15:14]
Reserved
CFG16 (FSB Dynamic ODT)
0 = Disabled
= Reserved
= XOR Mode Enabled
= All Z Mode Enabled
= Normal Operation(Default)
1 = Enabled
CFG[18:17]
Reserved
CFG19 (DMI Lane Reversal)
0 = Normal Operation
(Lane number in Order)
1 = Reverse Lane
CFG20 (PCIE/SDVO concurrent)
0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.
R140
0_0402_5%
PM@
R138
2
R139
0_0402_5%
PM@
GM@
1.02K_0402_1%
For Cantiga:1.02kohm
For Crestline:1.3kohm
For Calero: 255ohm
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
C670
C674
C669
C673
C662
C663
C658
C661
PCIE_GTX_C_MRX_P3
1
1
1
1
1
1
1
1
C306 1
2
2
2
2
2
2
2
2
HDMI_GM@
HDMI_GM@
HDMI_GM@
HDMI_GM@
HDMI_GM@
HDMI_GM@
HDMI_GM@
HDMI_GM@
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
2 HDMI_GM@ 0_0402_5%
R
2007/10/15
Issued Date
[email protected]
TMDS_B_CLK <23>
TMDS_B_CLK# <23>
TMDS_B_DATA0 <23>
TMDS_B_DATA0# <23>
TMDS_B_DATA1 <23>
TMDS_B_DATA1# <23>
TMDS_B_DATA2 <23>
TMDS_B_DATA2# <23>
TMDS_B_HPD# <23>
Deciphered Date
2008/10/15
4
Compal Secret Data
1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality
GM@
VGA
1 GM@
R132
1 GM@
R124
1 GM@
R123
F25
H25
K25
TV
R127
PCI-EXPRESS
<24> GMCH_ENBKL
+3VS
L32
G32
M32
M33
K33
J33
M29
T1
GMCH_ENBKL
2 10K_0402_5%
2 10K_0402_5%
PCIE_GTX_C_MRX_P[0..15] <16>
Title

Cantiga GMCH (3/6)-VGA/LVDS/TV

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet

1
10
of
53
+3VS_DAC_CRT
U26H
PM@
M25
VCCD_TVDAC
+1.5VS_QDAC
L28
VCCD_QDAC
+1.05VS_HPLL
AF1
VCCD_HPLL
+1.05VS_PEGPLL
AA47
C265
C606
CRT
VTT
A PEG A LVDS
C136
C608
AXF
PEG
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
V48
U48
V47
U47
U46
0.1U_0402_16V4Z
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
GM@
VCCD_TVDAC: 58.696mA
(0.1UF*1, 0.01UF*1)
0_0402_5%
R208
C299
GM@
2.2U_0603_6.3V4Z
PM@
2
1
0_0603_5%
GM@
+1.8V
+1.8V_TXLVDS: 118.8mA
(22UF*1, 1000PF*1)
GM@
C299
0_0402_5%
PM@
L17
BLM18PG121SN1D_0603
2
1
+VCC_DMI
VCC_DMI: 456mA
(0.1UF*1)
+VCCP
+1.5VS_PEG_PLL: 50mA
(0.1UF*1)
+1.05VS_PEGPLL
AH48
AF48
AH47
AG47
40 mils
1000P_0402_50V7K
+VCCP
C603
+VCC_PEG
+VCC_PEG
R186
+VCCP
1
C355
+
2
2.2U_0603_6.3V4Z
0316 add
2
1
0_0805_5%
change to 0805 size 1/04
20mils
+VCCP
VTTLF1
VTTLF2
VTTLF3
+VCC_DMI
A8
L1
AB2
R202
2
1
0_0805_5%
+VCCP_D
+VCCP
1
2
1
10_0402_5%
CH751H-40PT_SOD323-2
R157
2
1
0_0402_5%
+3VS_HV
+3VS
0316 add
C787
10U_0805_10V4Z
C353
GM@
10U_0805_10V4Z
U26
@
R158
C337
0.47U_0402_6.3V6K
@
D1
1U_0603_10V4Z
C618 0.47U_0402_6.3V6K
VCCD_LVDS_1
VCCD_LVDS_2
C35
B35
A35
C611 0.47U_0402_6.3V6K
+1.8V_LVDS
VCCD_PEG_PLL
VCC_HV_1
VCC_HV_2
VCC_HV_3
C94
M38
L37
LVDS
0_0402_5%
+1.5VS_TVDAC
D TV/CRT
GM@
+1.8V_TXLVDS
+3VS_HV
DMI
VCC_HDA
HDA
A32
+1.5VS
1.05VS_MPLL: 139.2mA
(22UF*1, 0.1UF*1)
C323
VCC_HDA: 50mA
(0.1UF*1)
R473
2
1
MBK2012121YZF_0805
C339
GM@
C171
0.1U_0402_16V4Z
+1.8V_TXLVDS
220U_D2_4VM
K47
+1.05VS_MPLL
C342
VCC_TX_LVDS
+1.8V_SM_CK
TV
VCCA_TV_DAC_1
VCCA_TV_DAC_2
BF21
BH20
BG20
BF20
0.1U_0402_16V4Z
C181
GM@
10U_0805_10V4Z
B24
A24
+3VS_TVDAC
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
HV
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
0_0603_5%
C181
0.022U_0402_16V7K
GM@
C370
+3VS_TVDAC
2.2U_0603_6.3V4Z
2
1
0_0603_5%
GM@
C180
C649
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
+3VS_TVDAC: 40mA
(0.1UF*1, 0.01UF*1 for
each DAC)
10U_0805_10V4Z
C604
+1.5VS
R136
+VCCP
+V1.05VS_AXF
0.1U_0402_16V4Z
C210
0.1U_0402_16V4Z
1U_0603_10V4Z
C214
10U_0805_10V4Z
B22
B21
A21
VTTLF
1U_0603_10V4Z
C102
A SM
0.1U_0402_16V4Z
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
R496
1
2
0_0805_5%
+1.5VS_TVDAC
+1.05VS_HPLL: 24mA
(4.7UF*1, 0.1UF*1)
1
C609
SM CK
C211
C194
GM@
R117
1
1U_0402_6.3V4Z
R474
POWER
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
R134
2
1
0_0603_5%
+3VS
4.7U_0805_10V4Z
C96
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
+1.05VS_A_SM_CK
VCCA_SM_CK: 220mA
(22UF*1, 2.2UF*1, 0.1UF*1)
+1.05VS_HPLL
10U_0805_10V4Z
10U_0805_10V4Z
GM@
C198
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C180
150U_D_6.3VM
C87
GM@
2
1
MBK2012121YZF_0805
R108
1
2
0_0805_5%
2
GM@
10U_FLC-453232-100K_0.25A_10%
1
C301
+1.05VS_A_SM
C605
0_0402_5%
PM@
+VCCP
C195
0.022U_0402_16V7K
VCCA_PEG_PLL
20 mils
+1.05VS_PEGPLL
1
+VCCP
AA48
+1.5VS_PEG_BG
R166
2
1
0_0603_5%
PM@
VCCA_SM:720mA
(22UF*2, 4.7UF*1, 1UF*1)
VCCA_PEG_BG
A CK
PM@
VSSA_LVDS
AD48
C628
+1.5VS
0_0402_5%
C300
GM@
+1.8V
R191
1
VCC_SM_CK: 119.85mA
(10UF*1, 0.1UF*1)
+1.8V_SM_CK
+1.05VS_DPLLB
C312
0.1U_0402_16V4Z
0_0402_5%
R495
0_0603_5%
10U_0805_10V4Z
+1.5VS_PEG_BG: 0.414mA
(0.1UF*1)
C631
C206
1U_0603_10V4Z
C637
J47
+1.05VS_DPLLA
+1.05VS_DPLLB: 64.8mA
(470UF*1, 0.1UF*1)
PM@
C627
1000P_0402_50V7K
0_0402_5%
GM@
C629
VCCA_LVDS
2
2
GM@ GM@
+VCCP
10U_0805_10V4Z
VCCA_MPLL
J48
+1.8V_TXLVDS
10U_FLC-453232-100K_0.25A_10%
C310
AE1
10U_0805_10V4Z
VCCA_HPLL
+1.05VS_MPLL
10U_0805_10V4Z
VCCA_DPLLB
AD1
C278
C312
VCCA_DPLLA
L48
+1.05VS_HPLL
0.1U_0402_16V4Z
F47
+
2
+VCCP
+V1.05VS_AXF
C275
VSSA_DAC_BG
+1.05VS_DPLLB
+1.05VS_DPLLA
GM@
B25
4.7U_0805_10V4Z
VCCA_DAC_BG
0.47U_0402_6.3V6K
GM@
C639
10U_0805_10V4Z
1
C637
0.1U_0402_16V4Z
GM@
0.022U_0402_16V7K
C638
R151
C278
+3VS_DAC_BG
1R115
0_0603_5%
GM@
A25
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
0.1U_0402_16V4Z
VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1)

+3VS_DAC_BG
+3VS
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
4.7U_0805_10V4Z
B27
A26
+3VS_DAC_CRT
C126
GM@
+1.05VS_DPLLA
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

220U_D2_4VM
GM@
2
VCC_AXF: 321.35mA
(10UF*1, 1UF*1)
+VCCP
1
10U_0805_10V4Z
C681
0.022U_0402_16V7K
C213
1
C206
GM@
0.1U_0402_16V4Z
R120
1
2
0_0603_5%
GM@
PLL
+3VS
add one more cap 1/2
PM
PM@
VCCD_QDAC: 48.363mA
(0.1UF*1, 0.01UF*1)
+1.5VS_QDAC
1.8V_LVDS: 60.311111mA
(1UF*1)
+1.8V_LVDS
R142
R137
GM@
C237
1U_0603_10V4Z
GM@
+1.5VS
C226
10U_0805_10V4Z
C221
10U_0805_10V4Z
C207
0.1U_0402_16V4Z
C208
1U_0402_6.3V4Z
2
1
0_0603_5%
1
2
1
0_0603_5%
GM@
+1.8V
2 GM@
C237
GM@
0_0603_5%
Issued Date
[email protected]
5
Compal Secret Data
PM@
2007/10/15
Deciphered Date
2008/10/15
4
Title

Crestline GMCH (4/6)-VCC

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet

1
11
of
53
U26F
+AXG_CORE
Check : power
JUMP_43X118
+VCCP
NCTF
VCC
B
+AXG_CORE
10U_0805_10V4Z
0.1U_0402_16V4Z
1
1
C149
1U_0603_10V4Z
C84
C104
C104
GM@
C157
220U_D2_4VM_R15
GM@
C167
10U_0805_10V4Z
GM@
GM@
GM@
C157
PM@
PM@
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
AJ14
AH14
VCC_AXG_SENSE
VSS_AXG_SENSE
GM@
PM@
C297 1U_0402_6.3V4Z
Title
C243 1U_0402_6.3V4Z
2008/10/15
C264 0.47U_0402_6.3V6K
Compal Secret Data
C159 0.22U_0402_10V4Z
GM@
GM@
C101 0.22U_0402_10V4Z
[email protected]
0_0603_5%
AV44 VCCSM_LF1
BA37 VCCSM_LF2
AM40 VCCSM_LF3
AV21 VCCSM_LF4
AY5 VCCSM_LF5
AM10 VCCSM_LF6
BB13 VCCSM_LF7
1
GM@
Deciphered Date
C99
C99
2007/10/15
C114 0.1U_0402_16V4Z
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
Issued Date
0.22U_0402_10V4Z
C121 0.1U_0402_16V4Z
T32
T31
GM@
4.7U_0603_6.3V6K
1 C197
GFX
0_0805_5% 0_0805_5%
BA36
BB24
BD16
BB21
AW16
AW13
AT13
0.1U_0402_16V4Z
VCC
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
GFX NCTF
POWER
J4
1
VCC
+AXG_CORE
VCC SM LF
+VCCP
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
C129
SM
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
T32
C645
VCC CORE
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
C220
0.1U_0402_16V4Z
C175
0.22U_0402_10V4Z
C193
0.22U_0402_10V4Z
C178
10U_0805_10V4Z
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
0.01U_0402_16V7K
U26G
D
10U_0805_10V4Z
C643
220U_D2_4VM_R15
C177
+VCCP
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
POWER
+1.8V
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29

Crestline GMCH (5/6)-VCC

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
12
of
53
VSS
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
BA16
VSS_235
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS
VSS NCTF
U26J
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS SCB
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
NC
U26I
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36
GM@
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
VSS_351
VSS_352
VSS_353
VSS_354
U24
U28
U25
U29
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
BH48
BH1
A48
C1
A3
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
A
GM@
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
Deciphered Date
2008/10/15
4
Title

Cantiga GMCH (6/6)-GND

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
13
of
53
Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.
+1.8V
+DDR_MCH_REF1
DDR_A_DQS#0
DDR_A_DQS0
R225
100_0402_1%
DDR_A_D8
DDR_A_D14
R232
DDR_A_DQS#1
DDR_A_DQS1
100_0402_1%
2
C404
0.1U_0402_16V4Z
Layout Note:
Place near JP41
DDR_A_D2
DDR_A_D3
+DDR_MCH_REF1
<15> +DDR_MCH_REF1
DDR_A_D9
DDR_A_D15
+1.8V
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_A_D16
DDR_A_D17
C650
C653
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C219
0.1U_0402_16V4Z
C218
C151
0.1U_0402_16V4Z
C268
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C644
2.2U_0805_16V4Z
C152
2.2U_0805_16V4Z
C235
2.2U_0805_16V4Z
DDR_A_DQS#2
DDR_A_DQS2
1
+
C215
470U_D2_2.5VM_R15
@
DDR_A_D18
DDR_A_D19
DDR_A_D29
DDR_A_D24
DDR_A_DM3
<15,35,37> EC_TX_P80_DATA
DDR_A_D26
DDR_A_D27
C
<8> DDR_CKE0_DIMMA
<15,35,37> EC_RX_P80_CLK
<9> DDR_A_BS#2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<9> DDR_A_BS#0
<9> DDR_A_WE#
+0.9VS
<9> DDR_A_CAS#
<8> DDR_CS1_DIMMA#
M_ODT1
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D37
DDR_A_D36
DDR_A_DQS#4
DDR_A_DQS4
2
C164
C242
C163
C217
C223
C162
C230
C161
C236
C228
C209
C179
C170
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
<8>
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_D38
DDR_A_D32
DDR_A_D40
DDR_A_D44
DDR_A_DM5
DDR_A_D41
DDR_A_D46
+0.9VS
RP1
DDR_A_WE#
DDR_A_CAS#
M_ODT1
DDR_CS1_DIMMA#
1
2
3
4
RP2
8
7
6
5
56_0804_8P4R_5%
DDR_A_BS#0
R128 1
DDR_A_MA10
R133 1
DDR_A_MA14
2
56_0402_5%
2
56_0402_5%
R146 1
2
56_0402_5%
8
7
6
5
1
2
3
4
DDR_A_RAS#
M_ODT0
DDR_A_MA13
DDR_CS0_DIMMA#
Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"
DDR_A_D49
DDR_A_D48
<15> EC_RX_P80_CLK_R
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D50
56_0804_8P4R_5%
DDR_A_D61
DDR_A_D60
RP5
5
6
7
8
4
3
2
1
DDR_A_BS#1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA4
DDR_A_DM7
DDR_A_D59
DDR_A_D58
56_0804_8P4R_5%
RP6
DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_MA8
4
3
2
1
RP9
5
6
7
8
56_0804_8P4R_5%
5
6
7
8
4
3
2
1
EC_RX_P80_CLK_R
<15,22> CLK_SMBDATA
<15,22> CLK_SMBCLK
DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_CKE1_DIMMA
CLK_SMBDATA
CLK_SMBCLK
+3VS
C83
0.1U_0402_16V4Z
RP10
DDR_A_MA9
DDR_A_MA12
DDR_A_BS#2
DDR_CKE0_DIMMA
4
3
2
1
5
6
7
8
DDR_A_DM0
DDR_A_D5
DDR_A_D7
SO-DIMM A
DDR_A_D13
DDR_A_D12
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 <8>
M_CLK_DDR#0 <8>
DDR_A_D11
DDR_A_D10
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
FOX_ASOA426-M2RN-7F
ME@
+DDR_MCH_REF1 <15>
DDR_A_D20
DDR_A_D21
PM_EXTTS#0 <8>
DDR_A_DM2
DDR_A_D23
DDR_A_D22
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D30
DDR_CKE1_DIMMA
DDR_A_MA14
DDR_CKE1_DIMMA <8>
DDR_A_MA14 <9>
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_BS#1 <9>
DDR_A_RAS# <9>
DDR_CS0_DIMMA# <8>
M_ODT0
<8>
DDR_A_D33
DDR_A_D39
DDR_A_DM4
DDR_A_D35
DDR_A_D34
DDR_A_D45
DDR_A_D43
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D42
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>
DDR_A_DM6
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
Top side
2007/10/15
Issued Date
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
DDR_A_D6
DDR_A_D0
Compal Secret Data
56_0804_8P4R_5%
[email protected]
56_0804_8P4R_5%
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
C402
<9> DDR_A_MA[0..13]
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
C388
DDR_A_D4
DDR_A_D1
<9> DDR_A_DQS[0..7]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
0.1U_0402_16V4Z
+1.8V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2.2U_0805_16V4Z
JP17
<9> DDR_A_D[0..63]
<9> DDR_A_DM[0..7]
+1.8V
R77
10K_0402_5%
2
1
<9> DDR_A_DQS#[0..7]
R73
10K_0402_5%
2
1
2008/10/15
Deciphered Date
4
Title

DDRII-SODIMM SLOT1

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
14
of
53
+1.8V
<9> DDR_B_DQS#[0..7]
+1.8V
<9> DDR_B_D[0..63]
+DDR_MCH_REF1
<9> DDR_B_DM[0..7]
DDR_B_D10
DDR_B_D11
+1.8V
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_B_D17
DDR_B_D20
1
1
C191
C199
0.1U_0402_16V4Z
C188
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C192
0.1U_0402_16V4Z
C241
C156
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C387
2.2U_0805_16V4Z
C150
C232
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C155
470U_D2_2.5VM_R15
@
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D25
DDR_B_D28
T80
DDR_B_DM3
<14,35,37> EC_TX_P80_DATA
DDR_B_D30
DDR_B_D31
C
<8> DDR_CKE2_DIMMB
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
<14,35,37> EC_RX_P80_CLK
<9> DDR_B_BS#2
DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
+0.9VS
<9> DDR_B_CAS#
<8> DDR_CS3_DIMMB#
1
<8>
M_ODT3
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D32
DDR_B_D33
2
C176
C185
C204
C222
C229
C246
C247
C187
C196
C216
C227
C240
C244
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
<9> DDR_B_BS#0
<9> DDR_B_WE#
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
+0.9VS
RP3
DDR_B_CAS#
DDR_B_WE#
DDR_CS3_DIMMB#
M_ODT3
8
7
6
5
RP4
1
2
3
4
56_0804_8P4R_5%
DDR_B_BS#0
DDR_B_MA10
DDR_B_MA14
R135 1
2
56_0402_5%
R131 1
2
56_0402_5%
R152 1
2
4
3
2
1
5
6
7
8
DDR_B_MA13
M_ODT2
DDR_CS2_DIMMB#
DDR_B_RAS#
Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"
5
6
7
8
DDR_B_D56
DDR_B_D61
DDR_B_BS#1
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4
DDR_B_DM7
DDR_B_D58
DDR_B_D59
<14,22> CLK_SMBDATA
<14,22> CLK_SMBCLK
5
6
7
8
+3VS
DDR_B_MA7
DDR_B_MA6
DDR_B_MA11
DDR_CKE3_DIMMB
C82
0.1U_0402_16V4Z
56_0804_8P4R_5%
DDR_B_DM1
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2 <8>
M_CLK_DDR#2 <8>
DDR_B_D14
DDR_B_D15
DDR_B_D21
DDR_B_D16
PM_EXTTS#1 <8>
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D26
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB <8>
DDR_B_MA14
DDR_B_MA14 <9>
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_BS#1 <9>
DDR_B_RAS# <9>
DDR_CS2_DIMMB# <8>
M_ODT2
DDR_B_MA13
M_ODT2
<8>
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D39
DDR_B_D38
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
FOX_AS0A426-NARN-7F~N
ME@
SO-DIMM B
R74
1
R78
56_0804_8P4R_5%
4
3
2
1
CLK_SMBDATA
CLK_SMBCLK
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
10K_0402_5%
DDR_B_DQS#6
DDR_B_DQS6
RP7
RP11
4
3
2
1
EC_RX_P80_CLK_R
<14> EC_RX_P80_CLK_R
56_0804_8P4R_5%
4
3
2
1
RP8
5
6
7
8
T22
DDR_B_D51
DDR_B_D50
56_0804_8P4R_5%
DDR_B_MA1
DDR_B_MA3
DDR_B_MA5
DDR_B_MA9
DDR_B_D48
DDR_B_D49
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DDR_B_D12
DDR_B_D13
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D6
DDR_B_D7
+3VS
10K_0402_5%
A
DDR_B_D8
DDR_B_D9
DDR_B_DM0
C407
DDR_B_D2
DDR_B_D3
Layout Note:
Place near JP42
DDR_B_D4
DDR_B_D5
C403
DDR_B_DQS#0
DDR_B_DQS0
D
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
0.1U_0402_16V4Z
DDR_B_D0
DDR_B_D1
<9> DDR_B_MA[0..13]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
2.2U_0805_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
<9> DDR_B_DQS[0..7]
+DDR_MCH_REF1 <14>
JP16
RP12
DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA8
8
7
6
5
1
2
3
4
2007/10/15
Issued Date
56_0804_8P4R_5%
[email protected]
Compal Secret Data
2008/10/15
Deciphered Date
4
Title

DDRII-SODIMM SLOT2
Size
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Date:
Sheet

1
15
of
53
U27A
CLK_PCIE_VGA
CLK_PCIE_VGA#
<22> CLK_PCIE_VGA
<22> CLK_PCIE_VGA#
1
2
R183 200_0402_5% @
2
1
R504 2.4K_0402_1% PM@
PLT_RST#
<8,26,32,33,36,40> PLT_RST#
1
XTALOUT
XTALIN
R100
10K_0402_5%
PM@
VGA_HSYNC
VGA_VSYNC
VGA_HSYNC <25>
VGA_VSYNC <25>
DACA_RED
DACA_BLUE
DACA_GREEN
AE2
AD3
AE3
VGA_CRT_R
VGA_CRT_B
VGA_CRT_G
VGA_CRT_R <25>
VGA_CRT_B <25>
VGA_CRT_G <25>
DACA_VREF
DACA_RSET
AF1
AE1
DACA_VREF
DACA_RSET
G6
F8
DACC_HSYNC
DACC_VSYNC
U6
U4
DACC_RED
DACC_BLUE
DACC_GREEN
T5
R4
T4
DACC_VREF
DACC_RSET
R6
V6
PM@
AF10
AE10
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
AG10
PEX_TERMP
AD9
PEX_RST_N
D11
E9
XTAL_SSIN
XTAL_OUTBUFF
E10
D10
XTAL_OUT
XTAL_IN
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
TESTMODE
SPDIF
VDD_SENSE
PM@
HDA_RST_N
HDA_SDI
HDA_SDO
HDA_SYNC
HDA_BCLK
PM@ 2
PM@ 2
PM@ 2
1
1
1
150_0402_1%
150_0402_1%
150_0402_1%
124_0402_1%
+3VS
R75
2.2K_0402_5%
HDMI_PM@
R69
2.2K_0402_5%
HDMI_PM@
R65
10K_0402_5%
@
R1
T3
R2
R3
A2
B1
N2
N3
Y6
W6
A3
A4
T1
T2
AF3
AG4
AE4
AF4
AG3
AD25
+3VS
R71
10K_0402_5%
@
PM@
PM@
U4
8
7
6
5
HDCP_SMB_CK1
HDCP_SMB_DAI
VGA_DDCCLK_C
VGA_DDCDATA_C
R116 1
2.2K_0402_5%
2
R119 1
2.2K_0402_5%
2
VGA_LVDS_SCL_C
VGA_LVDS_SDA_C
R196 1
2.2K_0402_5%
2
R193 1
2.2K_0402_5%
2
VGA_HDMI_SCL
VGA_HDMI_SDA
HDCP_SMB_CK1
HDCP_SMB_DAI
EC_SMB_CK2
EC_SMB_DA2
HDMI_PM@
C79
2 0.1U_0402_16V4Z
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
AT24C16AN-10SU-2.7_SO8
HDMI_PM@
R66
10K_0402_5%
@
R70
100K_0402_1% HDMI_PM@
2
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CD_SCL
I2CD_SDA
I2CE_SCL
I2CE_SDA
I2CH_SCL
I2CH_SDA
I2CS_SCL
I2CS_SDA
R164
R168
R180
DACB_VREF
DACB_RSET
R503
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
F7
E6
E7
CRT OUT
1 PM@
0.1U_0402_16V4Z
D6
2
C648
DACA
AD2
AD1
DACB_RED
DACB_BLUE
DACB_GREEN
PEX_REFCLK
PEX_REFCLK_N
DACA_HSYNC
DACA_VSYNC
DACB_CSYNC
VGA_LVDS_SCL <24>
VGA_LVDS_SDA <24>
T29
AB10
AC10
GPIO
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
2 10K_0402_5%
@ R173
OSC_SPREAD
R99
10K_0402_5%
PM@
AD10
AD11
AD12
AC12
AB11
AB12
AD13
AD14
AD15
AC15
AB14
AB15
AC16
AD16
AD17
AD18
AC18
AB18
AB19
AB20
AD19
AD20
AD21
AC21
AB21
AB22
AC22
AD22
AD23
AD24
AE25
AE26
PM@
VGA_DDCCLK <25>
VGA_DDCDATA <25>
PM@ PM@PM@PM@
PAD
PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N15
PM@
PM@
MBK1608121YZF_0603
2
2
MBK1608121YZF_0603
MBK1608121YZF_0603
2
2
MBK1608121YZF_0603
1
1
1
1
C770C771C772C773
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
2
2
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
PM@
VGA_LVDS_SCL_C L41
1
VGA_LVDS_SDA_C
1
L42
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
NV_INVTPWM
VGA_ENVDD
VGA_ENBKL
L39
1
1
L40
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VGA_DDCCLK_C
VGA_DDCDATA_C
HDMI_DETECT_VGA <23>
PAD T86
VGA_ENVDD <24>
VGA_ENBKL <24>
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
N1
G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2
PM@
PM@
VGA_HDMI_SCL <23>
VGA_HDMI_SDA <23>
JTAG_TRST_N
TESTMODE
EC_SMB_CK2 <5,35,41>
EC_SMB_DA2 <5,35,41>
JTAG_TCK
PAD
T60
JTAG_TDO
PAD
T59
JTAG_TRST_N
TESTMODE
PAD
PAD
T92
T57
F9
W15
SPDIF_IN
+VGASENSE
PAD
C6
A6
B6
B7
A7
HDA_RST_CODEC#_R
HDA_SDIN1_R
HDA_SDOUT_CODEC_R
HDA_SYNC_CODEC_R
HDA_BITCLK_CODEC_R
R650
R86
R651
R652
R653
PM@
1 R645
2
10K_0402_5%
1 R646
2
10K_0402_5%
PM@
+3VS
B
VGA_HDMI_SDA
VGA_HDMI_SCL
VGA_DDCCLK
VGA_DDCDATA
T28
R492
R490
R489
R491
1
1
1
1
@
@
@
@
2
2
2
2
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
+VGASENSE
1
1
1
1
1
PM@
2
PM@
2
PM@
2
PM@
2
PM@
2
22_0402_5%
10_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%
HDA_RST_CODEC# <8,27,30>
HDA_SDIN1 <27>
HDA_SDOUT_CODEC <8,27,30>
HDA_SYNC_CODEC <8,27,30>
HDA_BITCLK_CODEC <8,27,30>
C261
C260
C294
C293
C259
C258
C292
C291
C257
C256
C290
C289
C255
C254
C287
C288
C253
C252
C285
C286
C251
C250
C284
C283
C249
C248
C282
C281
C267
C266
C280
C279
CLK
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
DACB
PCIE_GTX_C_MRX_P[0..15]
<10> PCIE_GTX_C_MRX_P[0..15]
D
DACC
PCIE_GTX_C_MRX_N[0..15]
<10> PCIE_GTX_C_MRX_N[0..15]
PCI EXPRESS
PCIE_MTX_C_GRX_P[0..15]
<10> PCIE_MTX_C_GRX_P[0..15]
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
HDA
<10> PCIE_MTX_C_GRX_N[0..15]
Part 1 of 5
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
I2C
PCIE_MTX_C_GRX_N[0..15]
AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
AF22
AE22
AE24
AF24
AG24
AF25
AG25
AG26
AF27
AE27
TEST
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
NB9M-GS_BGA533
If External Spread Spectrum not stuff than stuff resistor
R647
10K_0402_5%
@
2
External Spread Spectrum
Y3
C612
U3
OUT
GND
REFOUT
GND
IN
XOUT
27MHZ_16PF_X7S027000BG1H-U
PM@
1
C614
VSS
MODOUT
XIN/CLKIN
VDD
ASM3P2872AF-06OR_TSOT-23-6
18P_0402_50V8J
PM@ 2
18P_0402_50V8J
PM@ 2
@
1
R55
2 OSC_SPREAD
22_0402_5%
+3VS
2
@
1
C66
0.1U_0402_16V4Z
@
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
2008/10/15
Deciphered Date
4
Title

NB9M-GS PCIE,LVDS,GPIO,CLK
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
16
of
53
FBAD[0..63]
FBAA[0..12]
FBAD[0..63] <20,21>
FBAA[0..12] <20,21>
FBBA[2..5] <21>
FBADQS[0..7]
R129
10K_0402_5%
<20,21>
2
FBADQS[0..7]
FBAODT0
FBBA[2..5]
FBADQS#[0..7]
FBADQM#[0..7]
FBADQS#[0..7]
PM@
D
<20,21>
FBADQM#[0..7] <20,21>
U27C
U27B
FBA_DEBUG
A24
C25
E19
A19
T22
T27
AA24
AA26
FBADQS0
FBADQS1
FBADQS2
FBADQS3
FBADQS4
FBADQS5
FBADQS6
FBADQS7
C269~C276
NEAR CONNECT
NEAR CONNECT PULL DOWN
TMDS pull down (500ohm) resistors G9x only
R182 1
R98 1
R102 1
2 @ 1K_0402_5%
2 @ 1K_0402_5%
1K_0402_5%
2
F5
F4
E4
D5
C3
C4
B3
B4
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
PM@
IFPAB_RSET
IFPE_RSET
IFPC_RSET
STRAP0
STRAP1
STRAP2
F10
F11
<19>
<19>
<19>
BUFRST_N
N5
PAD
T36
THERMDN
D8
PAD
T24
THERMDP
D9
PAD
T85
ROM_CS_N
B10
ROM_SCLK
STARP_REF_MIOB
STARP_REF_3V3
STRAP0
STRAP1
STRAP2
C7
B9
A9
R88
40.2K_0402_1%
PM@
C9
ROM_SCLK
ROM_SI
A10
ROM_SI
ROM_SO
C10
ROM_SO
IFPE_AUX_N
IFPE_AUX
IFPC_AUX_N
IFPC_AUX
R91
40.2K_0402_1%
PM@
2
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
STRAP0
STRAP1
STRAP2
C15
D15
E15
F6
J5
J22
L22
T6
AA6
AC19
AE9
AG9
NC
P4
N4
M5
M4
L4
K4
H4
J4
AB6
M6
R5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VGA_HDMI_TX2+
VGA_HDMI_TX2VGA_HDMI_TX1+
VGA_HDMI_TX0VGA_HDMI_CLK+
VGA_HDMI_CLK-
VGA_HDMI_TX2+
VGA_HDMI_TX0VGA_HDMI_CLK+
VGA_HDMI_CLK-
STRAP
1
2
<20,21>
R186~R195
ROM_SCLK <19>
ROM_SI <19>
ROM_SO <19>
D4
D3
G5
G4
NB9M-GS_BGA533
PM@
+1.8VS
R87
1K_0402_1%
@
15mil
FB_VREF1
A16
<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
GENERAL
FBADQS#0
FBADQS#1
FBADQS#2
FBADQS#3
FBADQS#4
FBADQS#5
FBADQS#6
FBADQS#7
R499
10K_0402_5%
@
AB3
AB2
W1
V1
W3
W2
AA2
AA3
AB1
AA1
SERIAL
B24
D25
E18
A18
R22
R27
Y24
AA27
R118
10K_0402_5%
PM@
Part 3 of 5
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
LVDS/TMDS
FBADQM#0
FBADQM#1
FBADQM#2
FBADQM#3
FBADQM#4
FBADQM#5
FBADQM#6
FBADQM#7
FBA_CKE
FBAODT0 <20,21>
AC4
AD4
V5
V4
AA5
AA4
W4
Y4
AB4
AB5
D23
C26
D19
B19
T24
T26
AA23
AB27
FBABA2
<20,21>
VGA_LVDS_ACLK
VGA_LVDS_ACLK#
VGA_LVDS_A0
VGA_LVDS_A0#
VGA_LVDS_A1
VGA_LVDS_A1#
VGA_LVDS_A2
VGA_LVDS_A2#
VGA_LVDS_ACLK
VGA_LVDS_ACLK#
VGA_LVDS_A0
VGA_LVDS_A0#
VGA_LVDS_A1
VGA_LVDS_A1#
VGA_LVDS_A2
VGA_LVDS_A2#
FBABA2
<24>
<24>
<24>
<24>
<24>
<24>
<24>
<24>
FBAA3
FBAA0
FBAA2
FBAA1
FBBA3
FBBA4
FBBA5
FBACS1#
PAD T33
FBACS0#
FBACS0# <20,21>
FBAWE#
FBAWE# <20,21>
FBA_BA0
FBA_BA0 <20,21>
FBA_CKE
AODT0 R494 1
2 FBAODT0
PM@
0_0402_5%
FBBA2
FBAA12
FBARAS#
FBARAS# <20,21>
FBAA11
FBAA10
FBA_BA1
FBA_BA1 <20,21>
FBAA8
FBAA9
FBAA6
FBAA5
FBAA7
FBAA4
FBACAS#
FBACAS# <20,21>
F26
J24
F25
M23
N27
M27
K26
J25
J27
G23
G26
J23
M25
K27
G25
L24
K23
K24
G22
K25
H22
M26
H24
F27
J26
G24
G27
M24
K22
FBA_D0 Part 2 of 5
FBA_CMD0
FBA_D1
FBA_CMD1
FBA_D2
FBA_CMD2
FBA_D3
FBA_CMD3
FBA_D4
FBA_CMD4
FBA_D5
FBA_CMD5
FBA_D6
FBA_CMD6
FBA_D7
FBA_CMD7
FBA_D8
FBA_CMD8
FBA_D9
FBA_CMD9
FBA_D10
FBA_CMD10
FBA_D11
FBA_CMD11
FBA_D12
FBA_CMD12
FBA_D13
FBA_CMD13
FBA_D14
FBA_CMD14
FBA_D15
FBA_CMD15
FBA_D16
FBA_CMD16
FBA_D17
FBA_CMD17
FBA_D18
FBA_CMD18
FBA_D19
FBA_CMD19
FBA_D20
FBA_CMD20
FBA_D21
FBA_CMD21
FBA_D22
FBA_CMD22
FBA_D23
FBA_CMD23
FBA_D24
FBA_CMD24
FBA_D25
FBA_CMD25
FBA_D26
FBA_CMD26
FBA_D27
FBA_CMD27
FBA_D28
FBA_CMD28
FBA_D29
FBA_D30
FBA_DQM0
FBA_D31
FBA_DQM1
FBA_D32
FBA_DQM2
FBA_D33
FBA_DQM3
FBA_D34
FBA_DQM4
FBA_D35
FBA_DQM5
FBA_D36
FBA_DQM6
FBA_D37
FBA_DQM7
FBA_D38
FBA_D39
FBA_DQS_RN0
FBA_D40
FBA_DQS_RN1
FBA_D41
FBA_DQS_RN2
FBA_D42
FBA_DQS_RN3
FBA_D43
FBA_DQS_RN4
FBA_D44
FBA_DQS_RN5
FBA_D45
FBA_DQS_RN6
FBA_D46
FBA_DQS_RN7
FBA_D47
FBA_D48
FBA_DQS_WP0
FBA_D49
FBA_DQS_WP1
FBA_D50
FBA_DQS_WP2
FBA_D51
FBA_DQS_WP3
FBA_D52
FBA_DQS_WP4
FBA_D53
FBA_DQS_WP5
FBA_D54
FBA_DQS_WP6
FBA_D55
FBA_DQS_WP7
FBA_D56
FBA_D57
FB_VREF
FBA_D58
FBA_D59
FBA_CLK0
FBA_D60
FBA_CLK0_N
FBA_D61
FBA_D62
FBA_CLK1
FBA_D63
FBA_CLK1_N
F24
F23
FBACLK0 <20>
FBACLK0# <20>
N24
N23
FBACLK1 <21>
FBACLK1# <21>
FBA_DEBUG 1
R113
M22
C90
@
0.1U_0402_16V4Z
R90
1K_0402_1%
@
2
2
D21
C22
B22
A22
C24
B25
A25
A26
D22
E22
E24
D24
D26
D27
C27
B27
D16
E16
D17
F18
D20
F20
E21
F21
C16
B18
C18
D18
C19
C21
B21
A21
P22
P24
R23
R24
T23
U24
V23
V24
N25
N26
R25
R26
T25
V26
V25
V27
V22
W22
W23
W24
AA22
AB23
AB24
AC24
W25
W26
W27
AA25
AB25
AB26
AD26
AD27
MEMORY INTERFACE
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
+1.8VS
10K_0402_5%
PM@
NB9M-GS_BGA533
PM@
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
2008/10/15
Deciphered Date
4
Title

NB9M-GS Memory
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
17
of
53
PLACE NEAR BGA

+VGA_CORE
NEAR BALL
0.1U_0402_16V4Z
C680
PM@
220U_D2_4VM
U27D
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
+
C182
PM@
C135
PM@
C141
PM@
C146
PM@
C147
PM@
0.1U_0402_16V4Z
0.47U_0402_6.3V6K
1
C153
PM@
0.1U_0402_16V4Z
0.47U_0402_6.3V6K
C144
PM@
PM@
0.1U_0402_16V4Z
C148
1
C160
PM@
1
C166
PM@
1
C165
PM@
C186
PM@
0.47U_0402_6.3V6K
0.47U_0402_6.3V6K
0.47U_0402_6.3V6K
0.47U_0402_6.3V6K
4.7U 6.3V K X5R 0603

1
C169
PM@
C133
PM@
NEAR BGA
4.7U 6.3V K X5R 0603

C
+3VS
NEAR BGA
110mA
C105
PM@
1
C120
PM@
2
0.1U_0402_16V4Z
1U_0603_10V4Z
+IFPAB_IOVDD
NEAR BALL
+1.8VS
L32
MBK1608121YZF_0603
1
2
PM@
1
NEAR BGA
110mA
NEAR BALL
0.1U_0402_16V4Z
1
C93
PM@
+IFPC_IOVDD
10K_0402_5% R109
2
1 PM@
4700P_0402_25V7K
470P_0402_50V8J
4700P_0402_25V7K
470P_0402_50V8J
1
1
1
1
12~16mil
C634
PM@
2
4.7U 6.3V K X5R 0603
C633
PM@
C776
PM@
C632
PM@
C777
PM@
C128
J9
J10
J12
J13
L9
M9
M11
M17
N9
N11
N12
N13
N14
N15
N16
N17
N19
P11
P12
P13
P14
P15
P16
P17
R9
R11
R12
R13
R14
R15
R16
R17
T9
T11
T17
U9
U19
W9
W10
W12
W13
W18
W19
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A12
B12
C12
D12
E12
F12
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
V3
V2
J6
IFPA_IOVDO
IFPB_IOVDD
IFPC_IOVDD
H6
IFPE_IOVDD
+IFPAB_PLLVDD
AD5
+IFPC_PLLVDD
P6
2
1 PM@ N6
10K_0402_5% R181
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
Part 4 of 5
POWER
11.57A
PM@
PM@
2
2
0.022U_0402_16V7K
A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22
+1.8VS
0.1U_0402_16V4Z
1
C124
PM@
PM@
2
2
0.1U_0402_16V4Z
PM@
2
4.7U 6.3V K X5R 0603
4700P_0402_25V7K
1
C140
C139
PM@
AG6
AF6
AE6
AD6
AC13
AC7
AB17
AB16
AB13
AB9
AB8
AB7
AG7
AF7
AE7
AD8
AD7
AC9
PEX_PLLVDD
VID_PLLVDD
SP_PLLVDD
PLLVDD
AF9
K6
L6
K5
+PEX_PLLVDD
FB_PLLAVDD
R19
+FB_PLLAVDD
FB_DLLAVDD
T19
+FB_DLLAVDD
DACA_VDD
DACB_VDD
DACC_VDD
AG2
D7
W5
+DACA_VDD
+DACB_VDD
+DACC_VDD
C142
C106
PM@
0.1U_0402_16V4Z
1
C212
PM@
PM@
2
0.1U_0402_16V4Z
0.47U_0402_6.3V6K
1
C203
C202
PM@
2
1U_0402_6.3V4Z
1
12~16mil
+1.1VS
PEX_IOVDDQ=1.6A
PEX_IOVDD=500mA
PEX_PLLVDD=100mA
C201
PM@
2
0.47U_0402_6.3V6K
0.1U_0402_16V4Z
1
C145
PM@
C122
PM@
2
1U_0402_6.3V6K
PLLVDD=65mA
NEAR BALL SP_PLLVDD=25mA
VID_PLLVDD=50mA
2
2 10K_0402_5%
10K_0402_5%
B15
2 R93
30_0402_1%
+1.1VS
+1.8VS
+FB_PLLAVDD
NB9M-GS_BGA533
PM@
L15
MBK1608121YZF_0603
+1.8VS
1
NEAR BGA
260mA
PM@
470P_0402_50V8J
+IFPAB_PLLVDD
4700P_0402_25V7K
1
1
+PEX_PLLVDD
NEAR BALL
C309
PM@
2
4.7U 6.3V K X5R 0603
C302
PM@
C657
PM@
2
0.01U_0402_16V7K
C660
PM@
10U_0603_6.3V6M
1
L38
1
2
MBK1608121YZF_0603
PM@
C788
C671
PM@
PM@
2
4.7U 6.3V K X5R 0603
1
C154
PM@
0.01U_0402_16V7K
NEAR BALL
L13
MBK1608121YZF_0603
1
2
PM@
NEAR BGA
2
C173
PM@
C174
PM@
L14
1
2
MBK1608121YZF_0603
PM@
1
C189
PM@
1
C190
PM@
C205
PM@
NEAR BGA
C115
PM@
2
4.7U 6.3V K X5R 0603
C779
PM@
C112
PM@
L37
MBK1608121YZF_0603
PM@
+DACA_VDD
4700P_0402_25V7K
150mA
+IFPC_IOVDD
1
C652
PM@
C117
PM@
4.7U 6.3V K X5R 0603 2

1
C651
PM@
+3VS
1
C664
PM@
A
470P_0402_50V7K
NEAR BALL
470P_0402_50V7K
Compal Secret Data
Issued Date
[email protected]
4.7U 6.3V K X5R 0603
4.7U 6.3V K X5R 0603

L9
MBK1608121YZF_0603
PM@
4700P_0402_25V7K
1
2
4.7U 6.3V K X5R 0603
0.01U_0402_16V7K
C231
PM@
C172
PM@
4700P_0402_25V7K 470P_0402_50V8J +IFPC_PLLVDD

1
+1.1VS
0.1U_0402_16V4Z
+FB_DLLAVDD
1
+1.8VS
L11
1
2
MBK1608121YZF_0603
PM@
0.1U_0402_16V4Z
1
+1.1VS
0.1U_0402_16V4Z
1
C778
PM@
C295
C270
PM@
PM@
2
2
10U_0805_10V4Z
MBK1608121YZF_0603 +1.1VS
2
1
L10
PM@
1
1U_0402_6.3V6K
1
10U_0805_10V4Z
1
C262
PM@
2
4.7U 6.3V K X5R 0603
PM@
FB_CAL_PD_VDDQ
B
+1.8VS
1U_0603_10V4Z
1
C97
C200
PM@
+1.8VS
1U_0603_10V4Z
1
C118
NEAR BALL
C132
C123
C138
PM@
PM@
PM@
2
2
2
0.1U_0402_16V4Z
1U_0402_6.3V6K
1 PM@
R1011
R130 PM@
PM@
PM@
2
2
0.1U_0402_16V4Z
PM@
2
2
4700P_0402_25V7K
PM@
PM@
2
2
0.1U_0402_16V4Z
PM@
2
0.022U_0402_16V7K
0.022U_0402_16V7K
1
C119
PM@
FBAVDDQ=1.72A
4700P_0402_25V7K
1
1
1
C127
C109
PM@
PM@
2
2
4700P_0402_25V7K
4.7U 6.3V K X5R 0603

1
C131
C107
@
PLACE BELOW GPU

4700P_0402_25V7K
1
C111
C108
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
IFPAB_PLLVDD
IFPC_PLLVDD
IFPE_PLLVDD
0.022U_0402_16V7K
1
1
C134
C125
2007/10/15
2008/10/15
Deciphered Date
4
Title

NB9M-GS Power

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet

1
18
of
53
A total of 8 signals are required for GB1 strapping this includes

2 reference signals
6 physical strapping pins
4 logical strapping bits
U27E
A total of 24 logical strapping bits are available
GND_SENSE
W16
FB_CAL_PU_GND
A15
FB_CAL_TERM_GND
B16
+3VS
R51
X76@
R50
@
2
20K_0402_1%
4.99K_0402_1%
2K_0402_5%
R53
PM@
2K_0402_5%
1
2
1
2
R58
PM@
15K_0402_1%
R54
@
10K_0402_5%
1
2
R61
@
R481
@
10K_0402_5%
R57
PM@
2
R59
@
R485
PM@
10K_0402_5%
STRAP2
STRAP1
STRAP0
ROM_SCLK
ROM_SI
ROM_SO
10K_0402_1%
2
<17> STRAP2
<17> STRAP1
<17> STRAP0
<17> ROM_SCLK
<17> ROM_SI
<17> ROM_SO
R60
@
10K_0402_1%
R62
X76@
45.3K_0402_1%~D
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Part 5 of 5
U2
U5
U11
U12
U13
U14
U15
U16
U17
U23
U26
V9
V19
W11
W14
W17
Y2
Y5
Y23
Y26
AC2
AC5
AC6
AC8
AC11
AC14
AC17
AC20
AC23
AC26
AF2
AF5
AF8
AF11
AF14
AF17
AF20
AF23
AF26
T16
T15
T14
10K_0402_5%
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B2
B5
B8
B11
B14
B17
B20
B23
B26
E2
E5
E8
E11
E14
E17
E20
E23
E26
H2
H5
J11
J14
J17
K9
K19
L2
L5
L11
L12
L13
L14
L15
L16
L17
M12
M13
M14
M15
M16
P2
P5
P9
P19
P23
P26
T12
T13
GB1 Family GPU Strap Qptions

R97
R96
1 R700
2
PM@ 0_0402_5%
PM@ 2 30_0402_1%
1
1
GPU
FB Memory
2 40.2_0402_1%
Samsung
NB9M-GS_BGA533
PM@
NB9M-GS
(0x06E9)
Hynix
Qimonda
32Mx16(5)
ROM_SO
ROM_SCLK
ROM_SI
STRAP2
STRAP1
STRAP0
PU 5K
PD 15K
PD 30K
PU 10K
PD 10K
PU 45K
64Mx16
PU 5K
PD 15K
PD 5K
PU 10K
PD 10K
PU 45K
32Mx16(7)
PU 5K
PD 15K
PD 45K
PU 10K
PD 10K
PU 45K
64Mx16
PU 5K
PD 15K
PD 10K
PU 10K
PD 10K
PU 45K
32Mx16(6)
PU 5K
PD 15K
PD 35K
PU 10K
PD 10K
PU 45K
Component
DDR2 VRAM
(32M*16)
Manufacturer
Compal PN
Hynix
SA00000FF30
Qimonda
SA00000S820
Samsung
SA00001VX10
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
2008/10/15
Deciphered Date
4
Title

NB9M-GE GND & STRAP
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
19
of
53
U6
FBA_BA0
FBA_BA1
L2
L3
FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBAA5
FBAA4
FBAA3
FBAA2
FBAA1
FBAA0
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
FBACLK0#
FBACLK0
K8
J8
CK
CK
FBA_CKE
K2
CKE
FBACS0#
L8
CS
FBAWE#
K3
WE
FBARAS#
K7
RAS
FBACAS#
L7
CAS
FBADQM#1
FBADQM#0
F3
B3
LDM
UDM
FBAODT0
+1.8VS
F7
E8
R480
1K_0402_1%
PM@
+VRAM_VREFA
FBADQS0
FBADQS#0
(SSTL-1.8) VREF = .5*VDDQ
1
2
R479
1K_0402_1%
PM@
C613
0.047U_0402_16V4Z
PM@
Close to U6
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
FBAD7
FBAD3
FBAD4
FBAD0
FBAD1
FBAD6
FBAD2
FBAD5
FBAD10
FBAD15
FBAD8
FBAD13
FBAD12
FBAD9
FBAD14
FBAD11
J1
J7
1
C184
B7
A8
UDQS
UDQS
J2
VREF
A2
E2
L1
R3
R7
R8
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
PM@
220U_D2_4VM_R15
2
LDQS
LDQS
FBA_BA0
FBA_BA1
L2
L3
BA0
BA1
FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBAA5
FBAA4
FBAA3
FBAA2
FBAA1
FBAA0
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
FBACLK0#
FBACLK0
K8
J8
CK
CK
FBA_CKE
K2
CKE
FBACS0#
L8
CS
FBAWE#
K3
WE
FBARAS#
K7
RAS
FBACAS#
L7
CAS
FBADQM#2
FBADQM#3
F3
B3
LDM
UDM
+1.8VS
ODT
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
BA0
BA1
FBADQS1
FBADQS#1
K9
U28
C630
0.1U_0402_16V4Z
PM@
C617
1U_0402_6.3V4Z
PM@
FBAODT0
K9
FBADQS2
FBADQS#2
FBADQS3
FBADQS#3
+VRAM_VREFA
C91
0.047U_0402_16V4Z
PM@
Close to U4
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
FBAD25
FBAD29
FBAD24
FBAD31
FBAD28
FBAD27
FBAD30
FBAD26
FBAD18
FBAD23
FBAD17
FBAD21
FBAD19
FBAD16
FBAD22
FBAD20
B7
A8
UDQS
UDQS
J2
VREF
A2
E2
L1
R3
R7
R8
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
FBADQS#[0..7]
<17,21> FBADQS#[0..7]
FBADQM#[0..7]
FBA_BA0
<17,21> FBA_BA0
FBA_BA1
<17,21> FBA_BA1
1
2
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
FBADQS[0..7]
<17,21> FBADQS[0..7]
<17,21> FBADQM#[0..7]
J1
J7
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
FBAA[0..12]
<17,21> FBAA[0..12]
+1.8VS
C92
0.1U_0402_16V4Z
PM@
C98
1U_0402_6.3V4Z
PM@
FBAD[0..63]
<17,21> FBAD[0..63]
ODT
LDQS
LDQS
FBBA[2..5]
<17,21> FBBA[2..5]
FBAODT0
<17,21> FBAODT0
FBA_CKE
<17,21> FBA_CKE
FBARAS#
<17,21> FBARAS#
FBACAS#
<17,21> FBACAS#
FBAWE#
<17,21> FBAWE#
FBACS0#
<17,21> FBACS0#
Close to U5
<17>
FBACLK0
FBACLK0
X76@ HY5PS561621F-25
1
X76@ HY5PS561621F-25
F7
E8
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
FBABA2
<17,21> FBABA2
R104
475_0402_1%
DDR2 BGA MEMORY
DDR2 BGA MEMORY
<17,21> FBABA2
FBABA2
+1.8VS
<17>
+1.8VS
0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
1
C621
C622
C624
C626
C625
C619
C620
PM@
PM@
PM@
PM@
PM@
PM@
PM@
2
2
1000P_0402_50V7K
2
2
0.01U_0402_16V7K
2
1U_0402_6.3V4Z
C615
PM@
2
2
0.1U_0402_16V4Z
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
1
C110
C113
C130
C137
C143
C103
C100
PM@
PM@
PM@
PM@
PM@
PM@
PM@
2
2
1000P_0402_50V7K
2
2
0.01U_0402_16V7K
2
1U_0402_6.3V4Z
PM@
FBACLK0#
FBACLK0#
C158
PM@
2
2
0.1U_0402_16V4Z
0.01U_0402_16V7K
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
2008/10/15
Deciphered Date
4
Title

VRAM DDRA

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
20
of
53
U29
FBA_BA0
FBA_BA1
L2
L3
FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBBA5
FBBA4
FBBA3
FBBA2
FBAA1
FBAA0
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
FBACLK1#
FBACLK1
K8
J8
CK
CK
FBA_CKE
K2
CKE
FBACS0#
L8
CS
FBAWE#
K3
WE
FBARAS#
K7
RAS
FBACAS#
L7
FBADQM#7
FBADQM#5
F3
B3
U7
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
J1
J7
BA0
BA1
FBAD40
FBAD45
FBAD41
FBAD46
FBAD47
FBAD43
FBAD44
FBAD42
FBAD61
FBAD62
FBAD58
FBAD56
FBAD59
FBAD57
FBAD63
FBAD60
FBA_BA0
FBA_BA1
L2
L3
BA0
BA1
FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBBA5
FBBA4
FBBA3
FBBA2
FBAA1
FBAA0
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
FBACLK1#
FBACLK1
K8
J8
CK
CK
FBA_CKE
K2
CKE
FBACS0#
L8
CS
FBAWE#
K3
WE
FBARAS#
K7
RAS
FBACAS#
L7
FBADQM#6
FBADQM#4
F3
B3
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
J1
J7
FBAD39
FBAD34
FBAD38
FBAD35
FBAD32
FBAD36
FBAD33
FBAD37
FBAD55
FBAD51
FBAD52
FBAD50
FBAD49
FBAD54
FBAD48
FBAD53
FBAD[0..63]
<17,20> FBAD[0..63]
FBAA[0..12]
<17,20> FBAA[0..12]
FBBA[2..5]
<17> FBBA[2..5]
K9
FBADQS7
FBADQS#7
F7
E8
LDM
UDM
2
LDQS
LDQS
R184
1K_0402_1%
PM@
+VRAM_VREFB
FBADQS5
FBADQS#5
B7
A8
UDQS
UDQS
J2
VREF
A2
E2
L1
R3
R7
R8
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
1
2
R190
1K_0402_1%
PM@
C319
0.047U_0402_16V4Z
PM@
Close to U3
ODT
+1.8VS
FBAODT0
CAS
+1.8VS
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
C305
0.1U_0402_16V4Z
PM@
C224
1U_0402_6.3V4Z
PM@
K9
FBADQS6
FBADQS#6
F7
E8
FBADQS4
FBADQS#4
+VRAM_VREFB
FBAODT0
C672
0.047U_0402_16V4Z
PM@
Close to U7
X76@ HY5PS561621F-25
LDM
UDM
B7
A8
UDQS
UDQS
J2
VREF
A2
E2
L1
R3
R7
R8
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
<17,20> FBABA2
C654
0.1U_0402_16V4Z
PM@
C655
1U_0402_6.3V4Z
PM@
FBARAS#
<17,20> FBARAS#
FBACAS#
<17,20> FBACAS#
FBAWE#
<17,20> FBAWE#
FBACS0#
<17,20> FBACS0#
DDR2 BGA MEMORY
C233
PM@
2
2
0.1U_0402_16V4Z
0.01U_0402_16V7K
2
2
1000P_0402_50V7K
2
2
0.01U_0402_16V7K
2
1U_0402_6.3V4Z
C667
PM@
FBACLK1
<17> FBACLK1
0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
1
C668
C666
C665
C659
C656
C647
C642
PM@
PM@
PM@
PM@
PM@
PM@
PM@
R154
475_0402_1%
PM@
2
2
0.1U_0402_16V4Z
0.01U_0402_16V7K
2
1U_0402_6.3V4Z
FBA_CKE
<17,20> FBA_CKE
1
+1.8VS
0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
1
C272
C234
C225
C304
C269
C263
C239
PM@
PM@
PM@
PM@
PM@
PM@
PM@
2
2
0.01U_0402_16V7K
FBAODT0
<17,20> FBAODT0
+1.8VS
2
2
1000P_0402_50V7K
FBA_BA1
<17,20> FBA_BA1
FBABA2
DDR2 BGA MEMORY
FBA_BA0
<17,20> FBA_BA0
2
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
FBADQM#[0..7]
<17,20> FBADQM#[0..7]
ODT
LDQS
LDQS
FBADQS#[0..7]
<17,20> FBADQS#[0..7]
+1.8VS
X76@ HY5PS561621F-25
FBABA2
<17,20> FBABA2
CAS
FBADQS[0..7]
<17,20> FBADQS[0..7]
FBACLK1#
<17> FBACLK1#
Close to U7
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
2008/10/15
Deciphered Date
4
Title

VRAM DDRB

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
21
of
53
FSB
FSA
CLKSEL2
CLKSEL1
CLKSEL0
CPU
MHz
SRC
MHz
266
PCI
MHz
100
REF
MHz
33.3
14.318
DOT_96 USB
MHz
MHz
96.0
1
R364
+3VS
2
0_0805_5%
48.0
2
133
100
200
33.3
100
166
14.318
33.3
100
14.318
33.3
14.318
96.0
96.0
96.0
+3VM_CK505
+3VS
C419
10U_0805_10V4Z
C422
0.1U_0402_16V4Z
C420
0.1U_0402_16V4Z
C438
0.1U_0402_16V4Z
C457
0.1U_0402_16V4Z
C474
0.1U_0402_16V4Z
C473
R278
0.1U_0402_16V4Z
48.0
+1.5VS
1
R306
2
0_0805_5%
+VCCP
1
R389
2
0_0805_5%
+1.5VM_CK505
48.0
C421
C423
C472
C425
C463
C471
C444
333
100
33.3
14.318
96.0
48.0
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
100
100
33.3
14.318
96.0
48.0
400
100
33.3
14.318
96.0
48.0
U14
55
6
SDA
CLK_SMBDATA
SCL
10
CLK_SMBCLK
CLK_CPU_BCLK
VDD_SRC
CLK_SMBDATA <14,15>
12
VDD_PCI
CPU_0
71
72
VDD_CPU
CPU_0#
70
CLK_CPU_BCLK#
CPU_1
68
CLK_MCH_BCLK
CPU_1#
67
CLK_MCH_BCLK#
R_CLK_DOT R251
1
R255
1
R_CLK_DOT# R250
1
R254
1
19
VDD_48
27
VDD_PLL3
66
VDD_CPU_IO
SRC_0/DOT_96
24
31
VDD_PLL3_IO
SRC_0#/DOT_96#
25
SRC PORT LIST
CLK_SMBCLK <14,15>
VDD_REF
CLK_CPU_BCLK <5>
+1.5VM_CK505
MCH_CLKSEL0 <8>
R262
1K_0402_5%
62
VDD_SRC_IO
52
VDD_SRC_IO
23
CLK_MCH_BCLK <8>
CLK_MCH_BCLK# <8>
VDD_IO
38
VDD_SRC_IO
R268
33_0402_5% 1
<28> CLK_48M_ICH
1K_0402_5%
@
2 R270
33_0402_5% 1
<28> CLK_14M_ICH
+VCCP
2 R316
<BOM Structure>
2 R310
@
33_0402_5% 1
<37> CLK_14M_SIO
FSB
FS_B/TEST_MODE
FSC
REF_0/FS_C/TEST_
REF_1
1
11
1K_0402_5%
@
1
2
MCH_CLKSEL1 <8>
PM_STP_CPU#
<28> H_STP_CPU#
R366
1K_0402_5%
1
2
R367
0_0402_5%
CPU_BSEL1
<28> H_STP_PCI#
53
PM_STP_PCI#
R375
54
CLK_XTAL_IN
CLK_XTAL_OUT
0_0402_5%
@
<37> CLK_PCI_DB
33_0402_5% 1
<35> CLK_PCI_LPC
33_0402_5% 1
R303
1K_0402_5%
SRC_2
32
CLK_MCH_3GPLL
SRC_2#
33
CLK_MCH_3GPLL#
+3VS
+3VS
CLK_XTAL_OUT
NC
39
CLK_PCIE_CARD
SRC_4#
40
CLK_PCIE_CARD#
SRC_6
57
CLK_PCIE_WLAN
SRC_6#
56
CLK_PCIE_WLAN#
SRC_7
61
CPU_STOP#
PCI_STOP#
SRC_7#
60
SRC_8/CPU_ITP
64
SRC_8#/CPU_ITP#
63
XTAL_IN
XTAL_OUT
SRC_9
44
CLK_PCIE_LAN
SRC_9#
45
CLK_PCIE_LAN#
15
PCI_3
2 R289
PCI4_SEL
16
PCI_4/SEL_LCDCL
ITP_EN
17
+3VS
CLK_PCIE_CARD
<36>
CLK_PCIE_WLAN <32>
CLK_PCIE_WLAN# <32>
SRC_10
50
CLK_PCIE_ICH
SRC_10#
51
CLK_PCIE_ICH#
SRC_11
48
CLK_PCIE_SATA
SRC_11#
47
CLK_PCIE_SATA#
CLKREQ_3#
37
EXP_CLKREQ#
SATA_CLKREQ#_R
EXP_CLKREQ#
MCH_CLKREQ#_R
CLKREQ_LAN#
WLAN_CLKREQ#
CLK_PCIE_LAN <33>
CLK_PCIE_LAN# <33>
CLK_PCIE_ICH
CLK_PCIE_ICH#
VSS_PCI
VSS_REF
VSS_48
PORT
26
VSS_IO
CLKREQ_4#
41
69
VSS_CPU
CLKREQ_6#
58
30
VSS_PLL3
CLKREQ_7#
65
34
VSS_SRC
CLKREQ_9#
43
EXP_CLKREQ# <40>
WLAN_CLKREQ#
CLKREQ_LAN#
CLKREQ_LAN# <33>
SLKREQ_10#
49
CLKREQ_11#
46
SATA_CLKREQ#_R
R307 1
2 0_0402_5%
SATA_CLKREQ# <28>
10K_0402_5%
@
10K_0402_5%
PM@
10K_0402_5%
73
VSS
USB_1/CLKREQ_A#
21
MCH_CLKREQ#_R
R260 1
2 0_0402_5%
MCH_CLKREQ# <8>
REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#
WLAN_CLKREQ# <32>
VSS_SRC
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
REQ PORT LIST
VSS_SRC
1
1
1
1
1
CLK_PCIE_SATA# <27>
42
PCI2_TME
2
2
2
2
2
<28>
59
PCI4_SEL
R315
R295
R256
R304
R372
R275
R277
R276
10K_0402_5%
10K_0402_5%
GM@
10K_0402_5%
@
<28>
CLK_PCIE_SATA <27>
DEVICE
PCIE_EXP#
PCIE_WLAN
PCIE_WLAN1
PCIE_LAN
PCIE_SATA
MCH_3GPLL
SLG8SP556VTR_QFN72_10X10
Compal Secret Data
Issued Date
[email protected]
2007/10/15
Deciphered Date
2008/10/15
4
<36>
CLK_PCIE_CARD#
PCIF_5/ITP_EN
18
22
CLK_PCIE_EXP# <40>
+3VS
PCI_2
22P_0402_50V8J
Routing the trace at least 10mil
SRC_4
PCIE_LAN
PCIE_ICH
PCIE_SATA
CLK_PCIE_EXP <40>
R286
2
2
C476
CLK_PCIE_EXP#
CLK_MCH_3GPLL# <8>
R287
ITP_EN
Y2
14.31818MHZ_16PF_DSX840GA
CLK_PCIE_EXP
<8>
CLK_MCH_3GPLL <8>
R285
2
22P_0402_50V8J
C464
CLK_XTAL_IN
35
36
<8>
PCIE_WLAN
PCIE_WLAN1
0_0402_5%
@
SRC_3
PCI_1
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#

Pin28/29 : LCDCLK / LCDCLK#
1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS
R302
MCH_SSCDREFCLK#
13
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
1
2
R296
0_0402_5%
CPU_BSEL2
MCH_SSCDREFCLK
PCI2_TME 14
2 R288
CLK_MCH_DREFCLK <8>
CLK_PCIE_VGA <16>
CLK_MCH_DREFCLK# <8>
CLK_PCIE_VGA# <16>
28
SRC_3#
DEVICE
MCH_DREFCLK
MCH_3GPLL
PCIE_EXP#
CKPWRGD/PD#
MCH_CLKSEL2 <8>
<6>
33_0402_5% 1
<26> CLK_PCI_ICH
FSC
1K_0402_5%
@
1
2
R311
10K_0402_5%
2
1
R312
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
29
2 R290
+VCCP
GM@
PM@
GM@
PM@
LCDCLK/27M
USB_0/FS_A
<6>
20
FSB
CK_PWRGD
<28> CK_PWRGD
R376
FSA
2
2
2
2
LCDCLK#/27M_SS
1
2
R257
0_0402_5%
CPU_BSEL0
R261
PORT
SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11
CLK_CPU_BCLK# <5>
+VCCP
<6>
CLK_SMBCLK
SA000020K00 (Silego : SLG8SP556VTR )

SA000020H00 (ICS : ICS9LPRS387AKLFT)
+3VM_CK505
56_0402_5%
@
1
2
Q27B
2N7002DW-T/R7_SOT363-6
Reserved
R267
2.2K_0402_5%
FSA 2
1
CLK_SMBDATA
<28,32,40> ICH_SMBCLK
10U_0805_10V4Z
2.2K_0402_5%
+3VS
<28,32,40> ICH_SMBDATA
48.0
R263
2.2K_0402_5%
2N7002DW-T/R7_SOT363-6
Q27A
FSC
Title

Clock generator
Size
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Date:
Sheet
1
22
of
53
+3VS
+3VS
+3VS
4.7K_0402_5%1
0_0402_5%
1
@
@
OE#
HDMICLK
28
SCL_SINK
HDMIDAT
29
SDA_SINK
30
HPD_SINK
32
DDC_EN
34
35
CFG0
CFG1
HDMI_GM@
R209
HDMI_DETECT
R210
@
4.7K_0402_5% 2
4.7K_0402_5% 2
1 R697
1 R696
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
2
11
15
21
26
33
40
46
PC1
PC0
4
3
1
C374
1
C335
HDMI_GM@
+3VS
R187
2.2K_0402_5%
default : pull low

HDMI_GM@
4.7K_0402_5% 2
@
4.7K_0402_5% 2
R188
2.2K_0402_5%
HDMI_GM@
1 R695
1 R664
R189 1 HDMI_GM@
2 499_0402_1%
HPD#
HDP 1 HDMI_GM@
2
R665
0_0402_5%
SDA
HDMIDAT_NB
<8>
SCL
HDMICLK_NB
<8>
REXT
48
47
IN_D4+
IN_D4-
HDMI_GM@
9/13 Add inverting lavel shift

circuit base on Design Guide P.277
9/14 Change from 4.7K to 2.2K

base on Design Guide P.274
default : pull low
<10> TMDS_B_DATA2
<10> TMDS_B_DATA2#
+3VS
09/13 change pull high enable

D
25
1
C318
HDMI_GM@HDMI_GM@HDMI_GM@
2
2
2
U8
R211
@
1
C357
R212
10U_0805_10V4Z
0.1U_0402_16V4Z
@
2
0_0402_5%
0.1U_0402_16V4Z
4.7K_0402_5%1
0.1U_0402_16V4Z
09/13 change pull low enable
+3VS
TMDS_B_HPD# <10>
RT_EN#
10
OUT_D4+
OUT_D4-
13
14
HDMI_TX2+
HDMI_TX2HDMI_TX1+
HDMI_TX1-
<10> TMDS_B_DATA1
<10> TMDS_B_DATA1#
45
44
IN_D3+
IN_D3-
OUT_D3+
OUT_D3-
16
17
<10> TMDS_B_DATA0
<10> TMDS_B_DATA0#
42
41
IN_D2+
IN_D2-
OUT_D2+
OUT_D2-
19
20
HDMI_TX0+
HDMI_TX0-
<10> TMDS_B_CLK
<10> TMDS_B_CLK#
39
38
IN_D1+
IN_D1-
OUT_D1+
OUT_D1-
22
23
HDMI_CLK+
HDMI_CLK-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PAD
1
5
12
18
24
27
31
36
37
43
49
TMDS pull down (500ohm) resistors G9x only

HDMI_CLK+_CONN
R155 1 HDMI_PM@
2 499_0402_1%
HDMI_CLK-_CONN
R156 1 HDMI_PM@
2 499_0402_1%
HDMI_TX0+_CONN
R150 1 HDMI_PM@
2 499_0402_1%
HDMI_TX0-_CONN
R153 1 HDMI_PM@
2 499_0402_1%
HDMI_TX1+_CONN
R145 1 HDMI_PM@
2 499_0402_1%
HDMI_TX1-_CONN
R149 1 HDMI_PM@
2 499_0402_1%
HDMI_TX2+_CONN
R141 1 HDMI_PM@
2 499_0402_1%
HDMI_TX2-_CONN
R144 1 HDMI_PM@
2 499_0402_1%
<17>
<17>
<17>
<17>
<17>
<17>
<17>
<17>
PS8101TQFN48G_QFN48_7X7
HDMI_GM@
C369
C362
C350
C341
C324
C321
C313
C308
VGA_HDMI_CLKVGA_HDMI_CLK+
R228
R227
<16> VGA_HDMI_SDA
<16> VGA_HDMI_SCL
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
HDMI_PM@
0.1U_0402_10V7K
HDMI_PM@
0.1U_0402_10V7K
HDMI_PM@
0.1U_0402_10V7K
HDMI_PM@
0.1U_0402_10V7K
HDMI_PM@
0.1U_0402_10V7K
HDMI_PM@
0.1U_0402_10V7K
HDMI_PM@
0.1U_0402_10V7K
HDMI_PM@
0.1U_0402_10V7K
HDMI_CLKHDMI_CLK+
HDMI_TX0HDMI_TX0+
HDMI_TX1HDMI_TX1+
HDMI_TX2HDMI_TX2+
1 HDMI_PM@ 0_0402_5% HDMIDAT

1 HDMI_PM@ 0_0402_5% HDMICLK
2
2
NEAR CONNECT
D
Q4
2N7002_SOT23
2
G
+3VS
S
HDMI_PM@
<16> HDMI_DETECT_VGA
1 @
HDMI@
4 4
HDMI_TX0+_CONN
HDMI_TX0-_CONN
R215 2 HDMI_PM@
0_0402_5%
L34
1 1
HDMI@
4 4
HDMI_TX1-
HDMI_TX1+_CONN
HDMI_TX1-_CONN
+5VS
HDMI@
R198
2.2K_0402_5%
D25
D26
L43
HDMIDAT
1
2
1
@
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_PM@ HDMI_PM@
2
HDMI_TX0-_CONN
12P_0402_50V8J 2
12P_0402_50V8J
L44
HDMI_TX0+_CONN
HDMI_TX1-_CONN
HDMICLK
HDMI_TX1+_CONN
HDMI_TX2-_CONN
0_0603_5% 0_0603_5%
HDMI_TX2+
0_0402_5%
L33
1 1
1 @
HDMI@
4 4
HDMI_TX2-
BAT54S-7-F_SOT23-3
@
2 R693
2
3
HDMI_TX2+_CONN
HDMI_TX2-_CONN
HDMI_GM@
HDMI_TX2+_CONN
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
TYCO_16-004-6131
ME@
Compal Secret Data
WCM-2012-900T_4P
0_0402_5% 1 @
2 R694
[email protected]
HDMI_GM@
BAT54S-7-F_SOT23-3
@
C276HDMI@
0.1U_0402_16V4Z
JHDMI1
3
1
C806
0.1U_0402_16V4Z
HDMI@
R194
2.2K_0402_5%
L43 HDMI_PM@ MBK1608121YZF_0603

1
2
1
2
L44 HDMI_PM@ MBK1608121YZF_0603
1
1
C774
C775
+5VS
WCM-2012-900T_4P
0_0402_5% 1 @
2 R692
2
1
HDMI_PM@
HDMIDAT
HDMICLK
2 R691
2
+5VS_HDMI
HDMI_PM@
1 @
D2 HDMI@
RB411DT146_SOT23-3
C338
330P_0402_50V7K
R199
10K_0402_1%
HDMI@
BAT54S-7-F_SOT23-3
0_0402_5%
WCM-2012-900T_4P
0_0402_5% 1 @
2 R690
HDMI_TX1+
1
3
1
@
2 R689
2
HDMI_TX0-
HDMI_PM@
D3
RB751V_SOD323
2
0_0402_5%
L35
1 1
L16
HDMI_PM@
1
2
FBML10160808121LMT_0603
1
WCM-2012-900T_4P
0_0402_5% 1 @
2 R688
HDMI_TX0+
R200
1
2
1K_0402_1%
HDMI_DETECT_VGA
HDMI_CLK-_CONN
HDMI_GM@
R725
0_0805_5%
D4
HDMI@
4 4
HDMI_CLK-
HDMI_CLK+_CONN
+5VS
R216 2 HDMI_GM@
0_0402_5%
9/14 Reserve for VGA

used;check pin name
2 R687
0_0402_5% 1 @
L36
1 1
HDMI_CLK+
HDMI_DETECT
C792
1800P_0402_50V7K
+5VS
Issued Date
2007/10/15
Deciphered Date
2008/10/15
4
Title

Level shiftter-CH7318
Size
Document Number
Rev
1.0
JIWA3/A4_LA-4212P
Date:
Thursday, May 22, 2008
Sheet
1
23
of
53
INVERTER Conn.
INVT_PWM
LCD POWER CIRCUIT
DAC_BRIG
DISPOFF#
JP2
+5VALW
<35>
INVT_PWM
<35>
L2
2
1
FBMA-L11-201209-221LMA30T_0805
DAC_BRIG
B+
+3VS
C23
C22
D
2
470P_0402_50V7K
For EMI
+LCDVDD
W=60mils
1
C1
+3VS
1
2
Q1
DTC124EKAT146_SC59-3
Q3
C3
R377
4.7U_0805_10V4Z
2
PM@
0.1U_0603_25V7K
0.1U_0402_16V4Z
4.7K_0402_5%
D13
<35>
BKOFF#
IN
1
<16> VGA_ENVDD
1
OUT
2 0_0402_5%
R1
10K_0402_5%
C18
4.7U_0805_10V4Z
C21
SI2301BDS-T1-E3_SOT23-3
1
GND
2 0_0402_5%
1 2
3
C4
470P_0402_50V7K
G8 8
2
2
G9 9
470P_0402_50V7K
ACES_87213-0700G
1
ME@
C789
470P_0603_50V8J
2
0.47U_0402_6.3V6K
R3
220K_0402_5%
2
C2
DTC124EK
GM@
R2
R6
1
+INVPWR_B+
2
G
Q2
2N7002_SOT23 S
DISPOFF#
<10> GM_ENVDD
R5
100K_0402_5%
R4
150_0603_1%
W=60mils
1
2
3
4
5
6
7
BKOFF#
2
1
R358
GM@ 0_0402_5%
2
1
R351
PM@ 0_0402_5%
<10> GMCH_ENBKL
<16> VGA_ENBKL
DISPOFF#
ENBKL
ENBKL
<35>
+LCDVDD
1
2
3
4
5
6
7
R368
10K_0402_5%
LCD/PANEL BD. Conn.
LCD/PANEL BD. Conn.

+3VS
JLVDS2
GND 22
GND 21
20 20
19 19
18 18
17 17
16 16
15 15
14 14
13 13
12 12
11 11
10 10
9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
+LCDVDD_CONN
L1
2
(60 MIL)
R18
2.2K_0402_5%
+LCDVDD GM@
JLVDS1
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R17
2.2K_0402_5%
GM@
GND
GND
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FBMA-L11-201209-221LMA30T_0805
+3VS
LVDS_SDA <10>
LVDS_SCL <10>
LVDS_ACLK
LVDS_ACLK#
LVDS_ACLK <10>
LVDS_ACLK# <10>
LVDS_A1
LVDS_A1#
LVDS_A1 <10>
LVDS_A1# <10>
LVDS_A0
LVDS_A0#
LVDS_A0 <10>
LVDS_A0# <10>
LVDS_A2
LVDS_A2#
LVDS_A2 <10>
LVDS_A2# <10>
ME@
ACES_87212-2000L
+3VS
+LCDVDD_CONN
R22
2.2K_0402_5%
PM@
R21
2.2K_0402_5%
PM@
(60 MIL)
+3VS
VGA_LVDS_SDA
VGA_LVDS_SCL
VGA_LVDS_ACLK
VGA_LVDS_ACLK#
VGA_LVDS_ACLK <17>
VGA_LVDS_ACLK# <17>
VGA_LVDS_A1
VGA_LVDS_A1#
VGA_LVDS_A1 <17>
VGA_LVDS_A1# <17>
VGA_LVDS_A0
VGA_LVDS_A0#
VGA_LVDS_A0 <17>
VGA_LVDS_A0# <17>
VGA_LVDS_A2
VGA_LVDS_A2#
VGA_LVDS_A2 <17>
VGA_LVDS_A2# <17>
VGA_LVDS_SDA <16>
VGA_LVDS_SCL <16>
ME@
ACES_87212-2000L
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
2008/10/15
Deciphered Date
4
Title

LVDS & DVI Connector
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
24
of
53
CRT Connector
Place closed to chipset
<16> VGA_CRT_B
<10> GMCH_CRT_B
CRT_R_1
1
L20
0_0402_5%
0_0402_5%
CRT_B_1
0_0402_5%
0_0402_5%
R230
1
L18
R223
R219
C406
10P_0402_50V8J
2
150_0402_1%
D18
2
<BOM Structure>
1
2
L19
FCM1608C-121T_0603
CRT_G_1
0_0402_5%
0_0402_5%
150_0402_1%
1
C391
10P_0402_50V8J
2
0.1U_0402_16V4Z
RED
2
FCM1608C-121T_0603
GREEN
BLUE
2
FCM1608C-121T_0603
C679
W=40mils
1
10P_0402_50V8J
2
C405
10P_0402_50V8J
2
RED
C390
10P_0402_50V8J
2
JVGA_HS
BLUE
C384
10P_0402_50V8J
JVGA_VS
150_0402_1%
CRT_DDC_CLK
+CRT_VCC
5
P
2
PM@ 0_0402_5%
2
GM@ 0_0402_5%
1
1K_0402_5%
JVGA_HS
2
FCM1608C-121T_0603
JVGA_VS
ME@
U11
CRT_HSYNC_1
@ C412
10P_0402_50V8J
SN74AHCT1G125DCKR_SC70-5
16
17
ALLTO_C10534-91507
<BOM Structure>
1
2
L21
FCM1608C-121T_0603
1
R241
1
R240
<10> GMCH_CRT_HSYNC
2
R239
<BOM Structure>
<16> VGA_HSYNC
1
L22
2
0.1U_0402_16V4Z
OE#
1
C413
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
CRT_DDC_DAT
GREEN
C385
RB491D_SC59-3
<16> VGA_CRT_G
<10> GMCH_CRT_G
2
2 PM@
GM@
2
2 PM@
GM@
2
2 PM@
GM@
1
R229 1
R231
1
R221 1
R224
1
R214 1
R218
<16> VGA_CRT_R
<10> GMCH_CRT_R
+CRT_VCC
+5VS
@ C408
10P_0402_50V8J
2
+CRT_VCC
2
0.1U_0402_16V4Z
<10> GMCH_CRT_VSYNC
2
PM@ 0_0402_5%
2
GM@ 0_0402_5%
U10
Y
PIN ASSIGMENT
CRT_VSYNC_1
1
R233
1
R235
<16> VGA_VSYNC
OE#
1
C410
Place closed to chipset
D-SUB
9
1
6
2
7, 5
3
8
14
10
13
11
12
15
4
SN74AHCT1G125DCKR_SC70-5
+5VS
+5VS
+5VS
+3VS
GM@
2
0_0402_5%
<10> GMCH_CRT_CLK
2
0_0402_5%
<16> VGA_DDCCLK
GM@
PM@
R644
RED
1
2
R643
GREEN
BAT54S-7-F_SOT23-3
@
BAT54S-7-F_SOT23-3
@
2.2K_0402_5%
2
2
0_0402_5%
2.2K_0402_5%
R252
2
BAT54S-7-F_SOT23-3
@
R253
<10> GMCH_CRT_DATA
PM@
R266
2
0_0402_5%
BLUE
+3VS
D29
3
1
R269
2
<16> VGA_DDCDATA
D28
2.2K_0402_5%
R247
2.2K_0402_5%
+CRT_VCC
2.2K
D27
2.2K
CRT_DDC_DAT
3
Q23B
2N7002DW-T/R7_SOT363-6
CRT_DDC_CLK
6
Q23A
2N7002DW-T/R7_SOT363-6
R264
C414
@
100P_0402_50V8J
C417
@
68P_0402_50V8K
FUNCTION
+CRT_VCC
RED
GND
GREEN
GND
BLUE
GND
VSYNC
GND
HSYNC
SENSE
SM_DAT
SM_CLK
PIN4
Compal Secret Data
2007/10/15
Issued Date
2008/10/15
Deciphered Date
A
[email protected]
Title

CRT & TV-OUT Connector

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet
E
25
of
53
+3VS
D
1
R425
1
R420
1
R430
1
R415
1
R464
1
R453
1
R449
1
R438
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
PCI_DEVSEL#
1
R428
1
R580
1
R402
1
R563
1
R448
1
R427
1
R457
1
R456
1
R463
1
R419
1
R396
1
R426
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
PCI_PIRQA#
PCI_STOP#
U34B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
+3VS
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
PCI_REQ0#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCI_REQ1#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ2#
PCI_REQ3#
PCI_GNT0#
J5
E1
J6
C4
PCI
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7
PCI_IRDY#
PCI_PAR
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLTRST#
PCICLK
PME#
C14
D4
R2
PLT_RST#
CLK_PCI_ICH
PCI_PME#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
H4
K6
F2
G2
PCI_REQ0#
PCI_GNT0#
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3 <33>
PCI_IRDY#
PCI_PAR
PCI_DEVSEL#
Place closely pin D4

CLK_PCI_ICH
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
R444
C
CLK_PCI_ICH <22>
PCI_PME# <35>
2
C567
+3VALW
@ 8.2P_0402_50V
@ 10K_0402_5%
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
10_0402_5%
PCI_PIRQG#
Pull high?
R326
@ 1K_0402_5%
PCI_GNT3#
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9-M ES_FCBGA676
1
2
D8
B4
D6
A5
R434
@ 1K_0402_5%
@ 1K_0402_5%
C/BE0#
C/BE1#
C/BE2#
C/BE3#
R575
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
SB_SPI_CS#1
<28> SB_SPI_CS#1
R433
F1
G4
B6
A7
F13
F12
E6
F6
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
PCI_AD[0..31]
PCI_FRAME#
PCI_TRDY#
Boot BIOS Strap
PCI_RST#
PCI_RST# <35,37>
1
A16 Swap Override Strap

Low= A16 swap override Enable
High= Default*
Boot BIOS Loaction
SPI
PCI
LPC*
R576
100K_0402_5%
PLT_RST#
PLT_RST# <8,16,32,33,36,40>
1
PCI_GNT#3
SPI_CS#1
PCI_GNT#0
R390
100K_0402_5%
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
2008/10/15
Deciphered Date
4
Title

ICH9M(1/4)-PCI
Size
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Date:
Sheet

1
26
of
53
+3VS
R407
GATEA20
+RTCVCC
NC
IN
NC
OUT
+RTCVCC
2 C706
12P_0402_50V8J
1
2
R324
20K_0402_5%
1
2
+VCCP
U34A
RTCX1
RTCX2
ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#
A25
F20
C22
RTCRST#
SRTCRST#
INTRUDER#
ICH_INTVRMEN
LAN100_SLP
B22
A22
INTVRMEN
LAN100_SLP
E25
GLAN_CLK
C13
LAN_RSTSYNC
2
2MM
100_0402_1%
C451
C470
0.1U_0402_16V4Z
2
1U_0603_10V4Z
close to RAM door

+1.5VS
24.9_0402_1%
R305 1
2
HDA_BITCLK_R
2
33_0402_5%
HDA_SYNC_R
2
0_0402_5%
HDA_RST_R#
1 R550
2
0_0402_5%
1 R559
<8,16,30> HDA_SYNC_CODEC
C
GLAN_COMP
1 R554
<8,16,30> HDA_BITCLK_CODEC
<8,16,30> HDA_RST_CODEC#
1 R557
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
<39> SATA_DTX_C_IRX_N1
<39> SATA_DTX_C_IRX_P1
<39> SATA_ITX_DRX_N1
<39> SATA_ITX_DRX_P1
SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_DRX_N1
SATA_ITX_DRX_P1
1
C721 1
C719
1
C677 1
C678
D13
D12
E13
LAN_TXD_0
LAN_TXD_1
LAN_TXD_2
B10
GPIO56
B28
B27
GLAN_COMPI
GLAN_COMPO
AF6
AH4
HDA_BIT_CLK
HDA_SYNC
HDA_SDOUT_R AG5
2
0_0402_5%
10K_0402_5%
2
1 R549
SATA_LED#
<39> SATA_LED#
LAN_RXD0
LAN_RXD1
LAN_RXD2
AE7
<8> HDA_SDIN0
<16> HDA_SDIN1
<30> HDA_SDIN2
+3VS
F14
G13
D14
AF4
AG4
AH3
AE5
<8,16,30> HDA_SDOUT_CODEC
2
2 0.01U_0402_16V7K
0.01U_0402_16V7K
2
2 0.01U_0402_16V7K
0.01U_0402_16V7K
LPC_AD[0..3]
C23
C24
ICH_RTCX2
CLRP1
+RTCBATT
R322
R515
10M_0402_5%
K5
K4
L6
K2
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
FWH4/LFRAME#
K3
LPC_FRAME#
LDRQ0#
LDRQ1#/GPIO23
J3
J1
LPC_DRQ0#
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
LPC
1
+RTCVCC
10K_0402_5%
CPU
32.768KHZ_12.5P_1TJS125BJ2A251
R462
KB_RST#
RTC
330K_0402_1%
2 ICH_INTVRMEN
ICH_RTCX1
Y4
LAN / GLAN
R517
1
2 C707
12P_0402_50V8J
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDOUT
AG7
AE8
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
AJ16
AH16
AF17
AG17
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1
AH13
AJ13
AG14
AF14
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
R510
<35,37>
H_DPSLP#
@
1
56_0402_5%
R514
@
1
56_0402_5%
LPC_DRQ0# <37>
GATEA20
H_A20M#
N7
AJ27
DPRSTP#
DPSLP#
AJ25 H_DPRSTP_R# R511 2

H_DPSLP#
AE23
GATEA20 <35>
H_A20M# <5>
FERR#
AJ26
H_FERR#_S
CPUPWRGD
AD22
H_PWRGOOD
IGNNE#
AF25
H_IGNNE#
INIT#
INTR
RCIN#
AE22
AG25
L3
H_INIT#
H_INTR
KB_RST#
NMI
SMI#
AF23
AF24
H_NMI
H_SMI#
STPCLK#
AH27
H_STPCLK#
THRMTRIP#
AG26
THRMTRIP_ICH#
R509
1 0_0402_5%
56_0402_5% 2
+VCCP
H_DPRSTP#
H_DPSLP#
H_DPRSTP# <6,8,51>
H_DPSLP# <6>
56_0402_5%
1 R20
H_FERR# <5>
H_PWRGOOD <6>
H_IGNNE# <5>
H_INIT# <5>
H_INTR <5>
KB_RST# <35>
H_NMI <5>
H_SMI# <5>
H_STPCLK# <5>
R112 1
2 54.9_0402_1%
H_THERMTRIP#
2
R114
TP12
AG27
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AH11
AJ11
AG12
AF12
R541 2
R540 2
@
@
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AH9
AJ9
AE10
AF10
R544 2
R547 2
@
@
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
AH18
AJ18
AJ7
AH7
1 1K_0402_5%
1 1K_0402_5%
H_THERMTRIP# <5,8>
1
56_0402_5%
+VCCP
R329 need to place within 2" of ICH9M

R328 must be place within 2" of R258 w/o stub.
1 1K_0402_5%
1 1K_0402_5%
CLK_PCIE_SATA#
CLK_PCIE_SATA
SATARBIAS
H_DPRSTP#
LPC_FRAME# <35,37>
A20GATE
A20M#
HDA_RST#
IHDA
1M_0402_5%
2 SM_INTRUDER#
SATA
330K_0402_1%
2 LAN100_SLP
R513
1
R520
1
10K_0402_5%
CLK_PCIE_SATA# <22>
CLK_PCIE_SATA <22>
R5532
10mils width less than 500mils

24.9_0402_1%
ICH9-M ES_FCBGA676
Need check
+3VS
2
XOR Chain Entrance Strap

ICH_TP3
HDA_SDOUT_R
R556
1K_0402_5%
@
HDA_SDOUT Description
RSVD
Enter XOR Chain
Normal Operation
Set PCIE port config bit 1
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
2008/10/15
Deciphered Date
4
Title

ICH9M(2/4)-LAN,IDELPC,RTC

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
27
of
53
+3VALW
+3VS
+3VALW
1 GPIO49
1K_0402_5%
TV TUNER
NEW CARD
<36>
<36>
<36>
<36>
<32>
<32>
<32>
<32>
<40>
<40>
<40>
<40>
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1
PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3
PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4
1
1
1 R328
D
2 VRMPWRGD
@ 0_0402_5%
<33> PCIE_RXN6
<33> PCIE_RXP6
<33> PCIE_TXN6
<33> PCIE_TXP6
Q29
@ RHU002N06_SOT323
2
G
3
<51> CLK_ENABLE#
LAN
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
5
6
7
8
4
3
2
1
0.1U_0402_10V7K
0.1U_0402_10V7K
USB_OC#6
USB_OC#1
USB_OC#2
USB_OC#4
PERN1
PERP1
PETN1
PETP1
L29
L28
M27
M26
PERN2
PERP2
PETN2
PETP2
C454
C453
PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3
J29
J28
K27
K26
PERN3
PERP3
PETN3
PETP3
C439
C440
PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4
G29
G28
H27
H26
PERN4
PERP4
PETN4
PETP4
E29
E28
F27
F26
PERN5
PERP5
PETN5
PETP5
C29
C28
D27
D26
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
D23
D24
F23
SPI_CLK
SPI_CS0#
SPI_CS1#GPIO58/CLGPIO6
D25
E23
SPI_MOSI
SPI_MISO
C435
C436
PCIE_RXN6
PCIE_RXP6
PCIE_C_TXN6
PCIE_C_TXP6
C449
C450
<38> FWR#SPI_SI_SB
<38> FRD#SPI_SO_SB
<43>
<43>
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11
USB_OC#0
USB_OC#1
10K_1206_8P4R_5%
RP14
5
6
7
8
4
3
2
1
USB_OC#5
USB_OC#7
USB_OC#9
USB_OC#0
<43> USB_OC#11
10K_1206_8P4R_5%
2
1
22.6_0402_1%
USBRBIAS
R447
RP13
5
6
7
8
4 USB_OC#8
3 USB_OC#3
2 USB_OC#10
1 USB_OC#11
Within 500 mils
M2
B13
1
2 R574
499_0402_1%
ICH_LOW_BAT#
PWRBTN#
R3
PBTN_OUT#
LAN_RST#
D20
<35>
<35>
<35>
D22
EC_RSMRST#R
CK_PWRGD_R
CLPWROK
R6
M_PWROK
SLP_M#
B16
T78
CL_CLK0
CL_CLK1
F24
B19
R170 100_0402_5%
M_PWROK
1
2
ICH_POK <8,35>
1
2 R362
@ 10K_0402_5%
DPRSLPVR <8,51>
DPRSLPVR
CL_DATA0
CL_DATA1
F22
C19
CL_VREF0
CL_VREF1
C25
A19
CL_VREF0_ICH
CL_VREF1_ICH
CL_RST0#
CL_RST1#
F21
D18
CL_RST#
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9
A16
C18
C11
C20
GPIO24
EC_RSMRST#R 1
R335
2 CK_PWRGD
0_0402_5%
1
R423
N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3
AG2
AG1
SPI
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#/GPIO44
OC9#/GPIO45
OC10#/GPIO46
OC11#/GPIO47
USB
1
C441
R301
453_0402_1%
0.1U_0402_16V4Z
CL_CLK0 <8>
CL_DATA0 <8>
T3
1
1
CL_RST# <8>
T4
C717
R528
453_0402_1%
0.1U_0402_16V4Z
+3VALW
2
R356
WOL_EN
1
2
R357
100K_0402_5%
@
ACIN
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN0 <8>
DMI_RXP0 <8>
DMI_TXN0 <8>
DMI_TXP0 <8>
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y27
Y26
W29
W28
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN1 <8>
DMI_RXP1 <8>
DMI_TXN1 <8>
DMI_TXP1 <8>
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB27
AB26
AA29
AA28
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN2 <8>
DMI_RXP2 <8>
DMI_TXN2 <8>
DMI_TXP2 <8>
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD27
AD26
AC29
AC28
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
DMI_RXN3 <8>
DMI_RXP3 <8>
DMI_TXN3 <8>
DMI_TXP3 <8>
T26
T25
CLK_PCIE_ICH#
CLK_PCIE_ICH
1
0_0402_5%
DMI_IRCOMP
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
RSMRST circuit
R271
@
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
Q26
3
<35> EC_RSMRST#
BAV99DW-7_SOT363
R272
@ 2.2K_0402_5%
EC_RSMRST#R1
R714
0_0402_5%
2
POK
<45,47>
MMBT3906_SOT23-3
1
2
+3VALW
R279
4.7K_0402_5%
D8B
D8A
BAV99DW-7_SOT363
1
R274
2.2K_0402_5%
Within 500 mils

+1.5VS
<43>
<43>
<43>
<43>
<40>
<40>
LEFT USB
LEFT USB
RIGHT USB
USB20_N6 <32>
USB20_P6 <32>
BT
USB20_N8 <32>
USB20_P8 <32>
WLAN
USB20_N10
USB20_P10
USB20_N11
USB20_P11
New Card
RIGHT USB
<40>
<40>
<43>
<43>
USB PORT LIST

PORT
USB20_N4 <43>
USB20_P4 <43>
USBRBIAS
USBRBIAS#
0_0402_5%
2
CLK_PCIE_ICH# <22>
CLK_PCIE_ICH <22>
R297 24.9_0402_1%
1
2
<35,44>
D14 RB751V_SOD323
2
1 ACIN
GPIO14
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2
R383 3.24K_0402_1%
1
2
+3VALW
V27
V26
U29
U28
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
R320 3.24K_0402_1%
1
2
+3VS
1
VGATE
1
2
R707 100_0402_5%
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI_ZCOMP
DMI_IRCOMP
0
2
3
4
6
8
10
11
DEVICE
LEFT SIDE
CMOS
3G
RIGHT SIDE
BT
WIRELESS
NEW CARD
RIGHT SIDE
ICH9-M ES_FCBGA676
Compal Secret Data

2007/10/15
Issued Date
2008/10/15
Deciphered Date
4
2
10K_0402_5%
CK_PWRGD <22>
M_PWROK <8>
T2
AF29
AF28
C576
22P_0402_50V8J
PBTN_OUT# <35>
R5
DMI_CLKN
DMI_CLKP
CK_PWRGD
RSMRST#
ICH_POK
BATLOW#
1
S4_STATE#
G20
10K_1206_8P4R_5%
[email protected]
N29
N28
P27
P26
SB_SPI_CS#1
<26> SB_SPI_CS#1
RP15
+3VALW
SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10
C10
PWROK
1
1
0.1U_0402_10V7K
0.1U_0402_10V7K
<38> SPI_CLK_SB
<38> FSEL#SPICS#_SB
SPI not used, Left NC
GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
S4_STATE#/GPIO26
SLP_S3#
SLP_S4#
SLP_S5#
C733
10P_0402_50V8J
ICH9-M ES_FCBGA676
U34D
PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1
+3VS
R319
@ 330_0402_5%
M7
AJ24
B21
AH20
AJ20
AJ21
High -->No boot
SB_SPKR
2
@ 10K_0402_5%
1
R408
TP11
T96
T97
T95
low-->default
WLAN
+3VS
A20
SLP_S3#
SLP_S4#
SLP_S5#
1 2
2 @
SST_CTL
SLP_S3#
SLP_S4#
SLP_S5#
C16
E16
G17
T101
1 ICH_RSVD
1K_0402_5%
VRMPWRGD
ICH_SUSCLK
2
@
D21
P1
DPRSLPVR/GPIO16
R460
33_0402_5%
R522
VRMPWRGD
SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD
<30>
SB_SPKR
<8> MCH_ICH_SYNC#
WAKE#
SERIRQ
THRM#
CLK_14M_ICH <22>
CLK_48M_ICH <22>
SUSCLK
R573
2 GPIO57
100K_0402_5%
2 DPRSLPVR
100K_0402_5%
R512
<22> SATA_CLKREQ#
GPIO7
GPIO13
GPIO17
GPIO18
GPIO20
GPIO22
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
@
1
@
R411
EC_SMI#
EC_SCI#
CLKRUN#
CLK_14M_ICH
CLK_48M_ICH
H1
AF3
2
2
2
2
2
2
STP_PCI#
STP_CPU#
AG19
AH21
GPIO7
AG21
EC_SMI#
A21
EC_SCI#
C12
GPIO13
C21
GPIO17
AE18
GPIO18
K1
GPIO20
AF8
GPIO22
AJ22
GPIO27
A9
D19
SATA_CLKREQ#
L1
GPIO38
AE19
GPIO39
AG22
GPIO48
AF21
GPIO49
AH24
GPIO57
A8
2 WOL_EN
100K_0402_5%
A14
E19
OCP#
OCP#
CPUSB#
T76
LID_OUT#
10K_0402_5%
SMBALERT#/GPIO11
L4
CLK_14M_ICH
R566
10_0402_5%
R551
10K_0402_5%
@
@
2
0_0402_5%
PMSYNC#/GPIO0
A17
ICH_PCIE_WAKE# E20
SERIRQ
M5
EC_THERM#
AJ23
CLK14
CLK48
clocks
AH23
AF19
AE21
AD20
<40>
<35>
<35>
1 ICH_LOW_BAT#
8.2K_0402_5%
1
1
1
1
1
1
R349
R365
R363
R578
R548
R521
1
R334
VGATE
12/14 changed from +3VS to +3VALW

+3VS
PCI_CLKRUN#
T98
2
1
R524
1
0_0402_5%
M6
SATA
GPIO
<8,51>
R539
PCI_CLKRUN#
SUS_STAT#/LPCPD#
SYS_RESET#
2LID_OUT#
0_0402_5%
H_STP_PCI#
R_STP_CPU#
<32,33,40> ICH_PCIE_WAKE#
<35,37> SERIRQ
<35> EC_THERM#
2 ICH_PCIE_WAKE#
1K_0402_5%
XDP_DBRESET#
R4
G19
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
R546
R348
Place closely pin AC1
CLK_48M_ICH
R350
<22> H_STP_PCI#
<22> H_STP_CPU#
2 ICH_RI#
10K_0402_5%
R360
RI#
PM_BMBUSY#
1
R532
<35> EC_LID_OUT#
2 XDP_DBRESET#
10K_0402_5%
R374
@R538
@
R538
<8> PM_BMBUSY#
10K_0402_5%
2 CL_RST#
10K_0402_5%
1 @
R338
@ R332
10K_0402_5%
2 LINKALERT#
10K_0402_5%
R370
F19
SYS / GPIO
2 GPIO48
10K_0402_5%
<5> XDP_DBRESET#
2 GPIO39
10K_0402_5%
ICH_RI#
SMB
Power MGT
+3VALW
SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1
MISC
GPIO
Controller Link
R345
1PM_BMBUSY#
8.2K_0402_5%
G16
A13
E17
C17
B18
Direct Media Interface
R336
2 @
LINKALERT#
ME__EC_CLK1
ME__EC_DATA1
PCI - Express
R410
2 OCP#
10K_0402_5%
U34C
R355
R344
8.2K_0402_5%
2.2K_0402_5%
+3VS
R579
2.2K_0402_5%
R543
SATA_CLKREQ#
2
10K_0402_5%
R371
10K_0402_5%
EC_THERM#
2
8.2K_0402_5%
@ 1
R519
D
R361
10K_0402_5%
GPIO38
2
10K_0402_5%
R352
R378
2 PCI_CLKRUN#
8.2K_0402_5%
R461
Place closely pin B2
+3VALW
2 SERIRQ
10K_0402_5%
R406
+3VS
Title

ICH9M(3/4)-USB,GPIO,PCIE

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
28
of
53
+VCCP
U34F
D21
1
100_0402_5%
ICH_V5REF_RUN
20 mils
+5VALW +3VALW
R582
2
C
R309
40 mils
+1.5VS
10U_0805_10V4Z
0_0805_5%
+
C455
220U_D2_4VM
C445
C446
C447
10U_0805_10V4Z
2
2.2U_0603_6.3V4Z
VCC3_3[01]
VCC3_3[02]
VCC3_3[07]
AG29
AJ6
AC10
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
AD19
AF20
AG24
AC20
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
B9
F9
G3
G6
J2
J7
K7
C542
1U_0603_10V4Z
+1.5VS
C492
+1.5VS
C528
1U_0603_10V4Z
VCCHDA
AJ4
AJ3
VCCSUS1_05[1]
VCCSUS1_05[2]
AC8
F17
C493
0.1U_0402_16V4Z
2
T100
T99
+3VS
VCC_LAN1_05_INT_ICH_1
VCC_LAN1_05_INT_ICH_2
close to AC7
CHB1608U301_0603 2.2U_0603_6.3V4Z
1
2
R282
1
1
+1.5VS
C431
(10UF*1, 2.2UF*1)
+1.5VS
R281
1
2
CHB1608U301_0603
C434
2
2
10U_0805_10V4Z
4.7U_0805_10V4Z
AC9
VCC1_5_A[17]
AC18
AC19
VCC1_5_A[18]
VCC1_5_A[19]
AC21
VCC1_5_A[20]
G10
G9
VCC1_5_A[21]
VCC1_5_A[22]
AC12
AC13
AC14
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
AJ5
VCCUSBPLL
AA7
AB6
AB7
AC6
AC7
VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]
A10
A11
VCCLAN1_05[1]
VCCLAN1_05[2]
A12
B12
VCCLAN3_3[1]
VCCLAN3_3[2]
A27
VCCGLANPLL
D28
D29
E26
E27
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
A26
+3VS
VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]
VCCGLAN3_3
ICH9-M ES_FCBGA676
C430
2
[email protected]
5
+VCCP
+3VS
(SATA)
C549
0.1U_0402_16V4Z
1
C545
0.1U_0402_16V4Z
+3VS
1
C532
0.1U_0402_16V4Z
C519
0.1U_0402_16V4Z
+1.5VS
R612
0_0402_5%
GM@
R613
PM@
0_0402_5%
1
0.1U_0402_16V4Z
C552
T82
T79
AD8 VCCSUS1_5_ICH_1
F18
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
A18
D16
D17
E22
VCCSUS3_3[05]
AF1
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
0.1U_0402_16V4Z
C534
check HDMI
2
+3VALW
R615
VCCSUS1_5_ICH_2
GM@ R715
1
2
R615
549_0402_1%
@
0_0402_5%
PM@
0_0402_5%
R614
453_0402_1%
@
+3VALW
0.1U_0402_16V4Z
1
C551
2
C546
0.1U_0402_16V4Z
+3VALW
C560
4.7U_0603_6.3V6K
G22 VCCCL1_05_ICH
G23
T75
1
A24
B24
+3VS
VCCSUS1_5[2]
VCCCL3_3[1]
VCCCL3_3[2]
(DMI)
C433
0.1U_0402_16V4Z
C486
0.1U_0402_16V4Z
VCCSUS1_5[1]
VCCCL1_05
VCCCL1_5
+3VS
+3VS
GLAN POWER
C529
0.1U_0402_16V4Z
10U_0805_10V4Z
VCCSUSHDA
USB CORE
+1.5VS
C510
0.1U_0402_16V4Z
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
+1.5VS
1
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
ATX
1U_0603_10V4Z
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
VCCPSUS
+1.5VS
VCCPUSB
+VCCP
VCCSATAPLL
ARX
C710
10U_0805_10V4Z
C712
CHB1608U301_0603
AJ19
1U_0603_10V4Z
10U_0805_6.3V6M
C504
R518
1
+1.5VS
C466
C738
1U_0603_10V4Z
AB23
AC23
C429
C484
V_CPU_IO[1]
V_CPU_IO[2]
0.1U_0402_16V4Z
20 mils
W23
Y23
C426
C502
ICH_V5REF_SUS
VCC_DMI[1]
VCC_DMI[2]
R280
1
2
+1.5VS
CHB1608U301_0603
0.01U_0402_16V7K
0.1U_0402_16V4Z
100_0402_5%
VCCDMIPLL
R29
0.1U_0402_16V4Z
4.7U_0603_6.3V6M
D22
VCCA3GP
C728
1U_0603_10V4Z
C515
0.1U_0402_16V4Z
2
2
R558
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]
1
C521
V5REF_SUS
+3VS
C498
@ 1U_0603_10V4Z
Compal Secret Data
2007/10/15
Issued Date
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
ICH9-M ES_FCBGA676
2008/10/15
Deciphered Date
4
AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29
+3VS
AE1
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25
+5VS
ICH_V5REF_SUS
A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
V5REF
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
C460
0.1U_0402_16V4Z
U34E
VCCRTC
CORE
C459
0.1U_0402_16V4Z
A6
VCCP_CORE
A23
ICH_V5REF_RUN
PCI
20 mils
+RTCVCC
Title

ICH9M(4/4)-POWER&GND

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
29
of
53
AUDIO CODEC
CODEC POWER
0308_Change R294 and R295 from 0 ohm to bead, C363 from 10uF to 680pF, C365 and C368 from 0.1uF to 680p
For Layout:
Place decoupling caps near the power pins of
SmartAMC device.
<35,40,41,42,46,48,49,50>
DIBP_HS
DIBN_HS
R387
R394
2
2
2
2
2 0_0402_5% DIBP_C
2 0_0402_5% DIBN_C
1
1
43
42
PC_BEEP
1
R369 1
R359
2
2 10K_0402_5%
10K_0402_5%
<35>
MICBIASB
PORTB_L
PORTB_R
19
14
15
MICBIASC
PORTC_L
PORTC_R
18
16
17
HP_L
HP_R
MIC_EXTL
MIC_EXTR
MIC_C_BIAS
C496 1
C505 1
<41>
<41>
2 2.2U_0603_16V6K
2 2.2U_0603_16V6K
S/PDIF
GPIO2
GPIO1
EAPD/GPIO0
PORTD_L
PORTD_R
27
28
MIC_L
MIC_R
20
21
MONO
STEREO_L
STEREO_R
29
30
31
MIC_INL
MIC_INR
C516 1
C525 1
BP
GND
SHDN#
C555
0.1U_0402_16V4Z
@
C562
1
4.7U_0805_10V4Z
@
R656
1
2
R701 2
R702
1
100_0402_5%
1
100_0402_5%
EXT_MIC_L <41>
EXT_MIC_R <41>external
MIC
2
48
2
R588
C783
34
35
OUT
1
APE8805A-33Y5P_SOT23-5
@
C558
0.1U_0402_16V4Z
2
@
2
R380
1
R385
C541
10U_0805_10V4Z
26
40
36
DIB_P
DIB_N
PC_BEEP
45
46
47
EAPD
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
12
PC_BEEP dB control
0.1U_0402_16V4Z
C536
33_0402_5% 6
33_0402_5%10
33_0402_5% 8
33_0402_5% 5
PORTA_L
PORTA_R
1
2.2K_0402_5%
1
1
1
1
RESET#
MIC_C_BIAS
1
2.2K_0402_5%
R659
R667
R323
R668
HDA_BITCLK_CODEC
HDA_SYNC_CODEC
HDA_SDIN2
HDA_SDOUT_CODEC
CX20548
AMOM DAA
1
2
R610 GM@ 0_0402_5%
R666 1
2 33_0402_5%11
VIN
SUSP#
+3VAMP_CODEC
+VDDA_CODEC
U21
2
4.7K_0402_5%
+1.5VS
HDA_RST_CODEC#
AVDD_26
AVDD_40
AVEE
9
4
3
44
U15
1
R723
3.9K_0603_1%
<8,16,27>
@
<8,16,27>
<8,16,27>
<27>
<8,16,27>
PM@
VDD_IO
DVDD_1-8
DVDD_3-3
DVDD_44
0_0603_5%
10U_0805_10V4Z
C481
0.1U_0402_16V4Z
C477
1
R611
4.7K_0603_5%
@
+5VALW
1
2
1
C571 0.1U_0402_16V4Z
2
2.2kohm for MICL + MICR

4.7kohm for MICL or MICR
R611
+3VDD_CODEC
R424
2
1
+VDDA_CODEC
MBV2012301YZF_0805
@
(3.33V)
250mW
2
R405
W=40Mil
+3VS
1
4.7K_0402_5%
C540
1U_0603_10V4Z
C537
0.1U_0402_16V4Z
C512
680P_0402_50V7K
@ C479
0.1U_0402_16V4Z
+3VAMP_CODEC
C491
0.1U_0402_16V4Z
+3VALW
C497
680P_0402_50V7K
R333
1
2
MBV2012301YZF_0805
R722
1
2
MBV2012301YZF_0805
@
+3VS
C475
1U_0603_10V4Z
C478
680P_0402_50V7K
+3VDD_CODEC
R395
2
1
MBV2012301YZF_0805
1
2
C524
4.7U_0805_10V4Z
1K_0402_5%
In order for the modem wake on ring feature to function,

the CODEC must be powered by a rail that is not
removed when the system is in standby.
10U_0805_10V4Z
2 2.2U_0603_16V6K
2 2.2U_0603_16V6K
INT_MICL <31>
INT_MICR
Internal MIC / Array MIC

Internal WOOFER
@
LINE_OUTL <31>
LINE_OUTR <31>
Internal SPKR.
+3VAMP_CODEC
SENSEA
13
SENSE
VREF
24
VC_REFA
FLY_P
FLY_N
39
37
VREF_LO
VREF_HI
RESERVED_32
RESERVED_33
22
23
32
33
CX20561-12Z_LQFP48_7X7
10U_0805_10V4Z
C548
2
1U_0603_10V4Z
C535
VREF_HI
VREF_LO
1
C533
1
R392
2
5.1K_0402_1%
1
R391
2
5.1K_0402_1%
1
R386
2
20K_0402_5%
Port A
JACK_PLUG_HP <41>
JACK_PLUG_MIC <41>
port
port
port
port
A
B
C
D
:
:
:
:
5.11K
10.0K
20.0K
39.2K
Port C
ohm
ohm
ohm
ohm
0216_Change value.
ANALOG
R347
10K_0402_1%
2
C553
1
2
0.1U_0402_16V4Z
1U_0603_10V4Z
2
@ 0.1U_0402_16V4Z
2
B
560_0402_5%
1U_0603_10V4Z
Q28
2SC2411KT146_SOT23-3
R317
2
1
1 1
560_0402_5%
1U_0603_10V4Z
GNDA
[email protected]
A
TIP_1
2007/10/15
2008/10/15
Deciphered Date
B
Compal Secret Data
Issued Date
Place these C and R around AGND and DGND,

then choose the one which is close to Codec
to populate
RING_1
D10 @
RB751V_SOD323
R313
10K_0402_5%
2
GND
GND1
GND2
ME@
R353
20K_0402_5%
<28> SB_SPKR
1
2
R318
1 1
C443
2
0_0402_5%
3
4
FOX_JM74613-P2002-7F
2
0_0402_5%
R454
1
1
2
330P 3KV J NPO 1808 X2Y3

C798
2
0_0402_5%
PC_BEEP
JRJ11
RING_1
TIP_1
C456
2
BEEP#
2PC_BEEP1
R354 20K_0402_5%
<35>
C452
R446
1
4
C485 1U_0603_10V4Z
2
1
C797
330P 3KV J NPO 1808 X2Y3
R443
1
CX20548
AMOM DAA
R346
10K_0402_1%
C490
1
2
0.1U_0402_16V4Z
C480
1
2
0.1U_0402_16V4Z
1C465
C565
1
2
0.1U_0402_16V4Z
DIGITAL
+3VS
AVSS_25
AVSS_38
C458
33P_0402_50V8K
7
41
25
38
DVSS_7
DVSS_41
R327
47_0402_5%
For Vista
0.1U_0402_16V4Z
DMIC_CLOCK
DMIC_1/2
C517
1U_0603_10V4Z
1
2
C526
1U_0603_10V4Z
HDA_BITCLK_CODEC
Title

CX20561-AMOM Codec

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet
E
30
of
53
+5VAMP
+5VS
L27
C689
0.1U_0402_16V4Z
Speaker Amplifier
FBMA-L11-160808-700LMT_0603
C686
10U_0805_10V4Z
1nd = APA2031 (SA00001RZ00)

2nd = G1431F2U (SA000012Y00)
+5VAMP
R401
100K_0402_1%
20mil
R413
R412
R435
R436
1
1
1
1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2
2
2
2
SPK_L1+
SPK_L1SPK_R1+
SPK_R1-
+3VALW
LINE_OUTR
R409 0_0402_5%
1
2
R455 1
2
0_0402_5%
C570
R451
12
19
LIN-
ROUT+
18
17
RIN-
LIN+
GND
GND
GND
GND
GND
BYPASS
1
11
13
20
21
10
GAIN1
7
2
C507
0.1U_0603_25V7K
VDD
NC
PVDD SHUTDOWN#
PVDD
LOUTGAIN0
ROUTGAIN1
LOUT+
GAIN0
0.1U_0603_25V7K
LIN
2
0.1U_0603_25V7K
RIN
2
2
C506
RIN+
U18
16
6
15
0.1U_0603_25V7K
C550
10K_0402_5%
10K_0402_5%
R417
<30>
C569
4.7U_0805_10V4Z
LINE_OUTL
<30>
R414
0_0402_5%
@
INT MIC
R439
10K_0402_5%
@
C527
0.1U_0402_16V4Z
2
ME@
@C557
@
C557 22P_0402_50V8J
W=40mil
1
4
3
2
1
ACES_85204-0400N
Speaker Conn.
GAIN1
R398
100K_0402_1%
@
+5VAMP
4
3
2
1
@C556
@
C556 22P_0402_50V8J
R400
100K_0402_1%
SPKL+O
SPKL-O
SPKR+O
SPKR-O
6dB
10dB
15.6dB
21.6dB
@C543
@
C543 22P_0402_50V8J
GAIN0
GAIN1
0
1
0
1
@C544
@
C544 22P_0402_50V8J
2 1
R397
100K_0402_1%
2 1
JP10
GAIN0
0
0
1
1
+5VAMP
AMP_OFF#
R441 1
2 EC_MUTE#
0_0402_5%
SPKL-O
14
SPKR-O
SPKL+O
SPKR+O
EC_MUTE# <35>
JMIC2
20mil
1
2
1
2
GND
GND
3
4
INT_MICL
INT_MICL <30>
GNDA
MOLEX_53780-0270
C742
47P_0402_50V8J
2
GNDA
ME@
APA2031RI-TRL_TSSOP20
D30
C523
4.7U_0805_10V4Z
INT_MICL
2
1
3
PJMBZ6V8_SOT23-3
Compal Secret Data
2007/10/15
Issued Date
[email protected]
A
2008/10/15
Deciphered Date
B
Title

AMP/VR/Audio Jack/MIC

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet

E
31
of
53
Mini-Express Card for 3G Or TV Tuner

Mini-Express Card for WLAN
+5VS
+1.5VS
1 2
+3VS
C734
4.7U_0805_10V4Z
C704
0.1U_0402_16V4Z
C729
4.7U_0805_10V4Z
1
C732
0.1U_0402_16V4Z
C709
2
WLAN@
WLAN@
WLAN@
0.1U_0402_16V4Z
<35>
BT_OFF#
IN
WLAN@
BT MODULE CONN
Q17
Q18
+3VS
+3VS_BT
D
WLAN@
C725 WLAN@
0.1U_0402_16V4Z
R246
10K_0402_1%
BT@
OUT
+3VALW
1
GND
BT@
G
BT_LED#
<38>
SRC9
<22> CLK_PCIE_WLAN#
<22> CLK_PCIE_WLAN
<28> PCIE_RXN3
<28> PCIE_RXP3
<28> PCIE_TXN3
<28> PCIE_TXP3
+3VS
+3VALW
R711
R712
WLAN@
1
2
0_0402_5%
@ 2
1
0_0402_5%
R710
WLAN@
R713
WLAN@
1
0_0402_5%
1
0_0402_5%
53
GND1
R708
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
FOX_AS0B226-S56N-7F
ME@
2
0_0402_5%
WLAN@
2
1
J3
JOPEN
R709
R596 1 @
0_0402_5%
+3VALW
<28>
<28>
+3VS
+1.5VS
2Watt
Q16
BT@
3G_OFF#
IN
WLAN@ 0_0402_5%
WL_OFF#
R592 1
2
WL_OFF# <35>
PLT_RST# <8,16,26,33,36,40>
1
2 @
+3VALW
R552 1
2 0_0402_5% +3VS
R555
@ 0_0402_5%
R537 1 @
0_0402_5%
2
ICH_SMBCLK <22,28,40>
R534 1 @
0_0402_5%
2
ICH_SMBDATA <22,28,40>
USB20_N6
USB20_P6
2
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
JP7
OUT
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
0_0402_5%
CR#_G
0_0402_5%
0_0402_5%
GND
<22> WLAN_CLKREQ#
2
2
1 @
JP22
ICH_PCIE_WAKE#
BT_ACTIVE
@ R569 1
WLAN_ACTIVE
@ R565 1
WLAN_CLKREQ#
2
1
C409
0.1U_0402_16V4Z
BT@
Mini-Express Card(Slot 1-WLAN)
BT@
1
2
3
4
5
6
7
8
9
10
USB20_N6
USB20_P6
BTON_LED
BT_ACTIVE
WLAN_ACTIVE
R245
10K_0402_5%
@
1
2
3
4
5
6
7
8
GND1
GND2
MOLEX_53780-0870
ME@
USB20_N8 <28>
USB20_P8 <28>
(WWAN_LED#)
1
R525
2
0_0402_5%
WLAN_LED# <38>
WLAN@
@ R523
1
+5VS
100K_0402_5%
2005/09/27 modified.
Base on OPTION GTM351E Datasheet Rev0.1
Vcc 3.3V +/- 8%
Peak Icc 2750mA
with max supply droop 50mA
Average Icc 1000mA
Compal Secret Data
Issued Date
2007/10/15
2008/10/15
Deciphered Date
A
[email protected]
Title

Mini-Card/3G/FeliCa/BT
Size
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Date:
Sheet
Tuesday, May 20, 2008

E
32
of
53
L3
@
FBM-L11-321611-260-LMT_1206
1
2
Layout Notice : Place as close

chip as possible.
Layout Notice : 1.2V filter. Place as close

chip as possible.
+3V_LAN
+2.5V_LAN
C74
0.01U_0402_16V7K
<35>
EN_WOL 2
Q8 G
2N7002_SOT23
EN_WOL
<22> CLK_PCIE_LAN#
28
PCIE_REFCLK_N
<22> CLK_PCIE_LAN
29
PCIE_REFCLK_P
<22> CLKREQ_LAN#
11
CLKREQ
+3VS
(CLKREQ#) and (ENERGY_DET) are

only supported in BCM5787M
C75
0.1U_0402_16V4Z
R35
+3VS
R52
+3V_LAN
R49
1
1
1
2
@ 0_0402_5%
2
1K_0402_5%
2
1K_0402_5%
53
VMAIN_PRSNT
54
VAUX_PRSNT
2
@ 0_0402_5%
59
ENERGY_DET
35
GPHY_PLLVDD
32
PCIE_RXD_N
41
40
42
43
48
47
49
50
TRD0_N
TRD0_P
TRD1_N
TRD1_P
TRD2_N
TRD2_P
TRD3_N
TRD3_P
LAN_TX0LAN_TX0+
LAN_RX1LAN_RX1+
LAN_TX0- <34>
LAN_TX0+ <34>
LAN_RX1- <34>
LAN_RX1+ <34>
T20
T18
T21
T19
+3V_LAN
LOW PWR
2 R36
1 R37
67 R38
66
LINKLED
SPD100LED
SPD1000LED
TRAFFICLED
0_0402_5%
2
0_0402_5%
2
2 @ 0_0402_5%
1
1
1
C53
LINKLED# <34>
ACTIVITY# <34>
2 0.1U_0402_16V4Z
C73
1U_0603_10V4Z
0.1U_0402_16V4Z
+1.2V_LAN
+AVDDL
U1
0.1U_0402_16V4Z
2
1
L30 FBM-L11-160808-601LMT_0603
1
2
C81
1U_0603_10V4Z
C45
0.1U_0402_16V4Z
C65
0.1U_0402_16V4Z
C58
0.1U_0402_16V4Z
C34
+LAN_BIASVDD
1
C71
2
C46
0.1U_0402_16V4Z
C68
C76
0.047U_0402_16V4Z
1
1
0.047U_0402_16V4Z
+LAN_AVDD
2
C77
4.7U_0805_10V4Z
L7
2
1
FBM-L11-160808-601LMT_06032
C55
0.1U_0402_16V4Z
C32
10U_0805_10V4Z
2
G
R25
33K_0402_5%
21.5
L8
2
1
FBM-L11-160808-601LMT_0603
AO3414_SOT23-3
+1.2V_LAN
3 Q7
+5VALW
1
C56
0.1U_0402_16V4Z
+3VALW
+XTALVDD
C62
0.1U_0402_16V4Z
L4
2
1
FBM-L11-160808-601LMT_06032
C49
0.1U_0402_16V4Z
Layout Notice : Filter place as close

chip as possible.
C67
0.1U_0402_16V4Z
MMJT9435T1G_SOT223
2
1
L31 FBM-L11-160808-601LMT_0603
2
2
C64
4.7U_0805_10V4Z
L5
2
1
FBM-L11-160808-601LMT_0603
1
2
C69
1U_0603_10V4Z
+GPHY_PLLVDD
C70
0.1U_0402_16V4Z
<28> PCIE_TXN6
31
PCIE_RXD_P
PCIE_MRX_C_LTX_N6
25
PCIE_TXD_N
PCIE_MRX_C_LTX_P6
26
PCIE_TXD_P
10
PERST
12
WAKE
58
SMB_CLK
57
SMB_DATA
<28> PCIE_TXP6
<28> PCIE_RXN6
0.1U_0402_16V7K
<28> PCIE_RXP6
0.1U_0402_16V7K
+PCIE_PLLVDD
C57
C59
<8,16,26,32,36,40> PLT_RST#
@ 1
R31
+PCIE_VDD
C60
0.1U_0402_16V4Z
+3V_LAN
+3V_LAN
1
R33
1
R32
Layout Notice : Place as close

chip as possible.
2
@ 4.7K_0402_5%
2
@ 4.7K_0402_5%
+3V_LAN
2
0_0402_5%
1
R42
1
R44
2
@ 47K_0402_5%
2
@ 47K_0402_5%
1
R34
LAN_WP
2
0_0402_5%
GPIO2
1
R41
2
@ 0_0402_5%
14
18
37
XTALVDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
23
6
15
19
56
61
+XTALVDD
VDDP
VDDP
17
68
+2.5V_LAN
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
5
13
20
34
55
60
+1.2V_LAN
BIASVDD
PCIE_PLLVDD
PCIE_VDD
PCIE_VDD
36
30
27
33
AVDD
AVDD
AVDD
38
45
52
+LAN_AVDD
AVDDL
AVDDL
AVDDL
AVDDL
39
44
46
51
+AVDDL
GPIO_0(SERIAL_DO)
GPIO_1(SERIAL_DI)
GPIO_2
UART_MODE
XTALI
Y1
1
2
25MHZ_20P
21
XTALI
XTALO
22
XTALO
16
REG_GND
24
PCIE_GND
GND
XTALO
XTALI
1
R56
C61
10U_0805_10V4Z
+3V_LAN
+3V_LAN
Q9
MBT35200MT1G_TSOP6
CTL25
+LAN_BIASVDD
+PCIE_PLLVDD
+PCIE_VDD
+2.5V_LAN
Notice : 4.7u 6.3V capactor Thickness 1.25mm

Layout Notice : Filter place as close
chip as possible.
69
200_0402_1%
1
C43
27P_0402_50V8J
C42
27P_0402_50V8J
0.1U_0402_16V4Z
C44
C52
0.1U_0402_16V4Z
C54
10U_0805_10V4Z
R39
+1.2V_LAN
Q6
CTL12
CTL25
2
1K_0402_5%
REGCTL12
REGCTL25
RDAC
+2.5V_LAN
C63
0.1U_0402_16V4Z
<35> LAN_WAKE#
CTL12
+GPHY_PLLVDD
LAN_CLK
SI
LAN_DATA
CS#
65
63
64
62
SCLK(EECLK)
SI
SO(EEDATA)
CS
1
2
5
6
C72
4.7U_0805_10V4Z
2
4
L6
C
2
1
FBM-L11-160808-601LMT_0603
2
2
R40
<26> PCI_CBE#3
+3V_LAN
R27
4.7K_0402_5%
2
R28
4.7K_0402_5%
C38
0.1U_0402_16V4Z
U2
8
7
6
5
LAN_WP
LAN_CLK
LAN_DATA
VCC
WP
SCL
SDA
A0
A1
NC
GND
1
2
3
4
AT24C02_SO8
A
LAN_CLK
[email protected]
5
4.7K_0402_5%
Compal Secret Data
Issued Date
1
R30
2007/10/15
2008/10/15
Deciphered Date
4
Title

BCM5787MKML

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
33
of
53
+2.5V_LAN
RJ45 CONN
EMI request
R67
2 0.1U_0402_16V4Z
R476
0_0402_5%
C607 1
2 0.1U_0402_16V4Z
C601 1
<33>
<33>
LAN_RX1+
LAN_RX1-
TCT
2 0.1U_0402_16V4Z
<33>
<33>
TCT
LAN_TX0+
LAN_TX0-
LAN_TX0+
LAN_TX0-
1
2
3
4
5
6
7
8
RD+
RDCT
NC
NC
CT
TD+
TD-
RX+
RXCT
NC
NC
CT
TX+
TX-
16
15
14
13
12
11
10
9
MDO1+
MDO1MCT0
MCT1
MDO0+
MDO0-
R72
R76
75_0402_5%
RJ45_PR
SHLD4
16
PR4-
SHLD3
15
PR4+
PR2-
PR3-
PR3+
MDO1+
PR2+
MDO0-
PR1-
MDO0+
330_0402_5%
1
SHLD2
14
PR1+
SHLD1
13
MDO1-
75_0402_5%
350uH_NS0013LF
R92
<33>
1
C88
220P_0402_25V8J
1
49.9_0402_1%
1
49.9_0402_1%
+3V_LAN
Change C468,C470,C473,C474,C475,C476 from 0.01uF to 0.1uF
LAN_RX1- 2
R475
LAN_RX1+ 2
R472
LINKLED#
Amber LED-
11
Amber LED+
220P_0402_25V8J
C80
JRJ45
12
+3V_LAN
U25
LAN_RX1+
LAN_RX1-
330_0402_5%
1
10
Green LED-
Green LED+
FOX_JM36113-P2221-7F
ME@
C600
1
2 0.1U_0402_16V4Z
RJ45_PR
1
2
C85
1000P_1206_2KV7K
1
49.9_0402_1%
1
49.9_0402_1%
R669
0_0402_5%
C610
1
2 0.1U_0402_16V4Z
LAN_TX0- 2
R478
LAN_TX0+ 2
R477
<33> ACTIVITY#
C602 1
near LAN controller
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
2008/10/15
Deciphered Date
4
Title

LAN CONTROLLER

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
34
of
53
+3VALW
+3VALW
+3VALW
PCI_PME#
+3VALW
FAN_SPEED1
EC_TX_P80_DATA
EC_RX_P80_CLK
<14,15,37> EC_TX_P80_DATA
<14,15,37> EC_RX_P80_CLK
<41>
ON/OFF#
@ Q31
2N7002_SOT23
<38> NUM_LED#
XCLKI
XCLKO
FRD#SPI_SO
2
100K_0402_1%
FSEL#SPICS#
2
100K_0402_1%
1
@ R292
KSO17
2
10K_0402_5%
AVCC
83
84
85
86
87
88
TP_CLK
TP_DATA
TP_LED# <38>
TP_CLK <37>
TP_DATA <37>
IN
4
OUT
R325 1
<33>
UMA_DIS
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
100
101
102
103
104
105
106
107
108
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
V18R
124
XCLK1
XCLK0
EC_LID_OUT#
EC_ON
MODULE_ID
ICH_POK_EC
BKOFF#
EC_THERM#
SUSP#
PBTN_OUT#
R583
10K_0402_5%
[email protected]
+3VALW
+3VALW
+3VALW
GM@ R330
10K_0402_1%
MODULE_ID
Vab
EC_RSMRST# <28>
EC_LID_OUT# <28>
EC_ON
<41,46>
D12
RB751V_SOD323
ICH_POK
1
2
ICH_POK <8,28>
BKOFF# <24>
1
2
1
2
+3VS
WL_OFF# <32>
R340 0_0402_5% R339 10K_0402_5%
@
SCROLL_LED# <38>
R308
100K_0402_1%
Vab
@
R342
10K_0402_1%
I2C_INTE
R616
10K_0402_5%
R341
0_0402_5%
UMA_DIS
BRD_ID
1
R321
C442
@ 100K_0402_1%
PM@ R329
0_0402_5%
UMA_DIS
SLP_S4# <28>
ENBKL
<24>
EAPD
<30>
EC_THERM# <28>
SUSP# <30,40,41,42,46,48,49,50>
PBTN_OUT# <28>
Vab
UMA
VGA
no used at B-test
C511
4.7U_0805_10V4Z
ENE
suggesttion
at C0
revision
Module ID
J
I
T
R
1
R
2
J
I
W
A
1
A
2
J
I
W
A
3
A
4
NC
NC
1
Analog Board ID definition,

Please see page 3.
SYSON
ACIN
I2C_INT <41>
FSTCHG <46>
CHARGE_LED0# <38>
CAPS_LED# <38>
CHARGE_LED1# <38>
PWR_LED# <38>
SYSON
<40,42,48>
VR_ON
<51>
ACIN
<28,44>
+3VS
CHARGE_LED0#
CAPS_LED#
CHARGE_LED1#
<38>
<38>
<38>
<38>
I2C_INTE
FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#
C501
15P_0402_50V8J
C415
X1
@ 100P_0402_50V8J
2
4.7K_0402_5%
2
4.7K_0402_5%
ID
0
1
2
3
4
5
6
7
BRD ID
R54/42(Rb) Vab
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
0
8.2K
18K
33K
56K
100K
200K
NC
R537/541(Ra)=100K Ohm
0V
0.25V
0.50V
0.82V
1.19V
1.65V
2.20V
3.30V
EC_SMB_CK2
2
4.7K_0402_5%
EC_SMB_DA2
2
4.7K_0402_5%
C416
1
R299
TP_DATA
1
R298
KB925 SPI STRAP PIN

unpoped for C0 version
11/16
+3VS
1
R258
1
R259
+5VS
TP_CLK
CMOS_OFF# <40>
+3VALW
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
GPI
2 4.7K_0402_5%
EN_WOL
SPI Device Interface
SM Bus
+3VALW
EC_MUTE# 1
2
R300
@ 10K_0402_5%
USB_ON
2
1
10K_0402_5%
R291
97
98
99
109
R273
100K_0402_1%
<8>
2
1
2
C514
15P_0402_50V8J
TSATN#
DAC_BRIG <24>
EN_FAN1 <5>
IREF
<46>
BT_OFF# <32>
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
SPI Flash ROM
C746 1
for G sensor
EC_MUTE# <31>
USB_ON <43>
XCLKO 1 R393
2 XCLKI
@ 20M_0603_5%
EC_SMB_CK1
2
6.8K_0402_5%
EC_SMB_DA1
2
6.8K_0402_5%
2
0_0603_5%
USB_ON
+5VALW
1
R294
1
R293
100P_0402_50V8J
GPIO
KB926QFA1_LQFP128
ACIN
BATT_TEMPA <45>
BATT_OVP <46>
ADP_I
<46>
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
100P_0402_50V8J
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
ECAGND
1
@ R379
1
@ R399
122
123
DAC_BRIG
EN_FAN1
IREF
PS2 Interface
GND
GND
GND
GND
GND
+3VALW
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
68
70
71
72
0.1U_0402_16V4Z
<43> KILL_SW#
<5> FAN_SPEED1
<26>
EC_PME#
2
0_0402_5%
EC_SMI#
LID_SW#
ESB_CK
ESB_DA
67
9
22
33
96
111
125
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
11
24
35
94
113
1
@R422
@
R422
<28> SLP_S3#
<28> SLP_S5#
<28> EC_SMI#
<41> LID_SW#
<41> ESB_CK
<41> ESB_DA
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
BRD_ID
TSATN#_EC@ 1
R382
BATT_TEMP
C745 1
2
0_0402_5%
BATT_TEMP
BATT_OVP
100P_0402_50V8J
1
1
R421
63
64
65
66
75
76
DA Output
R404
10K_0402_5%
<33> LAN_WAKE#
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
AD
ACOFF
BATT_OVP C744 1
1
2
PWM Output
1
2
3
4
AT24C16AN-10SU-2.7_SO8
INVT_PWM <24>
BEEP#
<30>
NOVO#
<41>
ACOFF
<44,46>
KSI0
<37>
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
A0
A1
A2
GND
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
2
2
C790
0.1U_0402_16V4Z
@
EC_RST#
EC_SCI#
12
13
37
20
38
R609
4.7K_0402_5%
@
<22> CLK_PCI_LPC
<26,37> PCI_RST#
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
KSI0
55
KSI1
56
KSI2
57
KSI3
58
<37>
KSI3
KSI4
59
<37>
KSI4
KSI5
60
KSI6
61
KSO[0..15]
KSI7
62
<37>
KSO[0..15]
R717
KSO0
39
KSI[0..7]
KSO1
40
100_0402_5%
<37>
KSI[0..7]
KSO2
ENE@
41
EC_SMB_CK1
KSO3
42
KSO4
43
ESB_CK
EC_SMB_DA1
KSO5
44
KSO6
45
ESB_DA
KSO7
46
R718
R719
KSO8
47
KSO9
4.7K_0402_5%
48
4.7K_0402_5%
KSO10
@
@
49
KSO11
50
KSO12
R608
51
KSO13
52
4.7K_0402_5%
2
2
KSO14
@
53
<37>
KSO14
C793
C794
KSO15
54
<37>
KSO15
KSO16
0.1U_0402_16V4Z
0.1U_0402_16V4Z
81
1
1 @
KSO17
@
82
L47 MBC1608121YZF_0603
2
L48 MBC1608121YZF_0603
C791
EC_SMB_CK1 1
2
77
<45> EC_SMB_CK1
+3VALW
EC_SMB_DA1 1
0.1U_0402_16V4Z
78
2
<45> EC_SMB_DA1
1 @
EC_SMB_CK2
79
<5,16,41> EC_SMB_CK2
EC_SMB_DA2
80
<5,16,41> EC_SMB_DA2
R716
100_0402_5%
ENE@
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
<28>
EC_SCI#
PWR_LED_SC#
+3VS
KB_RST#_EC
INVT_PWM
BEEP#
VCC
WP
SCL
SDA
1
@R40310_0402_5%
@
R40310_0402_5%
2
47K_0402_5%
C509
0.1U_0402_16V4Z
GATEA20
8
7
6
5
EC_SMB_CK1
EC_SMB_DA1
21
23
26
27
1
R388
<27>
<28,37> SERIRQ
<27,37> LPC_FRAME#
RB751V_SOD323
<27,37> LPC_AD3
<27,37> LPC_AD2
<27,37> LPC_AD1
<27,37> LPC_AD0
2
1
2
@C538
@
C538 22P_0402_50V8J
+3VALW
U12
KB_RST#
1
2
3
4
5
7
8
10
R265
100K_0402_1%
AGND
<27>
U17
C418
2 0.1U_0402_16V4Z
1
2
69
D23
VCC
VCC
VCC
VCC
VCC
VCC
C487
1000P_0402_50V7K
C448
1000P_0402_50V7K
C520
0.1U_0402_16V4Z
C530
0.1U_0402_16V4Z
C531
0.1U_0402_16V4Z
L23 1
2
+EC_AVCC
FBM-11-160808-601-T_0603
2
1
C432
C437
0.1U_0402_16V4Z
1000P_0402_50V7K
1 ECAGND 2
1
2
L24
FBM-11-160808-601-T_0603
C513
0.1U_0402_16V4Z
+3VALW
+EC_AVCC
1
@ 100P_0402_50V8J
32.768KHZ_12.5P_1TJS125BJ2A251
Compal Secret Data
Issued Date
2007/10/15
Deciphered Date
2008/10/15
Title

BIOS & EC I/O Port

Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Tuesday, May 20, 2008
Sheet
35
of
53
+3VS
+3VS_CARD
CARD@
+1.8VS
+3VS_CARD
+1.8VS_CARD
R642
R670 2
2
1
0_0603_5%
@
0_0805_5%
+3VS_CARD
+CR1_POWER
+CR1_POWER
1 R626
@
<22> CLK_PCIE_CARD#
<22> CLK_PCIE_CARD
<28> PCIE_TXN1
<28> PCIE_TXP1
C755
@
2 0.1U_0402_16V4Z
<28> PCIE_RXN1
<28> PCIE_RXP1
CLK_PCIE_CARD#
CLK_PCIE_CARD
3
4
APCLKN
APCLKP
PCIE_TXN1
PCIE_TXP1
9
8
APRXN
APRXP
PCIE_RXN1C756
PCIE_RXP1C757
+3VS_CARD
Reserve circuit for new version

not ready & debugging
CARD@
2
1 0.1U_0402_10V7K PCIE_C_RXN1 11
2
1 0.1U_0402_10V7K PCIE_C_RXP1 12
CARD@
R628 2
PREXT
1
7
CARD@ 8.2K_0402_5%
1 R633
2 1K_0402_5%
CARD@
1
T102
38
39
APTXN
APTXP
CARD@
1 R629
2 4.7K_0402_5%
CARD@
1 R630
2 4.7K_0402_5%
<8,16,26,32,33,40>
PLT_RST#
PLT_RST#
CR1_CD0N
PCIES_EN
PCIES
JMB385
T103
T104
CR1_CD1N
CR1_CD0N
Normal
0
CR1_CD0N
CR1_CD1N
XRSTN
XTEST
CR1_CD1N
JMB385 Operation Modes

XTEST
1
2
GND
CR1_PCTLN
T105
13
14
SEEDAT
SEECLK
15
16
CR1_CD1N
CR1_CD0N
17
21
5
10
30
+1.8VS_CARD
DV33
DV33
DV33
DV18
DV18
19
20
44
18
37
+3VS_CARD
MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
48
47
46
45
43
42
41
40
29
28
27
26
25
23
22
NC
NC
NC
34
35
36
APREXT
C762
@
2 0.1U_0402_16V4Z
+3VS_CARD
APVDD
APV18
TAV33
APGND
CR1_PCTLN
GND
GND
GND
GND
CR1_LEDN
+3VS_CARD
+1.8VS_CARD
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
8
9
26
27
28
30
31
32
XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7
MDIO4
MDIO6
MDIO14
XDCD#
MDIO13
MDIO12
MDIO5
MDIO7
@1
@1
@1
@1
@1
@1
@1
@1
R679
R680
R681
R682
R683
R684
R685
R686
2
2
2
2
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
6
7
5
34
1
2
3
4
XD-WE
XD-WP
XD-ALE
XD-CD-SW
XD-R/B
XD-RE
XD-CE
XD-CLE
MDIO5
MDIO4
CR1_CD0N
MDIO6
MS-VCC
MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS
14
15
19
20
18
16
17
21
GROUND
GROUND
37
38
MDIO5
MDIO0
MDIO1
MDIO2
MDIO3
CR1_CD1N
MDIO4
1K_0402_1%1K_0402_1%
R654
R655
@
@
close to
JREAD1.24
XDCD#
1
C
C780
C781
@
@
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
close to
JREAD1.15
C758
270P_0402_50V7K
SD,MMC,MS,XD muti-function pin define
+3VS_CARD
MDIO14
12
36
35
+1.8VS_CARD
MDIO12
SD-CMD
SD-CD-SW
SD-WP-SW
MDIO5
ME@
DAN202UT106_SC70-3
MMC Card
PIN Name
MMC_DAT0
MS Card
PIN Name
MS_DAT0
XD Card
PIN Name
XD_DAT0
SD_DAT1
MMC_DAT1
MS_DAT1
XD_DAT1
SD_DAT2
MMC_DAT2
MS_DAT2
XD_DAT2
SD_DAT3
MMC_DAT3
MS_DAT3
XD_DAT3
MDIO04
SD_CMD
MMC_CMD
MS_BS
XD_WE#
MDIO05
SDCLK1
MMCCLK
MSCCLK
XD_CE#
MDIO06
SD_WP#
MMC_WP#
MDIO03
Close
1 CARD@
0.1U_0402_16V4Z
C760 1
CARD@
2
C761
1000P_0402_50V7K
2
MDIO0
MDIO1
MDIO2
MDIO3
GND
MDIO02
4IN1-GND
24
31
32
33
MDIO01
CARD@
2
C763
0.1U_0402_16V4Z
4IN1-GND
22
MDIO13
13
D24
MDIO6
C759
CARD@
10U_0805_10V4Z
24
25
29
10
11
T-SOL_144-3000000900_NR
MDIO
PIN Name
MDIO00
MDIO7
SD-CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
4 IN 1 CONN
CR1_CD1N 2
CARD@
1 R634
2 10K_0402_1%
CARD@
1 R635
2 200K_0402_1%
CARD@
1 R636
2 200K_0402_1%
2
2
2
2
2
2
2
2
CR1_CD0N
CARD@
CARD@
1 R631
2 10K_0402_5%
CARD@
1 R632
2 10K_0402_5%
R671
R672
R673
R675
R676
R677
R678
R674
MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5_C 1 R705
2 22_0402_5%
MDIO6
CARD@
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
JMB385-LGEZ0A_LQFP48_7X7
+CR1_POWER
@1
@1
@1
@1
@1
@1
@1
@1
Q34
AO3413_SOT23-3
@
MDIO0
MDIO1
MDIO2
MDIO3
MDIO8
MDIO9
MDIO10
MDIO11
23
U39
CR1_PCTLN
CR1_PCTLN 1
SD-VCC
Need check CLK GEN &

SB select pin & page
XD-VCC
1
2
1K_0402_1%
R627
@
2 0_0402_5%
JREAD1
33
SD Card
PIN Name
SD_DAT0
to PIN5
XD_WP#
XD_CLE
MDIO07
MDIO08
MMC_DAT4
MS_DAT4
MDIO09
MMC_DAT5
MS_DAT5
XD_DAT4
XD_DAT5
MDIO10
MMC_DAT6
MS_DAT6
XD_DAT6
MDIO11
MMC_DAT7
MS_DAT7
XD_DAT7
MDIO12
XD_RE#
MDIO13
XD_R/B#
MDIO14
XD_ALE
+CR1_POWER
CARD@
R637 2
+1.8VS_CARD
CR1_POWER
+3VS_CARD
0_0805_5%
CARD@
C764
10U_0805_10V4Z
CARD@
C765
0.1U_0402_16V4Z
C766
0.1U_0402_16V4Z
2
@
C767
0.1U_0402_16V4Z
C768
CARD@
0.1U_0402_16V4Z
1
C769
C782
CARD@
CARD@
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
Cardreader contactor not support MMC & MS

Bit 4~7
Use 0805 type and over

20 mils trace width on
both side
Compal Secret Data
Card Reader power circuit
Issued Date
2007/10/15
Deciphered Date
2006/10/06
5
[email protected]
Title

4 in 1 Card

Custom
JIWA3/A4_LA4212P
Date:
Sheet
1
Rev
1.0
36
of
53
To TP/B Conn.
INT_KBD Conn.
KSI[0..7]
D
KSI[0..7]
EC DEBUG PORT
<35>
D
KSO[0..15]
KSO[0..15] <35>
JP4
+5VS
<35>
<35>
JP6
C396 1
2 @ 100P_0402_50V8J
KSO1 C401 1
2 @ 100P_0402_50V8J
KSO15
C334 1
2 @ 100P_0402_50V8J
KSO7 C398 1
2 @ 100P_0402_50V8J
KSO6
C400 1
2 @ 100P_0402_50V8J
KSI2 C392 1
2 @ 100P_0402_50V8J
KSO8
C399 1
2 @ 100P_0402_50V8J
KSO5 C394 1
2 @ 100P_0402_50V8J
KSO13
C330 1
2 @ 100P_0402_50V8J
KSI3 C393 1
2 @ 100P_0402_50V8J
KSO12
C329 1
2 @ 100P_0402_50V8J
KSO14C331 1
2 @ 100P_0402_50V8J
KSO11
C332 1
2 @ 100P_0402_50V8J
KSI7 C377 1
2 @ 100P_0402_50V8J
KSO10
C333 1
2 @ 100P_0402_50V8J
KSI6 C378 1
2 @ 100P_0402_50V8J
KSO3
C328 1
2 @ 100P_0402_50V8J
KSI5 C381 1
2 @ 100P_0402_50V8J
KSO4
C397 1
2 @ 100P_0402_50V8J
KSI4 C380 1
2 @ 100P_0402_50V8J
KSI0
C395 1
2 @ 100P_0402_50V8J
KSO9 C379 1
2 @ 100P_0402_50V8J
KSO0
C382 1
2 @ 100P_0402_50V8J
KSI1 C376 1
2 @ 100P_0402_50V8J
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TP_CLK
TP_DATA
1
2
3
4
5
6
GND
GND
+3VALW
<14,15,35> EC_TX_P80_DATA
<14,15,35> EC_RX_P80_CLK
EC_TX_P80_DATA
EC_RX_P80_CLK
1
2
3
4
1
2
3
4
ACES_85205-0400
ME@
ACES_85201-06051
ME@
+5VS
TP_DATA C327 1
2 @ 100P_0402_50V8J
TP_CLK
2 @ 100P_0402_50V8J
C245
C326 1
0.1U_0402_16V4Z
TP_CLK
TP_DATA
C
KSO2
JP5
1
2
3
4
5
6
7
8
TP_CLK
TP_DATA
SW/L
SW/R
D31
PJDLC05_SOT23-3
6
5
ACES_85202-2405
SW/L
3
SW3
EVQPLHA15_4P
FOR LPC SIO DEBUG PORT

B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
6
5
JP11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
+5VS
SW/R
+3VS
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
PCI_RST#
CLK_PCI_DB
SERIRQ
CLK_14M_SIO <22>
LPC_AD0 <27,35>
LPC_AD1 <27,35>
LPC_AD2 <27,35>
LPC_AD3 <27,35>
LPC_FRAME# <27,35>
LPC_DRQ0# <27>
PCI_RST# <26,35>
CLK_PCI_DB <22>
SERIRQ
<28,35>
3
SW4
EVQPLHA15_4P
2
R458
1
10K_0402_5%
@
ACES_85201-2005
ME@
Compal Secret Data
2007/10/15
Issued Date
[email protected]
5
Deciphered Date
2008/10/15
4
Title

KB /SW /LPC Debug Conn.
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
1
37
of
53
FOR EC 8M SPI ROM

+3VALW
+3VS
1
C566
0.1U_0402_16V4Z
20mils
1
2
C743
0.1U_0402_16V4Z
@
2
U22
FSEL#SPICS#
R437 2
FRD#SPI_SO 1
15_0402_5%
<35> FSEL#SPICS#
<35> FRD#SPI_SO
15_0402_5%
1
2
R431
SPI_CS# 1
SPI_SO 2
3
4
CS#
SO
WP#
GND
VCC
HOLD#
SCLK
SI
8
7
6
5
33_0402_5%
SPI_CLK_R1
SPI_SI 1
MX25L1605AM2C-12G SO8 ROM 33_0402_5%
R465
2 SPI_CLK
2 FWR#SPI_SI
<28> FSEL#SPICS#_SB
<28> FRD#SPI_SO_SB
SPI_CLK <35>
FWR#SPI_SI <35>
R603
2
1
15_0402_5%
@
@
15_0402_5%
1 SPI_CS#_SB
SPI_SO_SB
2
R605
R467
U35
1
2
3
4
CS#
SO
WP#
GND
VCC
HOLD#
SCLK
SI
8
7
6
5
SPI_CLK_SB
SPI_SI_SB
1
15_0402_5%
SPI_CLK_SB <28>
FWR#SPI_SI_SB <28>
2
R606
MX25L512AMC-12G_SO8
@
SPI_CLK_R
1
3
5
7
2
4
6
8
2
4
6
8
R106
33_0402_5%
+3VALW
SPI_SI
E&T_2941-G08N-00E~D
ME@
2 R466
SPI_CLK
1
15_0402_5%
FD6
FD4
FD5
1
FD2
1
FD3
FD1
1
3
5
7
+3VALW
JP12
SPI_CS#
SPI_SO
@
1
C573
22P_0402_50V8J
H21
HOLEA
H22
HOLEA
H3
HOLEA
H1
HOLEA
LED
H23
HOLEA
H20
HOLEA
H7
HOLEA
H10
HOLEA
H18
HOLEA
H16
HOLEA
H19
HOLEA
+5VS
H26
HOLEA
1
H28
HOLEA
1
H27
HOLEA
H9
HOLEA
H25
HOLEA
H6
HOLEA
H5
HOLEA
1
H4
HOLEA
H8
HOLEA
CHARGE_LED1#
CHARGE_LED0#
PWR_LED#
<35> CHARGE_LED1#
<35> CHARGE_LED0#
<35> PWR_LED#
H2
HOLEA
1
2
3
4
5
6
7
8
GND
GND
1
2
3
4
5
6
7
8
9
10
BT_LED#
WLAN_LED#
H12
HOLEA
JP24
+5VALW
<32> BT_LED#
<32> WLAN_LED#
H13
HOLEA
H14
HOLEA
TP_LED# <35>
19-215SUBC/S280/TR8 0603 BLUE
2
2
1.27K_0402_1%
H24
HOLEA
1
R585
+5VS
1 LED1
ACES_85201-08051~N
JP25
+5VS
<35> SCROLL_LED#
<35> CAPS_LED#
<35> NUM_LED#
<39> DRIVE_LED#
1
2
3
4
5
6
7
8
SCROLL_LED#
CAPS_LED#
NUM_LED#
DRIVE_LED#
1
2
3
4
5
6
GND
GND
ACES_85201-06051
Compal Secret Data
Issued Date
[email protected]
2007/10/15
Deciphered Date
2008/10/15
Title

LED/EC SPI ROM
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
38
of
53
+5VS
+3VS
1
1
C274
1000P_0402_50V7K
2
C462
0.1U_0402_16V4Z
2
C298
1U_0603_10V4Z
2
C461
C469
10U_0805_10V4Z 10U_0805_10V4Z
2
2
SATA HDD Conn.
C316
0.1U_0402_16V4Z
2 @
SATA ODD Conn.

JP15
JP18
2
SATA_DTX_C_IRX_N0
1
C684
SATA_DTX_C_IRX_P0
1
C685
1
2
3
4
5
6
7
SATA_ITX_DRX_P0
SATA_ITX_DRX_N0
SATA_DTX_IRX_N0
0.01U_0402_16V7K
SATA_DTX_IRX_P0
2
0.01U_0402_16V7K
2
+3VS
+5VS
GND
A+
AGND
BB+
GND
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12
23
24
G1
G2
SATA_DTX_C_IRX_N1
1
C676
SATA_DTX_C_IRX_P1
1
C675
2
2
SATA_ITX_DRX_P1
SATA_ITX_DRX_N1
SATA_DTX_IRX_N1
0.01U_0402_16V7K
SATA_DTX_IRX_P1
0.01U_0402_16V7K
+5VS
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
8
9
10
11
12
13
DP
+5V
+5V
MD
GND
GND
OCTEK_SLS-13SB1G
ME@
OCTEK_SAT-22SB1G_RV
ME@
D20
1
<27> SATA_LED#
RB751V_SOD323
DRIVE_LED#
2
DRIVE_LED# <38>
Issued Date
[email protected]
A
2007/10/15
2008/10/15
Deciphered Date
B
Compal Secret Data
Title
HDD & ODD Connector

Size
B
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Date:
G
Sheet
39
H
of
53
+1.5VS_CARD1
Imax = 0.75A
1
Express Card Power Switch

+1.5VS
2
C482
1
0.1U_0402_16V4Z
12
14
+3VS
2
C483
2
C500
<8,16,26,32,33,36> PLT_RST#
1
0.1U_0402_16V4Z
+3VALW
1
0.1U_0402_16V4Z
PLT_RST#
SYSON
<35,42,48> SYSON
<30,35,41,42,46,48,49,50>
SUSP#
2 R337
+3VALW
<28>
SUSP#
1 @
CPUSB#
CPUSB#
100K_0402_5%
C467
10U_0805_10V4Z
U16
2
4
17
6
1.5Vin
1.5Vin
1.5Vout
1.5Vout
3
5
+3VS_CARD1
AUX_OUT
15
+3VALW_CARD1
OC#
19
3.3Vin
3.3Vin
AUX_IN
3.3Vout
3.3Vout
SYSRST#
20
SHDN#
STBY#
NC
10
CPPE#
GND
9
18
+1.5VS_CARD1
11
13
PERST#
C489
0.1U_0402_16V4Z
JEXP1
2
40mil
<28> USB20_N10
<28> USB20_P10
60mils
+3VS_CARD1
C468
10U_0805_10V4Z
PERST#
1
C488
0.1U_0402_16V4Z
CPUSB#
+1.5VS_CARD1
Imax = 1.35A
40mil
1
New Card Socket (Left/TOP)

1
+3VALW_CARD1
PERST#
+3VS_CARD1
16
<22> EXP_CLKREQ#
<22> CLK_PCIE_EXP#
<22> CLK_PCIE_EXP
CPUSB#
CPUSB#
<28> PCIE_RXN4
<28> PCIE_RXP4
+3VALW_CARD1
RCLKEN
Imax = 0.275A
R5538_QFN20
<28> PCIE_TXN4
<28> PCIE_TXP4
1
C495
C499
10U_0805_10V4Z
0.1U_0402_16V4Z
2
2
@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
GND
GND
FOX_1CH4110C_LT
ME@
(NEW)
2
CMOS Camera Conn

+5VS
C784
0.1U_0402_16V4Z
1
1
IN
R661
0_0603_5%
<28>
<28>
USB20_N2
USB20_P2
CMOS1
USB20_N2
USB20_P2
Q36
1
C785
10U_0805_10V4Z
<35> CMOS_OFF#
GND
OUT
1 2
R660
10K_0402_5%
Q35
JP1
1
2
3
4
5
6
7
1
2
3
4
5
GND1
GND2
ACES_88266-05001
ME@
Compal Secret Data
2007/10/15
Issued Date
[email protected]
A
2008/10/15
Deciphered Date
B
Title

NEW CARD & CMOS Connector
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
E
40
of
53
+3VS
Switch Board Conn.
Power Button
2
+3VALW
ON/OFF#
ON/OFFBTN#
1
2
ON/OFF#
ON/OFFBTN#
NOVO_BTN#
<35>
51_ON#
51_ON#
I2C_INT_C
<44>
+3VALW
DAN202UT106_SC70-3
C810
0.1U_0402_16V4Z
1 @
C811
0.1U_0402_16V4Z
1 @
2
2
33K_0402_5% IN
<5,16,35>
<35,37>
<35>
<5,16,35>
<35,37>
<35>
<35>
<35,37>
<35,37>
EC_SMB_CK2
KSI4
ESB_CK
EC_SMB_DA2
KSO14
ESB_DA
I2C_INT
KSO15
KSI0
+3V
<35,37> KSI3
+3V
2
G
Q19
2N7002_SOT23-3
<30> EXT_MIC_L
EXT_MIC_L
Lid Switch
C796
0.1U_0402_16V4Z
1 @
GNDS
R663
0_0603_5%
<30> EXT_MIC_R
+VCC_LID
2
0_0402_5%
R429 1
C503
47P_0402_50V8J
2
VDD
GND
1
U19
1
0_0402_5%
2
2 0_0402_5%
0_0402_5%
2
2 0_0402_5%
0_0402_5%
EC_SMB_CK2_C
EC_SMB_DA2_C
I2C_INT_C
C494
220P_0402_50V8J
Audio Jack
EXT_MIC_R-2
MIC IN
@
C508
47P_0402_50V8J
@ C518
220P_0402_50V8J
JMIC1
1
2
6
3
GNDA
JACK_PLUG_MIC
<30> JACK_PLUG_MIC
CY@
1ENE@
R638 1
R622
CY@
1ENE@
R639 1
R624
EXT_MIC_L-2
GNDA
LID_SW# <35>
2
FB2
L26
FBM-11-160808-700T_0603
2 100K_0402_5%
A3212ELHLT-T_SOT23W-3
OUTPUT
2 MBC1608121YZF_0603
R620
FB1
L46 CY@ 1
GNDA
EXT_MIC_R
1
C561
0.1U_0402_16V4Z
2 MBC1608121YZF_0603
GNDA
1
R432
L45 CY@ 1
1
2
L25
FBM-11-160808-700T_0603
1
+3VALW
R662
0_0603_5%
2
1
R244
GND
EC_ON
Q24
C809
0.1U_0402_16V4Z
@
<35,46>
EC_ON
OUT
R243
4.7K_0402_5%
D6
RLZ20A_LL34
ACES_85201-08051
ME@
2
C411
1000P_0402_50V7K
1
C795
0.1U_0402_16V4Z
@
1
2
3
4
5
6
7
8
GND
GND
2
D5
R721
4.7K_0402_5%
@
1
R720
4.7K_0402_5%
@
R242
100K_0402_5%
Bottom Side
1
@ JOPEN
1
@ JOPEN
J2
EC_SMB_CK2_C
EC_SMB_DA2_C
I2C_INT_C
SMT1-05_4P
TOP Side
J1
FB1
FB2
1
2
3
4
5
6
7
8
9
10
JP3
ON/OFFBTN#
NOVO_BTN#
6
5
ON/OFF switch
CY@
SW1
R724
0_0603_5%
C547
10P_0402_50V8J
GNDA5
1
C522
SINGA_2SJ-S351-012
ME@
2
GNDA
220P_0402_50V8J
+3VALW
C564
R314
100K_0402_5%
NOVO#
<44>
51_ON#
2
51_ON#
GNDA
NOVO_BTN#
JHP1
3
DAN202UT106_SC70-3
Headphone
@ R452
1K_0402_5%
2
D9
1
<35>
NOVO#
@ R445
1K_0402_5%
220P_0402_50V8J
1
C568
220P_0402_50V8J
1
<30>
HP_L
<30>
HP_R
L28 1
2
FBM-11-160808-700T_0603
L29 1
2
FBM-11-160808-700T_0603
PL-OUT
PR-OUT
1
2
6
3
4
<30> JACK_PLUG_HP
5
SINGA_2SJ-S351-013
ME@
Compal Secret Data
Issued Date
[email protected]
2007/10/15
Deciphered Date
2008/10/15
Title

Audio Jack & SW connector
Size
B
Date:
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Sheet
41
of
53
+5VALW TO +5VS
+5VALW
+3VALW TO +3VS
+1.8V to +1.8VS
+5VS
+3VALW
+1.8V
+3VS
+1.8VS
U23
SI4800BDY-T1-E3_SO8
C360
PM@
R416 @
47K_0402_5%
1
2
0.1U_0603_50V4Z
+VSB
1
2
R450
47K_0402_5%
+VSB
1.8VS_GATE
SUSP
0.1U_0603_50V4Z
+1.8V
2
G
Q15 PM@
S
2N7002_SOT23
+5VALW
+5VALW
R234
R238
10K_0402_5% 100K_0402_5%
@
R236
470_0603_5%
<50>
SUSP
R237
100K_0402_5%
SUSP
R165
470_0603_5%
2
0.1U_0603_50V4Z
R68
470_0603_5%
C386
PM@ 0.1U_0603_50V4Z
RTCVREF
R283
470_0603_5%
+0.9VS
5VS_GATE
C389
@
+VCCP
SYSON#
2 SYSON#
G
Q20
2N7002_SOT23
R249
100K_0402_5%
+5VALW
0.01U_0402_16V7K
Q21
2N7002_SOT23
2
G
R248
100K_0402_5%
2 SUSP
G
Q12
2N7002_SOT23
<35,40,48> SYSON
SYSON
1
1
1
1
2 SUSP
G
Q10
2N7002_SOT23
Q22
2N7002_SOT23
2
G
<30,35,40,41,46,48,49,50> SUSP#
2 SUSP
G
Q25
2N7002_SOT23
1
1
SYSON#
C799
2 SUSP
G
Q13 PM@
2N7002_SOT23
R220
PM@
100K_0402_5%
C572
+1.5VS
R222
100K_0402_5%
5VS_GATE
2
Q32 G
2N7002_SOT23
R207
PM@
470_0603_5%
SUSP
C345
PM@
2 SUSP
G
Q30
2N7002_SOT23
1U_0603_10V4Z
C383
PM@
1
2
3
4
S
S
S
G
10U_0805_10V4Z
10U_0805_10V4Z
2
470_0603_5%
1 1
C365
PM@
D
D
D
D
C581
R418
SUSP
2
Q14G
2N7002_SOT23
8
7
6
5
SI4800BDY-T1-E3_SO8
C554
C563
10U_0805_10V4Z
2 SUSP
G
Q33
2N7002_SOT23
1
2
3
4
1U_0603_10V4Z
2
D
C559
S
S
S
G
R226
20K_0402_5%
C539
D
D
D
D
5VS_GATE
470_0603_5%
8
7
6
5
10U_0805_10V4Z
R468
10U_0805_10V4Z
10U_0805_10V4Z
C578
SI4800BDY-T1-E3_SO8
10U_0805_10V4Z
C580
1U_0603_10V4Z
S
S
S
G
+VSB
10U_0805_10V4Z
D
D
D
D
U9 PM@
U20
1
2
3
4
10U_0805_10V4Z
C577
C575
8
7
6
5
+5VS
C800
0.01U_0402_16V7K
C801
470P_0402_50V7K
C802
470P_0402_50V7K
C804
0.01U_0402_16V7K
C805
470P_0402_50V7K
2007/10/15
Issued Date
Compal Secret Data
Deciphered Date
2007/8/18
A
[email protected]
Title
DC Interface
Custom
Date:
Rev
1.0
JIWA3/A4_LA4212P
Sheet

E
42
of
53
LIFT USB CONN. 1
+5VALW
LIFT USB CONN. 2

+USB_VCCA
C803 470P_0402_50V7K
2
1
+USB_VCCA
+USB_VCCA
C694 0.1U_0402_16V4Z
2
1
<35>
USB_ON
GND
IN
IN
EN#
W=80mils
+USB_VCCA
U13
1
2
3
USB_ON 4
OUT
OUT
OUT
OC#
8
7
6
5
W=80mils
1
+
G545A1P1U_SO8
USB_OC#1 <28>
1
C691
USB_OC#0 <28>
150U_D2_6.3VM
C688
470P_0402_50V7K
C754
470P_0402_50V7K
JUSB1
C428
@ 1000P_0402_50V7K
USB20_N0
USB20_P0
<28> USB20_N0
<28> USB20_P0
1
2
3
4
VCC
DD+
GND
5
6
7
8
GND1
GND2
GND3
GND4
JUSB2
USB20_N1
USB20_P1
<28> USB20_N1
<28> USB20_P1
1
2
3
4
VCC
DD+
GND
5
6
7
8
GND1
GND2
GND3
GND4
SUYIN_020173MR004G579ZR
ME@
SUYIN_020173MR004G579ZR
ME@
+3VALW
Kill Switch
2
R706
100K_0402_5%
R581@
2
1
100K_0402_5%
<35>
KILL_SW#
SW2
+3VS
KILL_SW#
1BS003-1211L_3P
+5VALW
+USB_VCCC
U31
1
2
3
4
C693
GND
IN
IN
EN#
OUT
OUT
OUT
OC#
G545A1P1U_SO8
4.7U_0805_10V4Z
8
7
6
5
USB_OC#11 <28>
1
C690
USB_OC#4 <28>
W=80mils
W=80mils
1
<35> USB_ON
470P_0402_50V7K
1
1
C711
150U_D2_6.3VM
C716
470P_0402_50V7K
470P_0402_50V7K
JUSB4
JUSB3
+USB_VCCC
C786
C726
+USB_VCCC
+USB_VCCC
<28> USB20_N11
<28> USB20_P11
+USB_VCCC
1
@
C697
470P_0402_50V7K
2
+USB_VCCC
+USB_VCCC
0.1U_0402_16V4Z
2 @
RIGHT USB CONN.4
RIGHT USB CONN. 3
USB20_N11
USB20_P11
1
2
3
4
5
6
7
8
1
2
3
4
GND
GND
GND
GND
USB20_N4
USB20_P4
<28> USB20_N4
<28> USB20_P4
1
2
3
4
5
6
7
8
1
2
3
4
GND
GND
GND
GND
SUYIN_020173MR004S558ZL
SUYIN_020173MR004S558ZL
ME@
ME@
4
Issued Date
2007/10/15
Deciphered Date
2007/8/18
Title
[email protected]
A
Compal Secret Data
Power OK, Reset and RTC Circuit, TP

Custom
JIWA3/A4_LA4212P
Date:
Sheet
E
Rev
1.0
43
of
53
VIN
ACIN
PL6
SMB3025500YA_2P
1
2
PR69
1K_1206_5%
1
2
DC030006J00
PR70
1K_1206_5%
1
2
1
PD3
RLS4148_LL34-2
Vin Detector
VS
17.566
14.355
PR71
1K_1206_5%
1
2
PR72
1K_1206_5%
1
2
PD4
@ RLS4148_LL34-2
17.011
14.063
High 18.135
Low 14.866
PQ16
TP0610K-T1-E3_SOT23-3
1
VIN
PQ14
DTC115EUA_SC70-3
PR85
PC60
@ 10K_0402_1% @ 0.01U_0402_25V7K
1
2
1
2
PACIN
<40>
2
PR74
22K_0402_1%
OUT
IN
GND
PC106
10U_0805_10V4Z
@ MAXEL_ML1220T10
PC111
0.01U_0402_25V7K
PR81
47K_0402_5%
1
PACIN <40>
2
1
PR158
499K_0402_1%
1
PRG++ 2
2
G
S
+5VALWP
PQ17
DTC115EUA_SC70-3
+RTCBATT
N2
PQ10
SSM3K7002F_SC59-3
PD6
2
+CHGRTC
RB751V-40TE17_SOD323-2
SP093MX0000
3.3V
PR114
0_0603_5%
2
1
PR66
200_0603_5%
PU7
G920AT24U_SOT89-3
PR113
PR112
560_0603_5% 560_0603_5%
1
2
1
2
PR156
205K_0402_1%
1
2
RTC Battery
JRTC
1
2
2
2
PC48
0.1U_0603_25V7K
RTCVREF
PC47
1U_0805_25V4Z
[email protected]
Compal Secret Data
Issued Date
RTCVREF
+CHGRTC
PR153
10K_0402_5%
2
1
<32> 51_ON#
PU8B
LM393DG_SO8
1
PC57
0.22U_0603_25V7K
PR75
100K_0402_1%
VS
PC108
1000P_0402_50V7K
2
1
PR155
66.5K_0402_1%
N1
PR65
200_0603_5%
1
2
PR63
68_1206_5%
CHGRTCP
PR67
PQ6
68_1206_5%
TP0610K-T1-E3_SOT23-3
PD1
RLS4148_LL34-2
PD2
RLS4148_LL34-2
<40> PRECHG
PR154
200K_0402_1%
2
1
<40> ACON
PD15
RB715F_SOT323-3
2
1
3
<41,46> MAINPWON
3.3V
PC109
0.01U_0402_25V7K
VS
2
1
PR161
100K_0402_1%
2
RTCVREF
PR159
2.2M_0402_5%
2
1
VL
1
PR80
10K_0402_1%
LM393DG_SO8
PR160
10K_0402_1%
2
1
PQ13
DTC115EUA_SC70-3
2
1
PR157
499K_0402_1%
PACIN
VIN
BATT+
B+
3
<21,33>
ACIN
PU8A
PD5
RLZ4.3B_LL34
ACOFF
PR87
10K_0402_5%
1
2
1
2
PR86
215K_0402_1%
1
2
PC113
0.1U_0402_16V7K
2
1
PR84
82.5K_0402_1%
VS
2
1
PR82
24.9K_0402_1%
PC59
<33,40>
1
PR88
10K_0805_5%
PR83
1M_0402_1%
1
2
VIN
0.068U_0603_25V7M
2
1
VIN
PC107
0.1U_0603_25V7K
1
PR79
100K_0402_5%
1 2
2
1
PC52
100P_0402_50V8J
2
1
PC168
0.01U_0402_50V7K
JUMP_43X118
2
1
PC54
100P_0402_50V8J
2
1
PC167
0.01U_0402_50V7K
2
@
2
1
PC53
1000P_0402_50V7K
2
1
PC50
1000P_0402_50V7K
PJ9
4
BATT ONLY
Precharge detector
Min.
typ.
Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V
Precharge detector
Min.
typ.
Max.
H-->L 13.843V 14.247V 14.636V
L-->H 14.936V 15.381V 15.814V
2
1
PR77
100K_0402_5%
PF1
@ 7A_24VDC_429007.WRML
1
2
JDCIN
@ 4602-Q04C-09R 4P P2.5
2
1
PR76
100K_0402_5%
2007/06/22
Deciphered Date
2008/06/22
B
Title
DCIN & DETECTOR

Size
Date:
Document Number
Rev
1.0
Sheet
D
44
of
53
PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C
VL
1
VL
1
MAINPWON <4,36,39>
PR163
47K_0402_1%
O
PQ39
DTC115EUA_SC70-3
2
PU9A
LM393DG_SO8
8
3
VL
PR164
100K_0402_1%
PR165
100K_0402_1%
1
2
PR149
6.49K_0402_1%
EC_SMB_DA1 <29,34>
2
EC_SMB_CK1 <29,34>
1
2
PC115
1000P_0402_50V7K
PC26
0.01U_0402_25V7K
@ TYCO_1775768-1
PC101
1000P_0402_50V7K
PR148
100_0402_1%
TM_REF1
PR147
100_0402_1%
2
PR166
13.7K_0402_1%
1
2
BATT+
PR167
15.4K_0402_1%
@ JUMP_43X118
EC_SMCA
EC_SMDA
TS
PC116
0.22U_0603_16V7K
BATT_S1
1
2
3
4
5
6
7
8
9
PL3
SMB3025500YA_2P
1
2
PJ7
1
2
3
4
5
6
7
GND
GND
PC114
0.1U_0603_25V7K
1
JBATT
VMB
PH2
100K_0603_1%_TH11-4H104FT
PF2
@ 12A_65V_451012MRL
1
2
PR162
47K_0402_1%
VL
O
4
+3VALWP
7
2
PU9B
LM393DG_SO8
PR146
10K_0402_1%
A/D
BATT_TEMPA <29,34>
PJ19
2
PJ14
@ JUMP_43X39
1
2
2
2
+3VALW
+1.8VP
+5VALWP
+5VALW
+0.9VSP
1
3
PC87
0.1U_0402_16V7K
+0.9VS
3
PJ10
1
+1.5VS
JUMP_43X79
PJ11
PJ6
2
(2A,80mils ,Via NO.= 4)
@ JUMP_43X118
+VSBP
+1.8V
@ JUMP_43X39
PJ13
+1.5VSP
+VSB
+VGA_COREP
@ JUMP_43X39
PQ25
@ SSM3K7002F_SC59-3
PJ3
1
JUMP_43X118
2
G
(8A,320mils ,Via NO.=16)
(6.0A,240mils ,Via NO.=12)
PR116
@ 0_0402_5%
1
2

PJ15
2
1
POK
PJ12
1
@ JUMP_43X118
PR115
@ 100K_0402_1%
<39>
JUMP_43X118
+VSBP
PC88
0.22U_1206_25V7K
PR119
@ 22K_0402_1%
1
2
VL
2
1
PR120
100K_0402_1%
PC89
0.1U_0603_25V7K
B+
+3VALWP
PQ26
@ TP0610K-T1-E3_SOT23-3
+VGA_CORE
JUMP_43X79
(15A,600mils
,Via NO.=30)
(120mA,40mils ,Via NO.= 2)
S
PJ17
1
+VCCPP
PJ18
2
+VCCP
+VGA_CORE
JUMP_43X79
+VCCP
JUMP_43X79
(3000mA,120mils ,Via NO.= 6)
PJ21
1
+1.1VSP
+1.1VS
JUMP_43X79
4
Issued Date
[email protected]
A
Compal Secret Data
2007/6/22
Deciphered Date
2008/6/22
B
Title
BATTERY CONN / OTP

Size
Date:
Document Number
Rev
1.0
Sheet

D
45
of
53
2
16
OUTC1 FB123
15
11
SEL
12
-INC1
CTL
14
+INC1
13
PR135
@ 0_0402_5%
PC17
1500P_0402_50V7K
1
2
1
2
PC21
10P_0402_50V8J
1
PR33
0_0402_5%
IREF=0.4~2.88V
MB39A126
1
2
PR28
33K_0402_1%
BATT+
4
1
PR138
10K_0402_1%
3 2
2
PR125
10K_0402_1%
1
1
2
PR150
0.02_1206_1%
PD11
1
RB751V-40TE17_SOD323-2
2
FSTCHG <32>
PD10
1
RB751V-40TE17_SOD323-2
2
SUSP#
-INE3
10
PL5
10U_LF919AS-100M-P3_4.5A_20%
1
2
4
PQ29
@ DTC115EUA_SC70-3
PC102
10U_1206_25V6M
ACON
<39>
2
PRECHG <39>
2
PACIN
G
PQ28
SSM3K7002F_SC59-3
+INE1
ACON
PQ30
@DTA144EUA_SC70-3
2
RT
PR19
47K_0402_1%
1
2
PC103
10U_1206_25V6M
-INE1
17
18
PC91
0.1U_0603_25V7K
19
PR139
@ 100K_0402_1%
1
PR17
0_0402_5%
1
VH
ACIN XACOK
VREF
PC13
0.1U_0603_25V7K
1
2
ACOFF
PR18
10K_0402_1%
2
1
PD8
1SS355TE-17_SOD323-2
1
2
PD13
B340A_SMA2
20
VIN
VIN
PQ27
DTC115EUA_SC70-3
PD9
2
1
21SS355TE-17_SOD323-2
PQ5
FDS4435BZ_SO8
OUT
PC1
0.22U_0603_16V7K
1
2
PC8
0.1U_0603_25V7K
PD14
B340A_SMA2
ACOK
1
2
3
PR124
200K_0402_1%
1
2
4
3
2
1
21
G
S
S
S
VCC
D
D
D
D
CS
-INE2
5
6
7
8
+INE2
CS
LXCHRG
23
22
GND
OUTC2
8
7
6
5
PC150
0.01U_0402_25V7K
PC36
2200P_0402_50V7K
2
1
2
3
1
2
PR137
100K_0402_5%
PC9
0.22U_0603_16V7K
PR132
3K_0402_1%
1
2
PR14
PC14
1K_0402_1% 2200P_0402_50V7K
2
1
2
MB39A1261
PC37
0.1U_0603_25V7K
2
1
1
1
PR12
10K_0402_1%
2
1
PR1
31.6K_0402_1%
2
S PQ11
SSM3K7002F_SC59-3
PU1
MB39A126PFV-ER_SSOP24
1 -INC2 +INC2 24
Charger
PQ34
@ AO4407_SO8
8
7
6
5
PR121
47K_0402_1%
1
2
PR123
100K_0402_1%
2
1
65W: PR1=49.9K
90W: PR1=31.6K
2
1
PC16
0.01U_0402_25V7K
2
ACON
PR122
10K_0402_5%
PR27
100K_0402_1%
1
2
2
G
<39>
1
2
FBMA-L11-321611-121LMA30T_1206
PR126
PC90
10K_0402_1% 4700P_0402_25V7K
1
2
1
2
1
PR22
100K_0402_1%
PQ7
SSM3K7002F_SC59-3
<33> IREF
PACIN
1
2
3
2
1
PR78
150K_0402_1%
3
1
2
G
PC6
0.01U_0402_25V7K
1
2
<39>
ADP_I
PC92
0.22U_0603_16V7K
MB39A126
CHG_B+
PL12
PR152
0.015_1206_1%
PQ9
DTA144EUA_SC70-3
PQ8
DTC115EUA_SC70-3
PQ32
AO4407_SO8
1
2
3
A/D
<31,33>
PJ8
@ JUMP_43X118
2 2
1 1
B+
1
2
PC56
0.1U_0603_25V7K
2
1
PR73
200K_0402_1%
1
2
3
4
2
1
PR68
47K_0402_5%
2
1
PC162
1800P_0402_50V7K
2
1
PC160
0.01U_0603_50V7K
VIN
8
7
6
5
P3
PQ38
FDS4435BZ_SO8
S
D 8
S
D 7
S
D 6
G
D 5
Fosc=14100/Rt=14100/47=300KHz
CP mode
65W: 2.8A
90W: 4.0A
PC38
4.7U_1206_25V6K
2
1
P2
PQ37
FDS4435BZ_SO8
D
S 1
D
S 2
D
S 3
D
G 4
BATT+
PC39
4.7U_1206_25V6K
2
1
PD12 @ RB751V-40TE17_SOD323-2
1
2
EC_ON
PC22
47P_0402_50V8J
1
2
VMB
3
2
2
LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.1112*BATT+
3
2
Adapter 65W CP Point=2.8A
5V*(10K/(49.9K+10K))=0.835V
1
2
PU3A
LM358DR_SO8
PU3B
LM358DR_SO8
2006/08/04
Adapter 90W CP Point=4A

4
5V*(10K/(31.6K+10K))=1.202V
1.202V/(20*0.015)=4.006A

2006/10/06
Deciphered Date
B
0.835V/(20*0.015)=2.78A
Compal Secret Data
Issued Date
PC20
0.01U_0402_25V7K
0
4
Charge voltage
3S CC-CV MODE : 12.6V
SEL is L
PR23
10K_0402_1%
2
1
<33> BATT_OVP
VS
8
7
1.44/(20*0.02)=3.6A
1
2
1
PR29
PR34
499K_0402_1% 340K_0402_1%
PQ2
DTC115EUA_SC70-3
A/D
[email protected]
(100K/(100K+100K))*2.88V=1.44V
VMB
VS
CC=3.6A
FSTCHG
<33>
PQ1
DTC115EUA_SC70-3
1
PR35
105K_0402_1%
PQ15
DTC115EUA_SC70-3
PC5
0.01U_0402_25V7K
ACOFF
PC161
1800P_0402_50V7K
2
1
<39>
CS
1
PR2
47K_0402_5%
+3VALWP
Title
CHARGER
Size
B
Date:
Document Number
Rev
1.0
Sheet
E
46
of
53
ISL6237_B+
ISL6237_B+
B+
LGATE2
VL
PGND
22
OUT1
10
FB1
11
BYP
SKIP
29
NC
POK2
28
EN_LDO
POK1
13
EN1
ILIM1
12
ILM1
ILIM2
31
ILIM2
30
OUT2
32
REFIN2
2VREF_ISL6237
1
2
PC119
0.22U_0603_10V7K
REF
LDOREFIN
PD16
RB751V-40TE17_SOD323-2
1
2
20
PR118
100K_0402_1%
1
2
4
PC86
0.22U_0603_25V7K
PQ40
AO4712_SO8
PC129
4.7U_1206_25V6K
2
1
PC134
2200P_0402_50V7K
2
1
1
+ PC135
220U_6.3V_M
GND
TON
NC
FB5
2
1
PR175
@ 0_0402_5%
1
2
PR177
0_0402_5%
VL
POK <38>
PU10
ISL6237IRZ-T_QFN32_5X5
2
1
PR176
301K_0402_1%
2
1
PR170
301K_0402_1%
21
PC125
@ 0.047U_0402_16V7K
PC123
0.047U_0402_16V7K
0_0402_5%
PC149
1U_0402_6.3V6K
OS-CON
PR169
0_0402_5%
2VREF_ISL6237 2
PR178
0_0402_5%
PR182
@ 47K_0402_5%
2VREF_ISL6237 1
2
1
1
806K_0603_1%
PR181
MAINPWON
@ PR180
0_0402_5%
VL
PR179
EN2
27
PD17
@ RB751V-40TE17_SOD323-2
1
2
<42,44>
14
PR117
200K_0402_5%
1
2
PC124
0.1U_0603_25V7K
2
1
PC166
470P_0402_50V7K
2
1
PC165
0.01U_0402_25V7K
DL5
1
23
PHASE2
PR174
61.9K_0402_1%
2
LGATE1
18
LX5
25
PC157
680P_0402_50V7K
PHASE1
16
PR172
10K_0402_1%
1
2
FB3
PD7
RLZ5.1B_LL34
1
2
3
2
1
PC122
2
1
1U_0402_6.3V6K
BST5A2
PR184
0_0603_5%
VS
4.7U_0603_6.3V6K
7
BOOT1
BOOT2
3
2
1
1
1
2
3
DL3
DH5
17
19
15
+5VALWP
PQ43
AO4466_SO8
24
PVCC
UGATE1
PL10
2
1
4.7UH_PCMC063T-4R7MN_5.5A_20%
PC127
1U_0402_6.3V6K
1
2
5
6
7
8
2
1 BST3A
PR183
0_0603_5%
PC126
0.1U_0603_25V7K
LX3
UGATE2
LDO
TP
26
8
7
6
5
PR196
6.8_1206_5%
1
2
PR173
10K_0402_1%
PQ41
AO4712_SO8
PC156
680P_0402_50V7K
2
1 2
2
2
OS-CON
PR171
0_0402_5%
33
DH3
VCC
PL11
1
2
4.7UH_PCMC063T-4R7MN_5.5A_20%
+3VALWP
VIN
1
2
3
PC120
0.1U_0603_25V7K
PC121
1
2
VL
PQ42
AO4466_SO8
4
PR195
6.8_1206_5%
1
8
7
6
5
5
6
7
8
PC132
2200P_0402_50V7K
2
1
PC130
4.7U_1206_25V6K
2
1
PC128
4.7U_1206_25V6K
2
1
PC131
4.7U_1206_25V6K
2
1
PR168
0_0805_5%
1
2
PL13
1
2
FBMA-L11-321611-121LMA30T_1206
PC133
220U_6.3V_M
2007/06/22
Issued Date
[email protected]
5
Compal Secret Data
Deciphered Date
2008/06/22
+5V/+3V
4
Title

Custom
Date:
Rev
1.0
Sheet
1
47
of
53
1
2
PR101
2.2_0603_1%
2
2
1
PR103
10_0603_1%
PC67
0.1U_0603_25V7K
2
1
PR97
10_0603_1%
1
1
1
2
VO2
26
11
EN1
OCSET2
25
PU6
1
2
PL9
1.8UH_SIL104R-1R8PF_9.5A_30%
5
6
7
8
BOOT2
LX_1.5V
PR193
6.8_1206_5%
1
2
PC69
0.1U_0402_16V7K
PC79
1U_0402_6.3V6K
+ PC117
220U_6.3V_M
1 2
2
+1.5VSP
1
4
2
1
+5VALW BST_1.5V
PR99
0_0603_5%
LG_1.8V
PR106
0_0402_5%
2
1
UG_1.5V
3
2
1
2
1
PC76
1U_0402_6.3V6K
22
PR94
10.5K_0402_1%
PQ22
AO4466_SO8
21
PVCC2
20
LGATE2
19
PGND2
18
PGND1
17
PVCC1
UGATE2
LGATE1
BOOT1
PR104
0_0603_5%
16
1BST_1.8V14
1 2
1
2
23
PC68
0.033U_0402_16V7K
PHASE2
SUSP#
<42,44>
PC71
0.1U_0402_16V7K
2
UGATE1
+5VALW
OS-CON
PC154
680P_0402_50V7K
PQ24
AO4712_SO8
LG_1.5V
1.8V_EN
SYSON
<42,44>
24
PC74
4.7U_1206_25V6K
EN2
PHASE1
ISL6228_B+
PR100
47K_0402_5%
1
2
4
2
1
2
PR98
10.5K_0402_1%
PC82
0.1U_0402_16V7K
PR92
PC66
3.3K_0402_5% 1000P_0402_50V7K
2
1
1
2
2
1
PR93
26.1K_0402_1%
8
7
6
5
UG_1.8V 13
PQ23
AO4712_SO8
PR96
16.5K_0402_1%
+5VALW
FSET2
2
VIN2
3
VCC2
VCC1
FSET1
OCSET1
15
10
1.8V_EN
27
ISL6228HRTZ-T_QFN28_4X4
1
2
3
OS-CON
2
PR186
@ 0_0402_5%
PC75
4.7U_1206_25V6K
FB2
1
2
3
PC72
4.7U_1206_25V6K
8
7
6
5
1
2
1
PC118
220U_6.3V_M
PC158
680P_0402_50V7K
2
1 2
PC159
10U_0805_6.3V6M
2
1
28
VO1
LX_1.8V 12
1
+
PQ21
AO4466_SO8
1.8UH_SIL104R-1R8PF_9.5A_30%
PR197
6.8_1206_5%
+1.8VP
PR110
10.5K_0402_1%
PC73
4.7U_1206_25V6K
2
1
PL8
PGOOD2
ISL6228_B+
PC84
0.022U_0402_25V7K
1
FB1
29
5
6
7
8
GND_T
3
2
1
1
2
PR107
10.5K_0402_1%
PGOOD1
1
2
PR109
34.8K_0402_1%
ISL6228_B+
PR95
18.2K_0402_1%
2
1
2
PR185
@ 0_0402_5%
+5VALW
PR111
3.3K_0402_5%
2
PC85
1000P_0402_50V7K
2
1
1
PC70
1000P_0402_50V7K
PR108
22K_0402_1%
VIN1
PC81
1000P_0402_50V7K
PR105
16.5K_0402_1%
ISL6228_B+
1
2
ISL6228_B+
FBMA-L11-321611-121LMA30T_1206
+5VALW
PC80
0.1U_0603_25V7K
PL14
PC77
1U_0402_6.3V6K
+5VALW
2
1
PR102
2.2_0603_1%
B+
PC78
1U_0402_6.3V6K
PC83
@ 0.01U_0402_25V7K
Issued Date
[email protected]
A
Compal Secret Data
2007/06/22
Deciphered Date
2008/06/22
B
Title
1.8V / 1.5V
Size
Date:
Document Number
Rev
1.0
Sheet

D
48
of
53
UG_1.05V
PR54
PR60
10K_0402_1%
2
BOOT_1.05V
PC43 0.1U_0603_25V7K
VCC
UG
BOOT
PVCC
LG
13
PGND
12
ISEN
11
1
2
PR50
4.7_0603_5%
1
2
PC33
2.2U_0603_6.3V6K
6268_1.05V
4
LG_1.05V
PL7
1UH_PCMB103E-1R0MS_20A_20%
1
2
+VGA_CORE
+VGA_COREP
PU4
ISL6268CAZ-T_SSOP16
+
PC112
220U_6.3V_M
PC148
10U_0805_6.3V6M
OS-CON
PR57
@ 0_0402_5%
PC155
680P_0402_50V7K
1 2
2
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8
PQ12
FDS8672S 1N SO8
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8
PQ18
FDS8672S 1N SO8
ISEN_1.05V
1
2
PR52
3.9K_0402_1%
VO
10
FSET
PR194
6.8_1206_5%
2
PR55
0_0402_5%
+VGASENSE
2
PR53
@ 0_0402_5%
+VCCP
PR51
37.4K_0402_1%
PC34
0.01U_0402_25V7K
PR58
2.8K_0402_1%
1
PR61
49.9K_0402_1%
PC49
6800P_0402_25V7K
1
2
PC45
22P_0402_50V8J
PC44
@ 0.1U_0402_16V7K
1
2
FB
EN
COMP
PC46
2.2U_0603_6.3V6K
PR64
0_0402_5%
1
2
3
2
1
PQ19
SI4686DY-T1-E3_SO8
PHASE
VIN
14
PGOOD
GND
15
16
PC51
@ 0.1U_0402_16V7K
5
6
7
8
PR49
0_0603_5%
1
2
1_0603_5%
+5VS
1
2
PR62
0_0603_5%
1
2
1
PC58
10U_1206_25V6M
PHASE_1.05V
6268_1.05V
6268_1.05V
<19,27,29,30,35,40,42> SUSP#
6268_B+
2
1
PC55
10U_1206_25V6M
PC151
1000P_0402_50V7K
2
1
PC163
1800P_0402_50V7K
1
2
2
1
PC164
470P_0603_50V8J
PL15
1
2
FBMA-L11-321611-121LMA30T_1206
B+
PR59
3K_0402_1%
2007/6/22
Issued Date
2008/6/22
Deciphered Date
[email protected]
5
Compal Secret Data
Title
VGA_CORE
Size
Date:
Document Number
Rev
1.0
Sheet
1
49
of
53
PC141
10U_0805_6.3V6M
+5VS
+VGA_CORE
PC136
1U_0402_6.3V6K
PU11
3
4
FB
+VCCPP
PC142
10U_0805_6.3V6M
PC139
0.01U_0402_25V7K
GND
APL5912-KAC-TRL_SO8
PC110
0.47U_0402_6.3V6K
PR188
1.27K_0402_1%
EN
POK
VOUT
VOUT
1
8
7
1
<19,27,29,30,35,40,42> SUSP#
VCNTL
VIN
VIN
PR187
100K_0402_5%
1
2
6
5
9
PR189
3.65K_0402_1%
PJ4
@ JUMP_43X39
+1.8V
VCNTL
GND
NC
VREF
NC
VOUT
NC
TP
+3VALW
1
VIN
2
1
2
PR91
1K_0402_1%
PC64
4.7U_0603_6.3V6K
PU5
1
PC65
1U_0402_6.3V6K
+0.9VSP
PC63
0.1U_0402_16V7K
PR90
1K_0402_1%
S PQ20
SSM3K7002F_SC59-3
PC62
10U_0805_6.3V6M
PC61
@ 0.1U_0402_16V7K
+1.8VS
2
G
PR89
0_0402_5%
1
2
SUSP
<35>
APL5331KAC-TRL_SO8
PJ20
JUMP_43X79
VCNTL
GND
NC
VREF
NC
VOUT
NC
TP
+5VS
1
VIN
2
1
2
PR190
1.91K_0402_1%
PC144
4.7U_0603_6.3V6K
PU12
1
PC145
1U_0402_6.3V6K
+1.1VSP
PR192
3.16K_0402_1%~D PC143
0.1U_0402_16V7K
S PQ44
SSM3K7002F_SC59-3
PC147
22U_0805_6.3V6M
PC146
@ 0.1U_0402_16V7K
2
G
PR191
0_0402_5%
1
2
SUSP
<35>
APL5331KAC-TRL_SO8
2007/6/22
Issued Date
2008/6/22
Deciphered Date
[email protected]
5
Compal Secret Data
Title
VCCP/0.9V/1.1V
Size
Date:
Document Number
Rev
1.0
Sheet
1
50
of
53
PHASE2
28
PHASE_CPU2
UGATE2
27
UGATE_CPU2-1
BOOT2
26
NC
25
BOOT_CPU2
1
PR43
1_0603_5%
PC40
3300P_0402_50V7K
1
2
PC42
680P_0402_50V7K
2
1
1
2
PC105
220U_25V_M
PR45
10K_0402_1%
2
1
1
PR48
2
3.65K_0402_1%
1
2
VCC_PRM
ISEN1 PC27
0.22U_0603_10V7K
2
3
2
1
0.36UH_MPC1040LR36_24A_20%
2
G
S
S
S
4
3
2
1
+5VS
1 2
PR145
6.8_1206_5%
PC29
0.22U_0603_10V7K
PC98
680P_0402_50V7K
PL2
PQ31
FDS8672S 1N SO8
1
2
1K_0402_1%
VSUM
PQ3
FDMS8692 1N POWER56-8
PQ33
FDS8672S 1N SO8
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8
5
6
7
8
D
D
D
D
ISEN1
4
UGATE_CPU2-2
24
23
22
21
20
19
18
17
16
15
13
1
PR10
@ 0_0402_5%
PR3
1
1
2
2
1
PR134
PC94
97.6K_0402_1% 470P_0402_50V7K
1
2
PC93
220P_0402_50V7K
LGATE_CPU2
ISEN1
ISEN2
2
PR141
1_0603_5%
PR40
@ 0_0603_5%
1
2
29
+CPU_CORE
PR44
1_0402_5%
PR144
1_0402_5%
PR140
@ 0_0603_5%
1
2
PGND2
PL4
PR143
10K_0402_1%
2
1
31
30
+CPU_B+
1
PVCC
ISEN2
VDD
GND
VIN
VSUM
VO
DFB
DROOP
FB2
RTN
FB
12
VSEN
11
VDIFF
COMP
14
10
PC152
2200P_0402_50V7K
2
1
1 2
2
5
6
7
8
LGATE_CPU1
LGATE2
PU2
ISL6262ACRZ-T_QFN48_7X7
PC104
680P_0402_50V7K
2
1
PR46
3.65K_0402_1%
33
32
PQ36
FDS8672S 1N SO8
1
PGND1
LGATE1
D
D
D
D
D
D
D
D
PHASE_CPU1
G
S
S
S
5
6
7
8
37
39
40
41
42
43
44
46
45
38
UGATE_CPU1-1
34
4
3
2
1
VW
35
PHASE1
PR151
6.8_1206_5%
5
9
UGATE1
G
S
S
S
OCSET
36
PC41
0.01U_0402_25V7K
B+
0.36UH_MPC1040LR36_24A_20%
2
1
3
2
1
0.22U_0603_10V7K
PC28
2 1
2
4
3
2
1
VID0
SOFT
VID1
NTC
VID2
VID3
VR_TT#
VID4
RBIAS
VID5
VID6
PMON
VR_ON
PSI#
47
48
49
2
BOOT1
1
2 1
2
PR127
PH3
@ 4.22K_0402_1%
@ 100K_0603_1%_TH11-4H104FT
1
2
PC4
@ 0.015U_0402_16V7K
1
2
PC3
0.022U_0402_16V7K
PR5 1
2
13K_0402_1%
1
2
PC2
1000P_0402_50V7K
PR133 1
2
6.81K_0402_1%
1
2
PC95
1000P_0402_50V7K
PC35
10U_1206_25V6M
2
1
PC32
10U_1206_25V6M
2
1
PC153
470P_0402_50V7K
2
1
1
PC99
2.2U_0603_6.3V6K
2
1
PC100
0.022U_0402_16V7K
2
1
CPU_VID1 <5>
<5>
CPU_VID2 <5>
<5>
CPU_VID3
CPU_VID4
CPU_VID0 <5>
1_0603_5%
PR42
1
PC30
10U_1206_25V6M
2
PR6
147K_0402_1%
VR_TT#
BOOT_CPU1
PL1
HCB4532KF-800T90_1812
1
2
1
PQ4
FDMS8692 1N POWER56-8
PC31
10U_1206_25V6M
2
1
2
PR7
@ 0_0402_5%
UGATE_CPU1-2 4
PQ35
FDS8672S 1N SO8
CPU_VID5 <5>
<30>
H_PSI#
PGD_IN
PGOOD
DPRSLPVR
<5>
DPRSTP#
<21,30> VGATE
+CPU_B+
PC10
1U_0402_6.3V6K
1
PR8
2
PR9
0_0402_5%
499_0402_1%
1.91K_0402_1%
PR13
2
1
PR21 0_0402_5%
2
1
PR25 0_0402_5%
2
1
PR26 0_0402_5%
2
1
PR31 0_0402_5%
2
1
PR32 0_0402_5%
2
1
PR36 0_0402_5%
2
1
PR37 0_0402_5%
2
1
PR39 0_0402_5%
+3VS
+3VS
PR142
1_0603_5%
3V3
<21> CLK_ENABLE#
CLK_EN#
<5,8,20> H_DPRSTP#
VR_ON
1
PR20
0_0402_5%
1
PR16
0_0402_5%
1
PR15
0_0402_5%
<8,21> DPRSLPVR
GND
CPU_VID6 <5>
+5VS
VSUM
1
PC24
1U_0402_6.3V6K
PC97
0.22U_0603_10V7K
VCC_PRM
ISEN2
2
1
2
PC12
0.018U_0603_50V7J
PC11
0.018U_0603_50V7J
PC96
0.1U_0603_25V7K
PC15
0.018U_0603_50V7J
PR41
2.61K_0402_1%
2
1
2
PR30
1K_0402_1%
VCC_PRM
PC18
0.22U_0603_10V7K
2PC19
180P_0402_50V8J
1
2
PR24
4.42K_0402_1%
PH1
10KB_0603_5%_ERTJ1VR103J
1
PR131
20_0402_5%
1
PR130
0_0402_5%
1
2
1
PR38
11K_0402_1%
<5> VSSSENSE
2
+CPU_B+
PR136
10_0603_1%
VSUM
1
+CPU_CORE 1
PR129
20_0402_5%
2
PR4
1K_0402_1%
1
PR128
0_0402_5%
<5> VCCSENSE
2PC7
1000P_0402_50V7K
1
2
PR11
255_0402_1%
1
1
2
PC23
0.1U_0402_16V7K
2
1
PC25
0.22U_0402_6.3V6K
2007/6/22
Issued Date
[email protected]
5
Compal Secret Data
2008/6/22
Deciphered Date
+CPU_CORE
4
Title

Custom
Date:
Rev
1.0
Sheet
1
51
of
53
NO DATE
PAGE
MODIFICATION LIST
PURPOSE
------------------------------------------------------------------------------------------------------------10/12
P48
Add PR185, PR186
Reserve for debug use.
10/12
P49
Delete PC110
Because HW reserve enough CAP.
10/17
P49
Add PU11, PC136, PC141, PC142, PC139, PC110,

PR187, PR188, PR189
Because need separate +VCCP and +VGA_CORE
10/17
P49
Change PR58 from 2.7k_0402_1% to 2.8k_0402_1%

PR59 from 3.24k_0402_1% to 3k_0402_1%.
HW request change VGA_CORE from 1.1V to 1.16V
Compal Secret Data
Issued Date
[email protected]
2005/06/01
Deciphered Date
2006/06/01
Title

Power PIR
Size
Document Number
Rev
1.0
JIWA3/A4_LA4212P
Date:
Sheet
51
of
51
NO DATE
PAGE
MODIFICATION LIST
PURPOSE
------------------------------------------------------------------------------------------------------------1 12/10
P29
C615 change to R615 and BOM Structure change to PM@
Fix DIS Audio issue
2 12/10
P20P21
R104 & R154 BOM Structure change to PM@
Reduce cost
3 12/10
P16
R86R645R646R650R651R652 & R653

Structure change to PM@
4 12/10
P29
R614 change from 10K to 45.3ohm

R615 change from 12K to 54.9ohm
Fix UMA Audio issue
5 12/10
P08
R79 change from 33 to 10ohm

R80R81R82 & R85 change from 0 to 22 ohm
Fix UMA Audio issue
6 12/10
P30
The C783 links to GND
Fix Internal MIC issue

Fix F/B issue
7 12/10
P41
Add L45 & L46 MBC1608121YZF Bead
8 01/02
P11
Change C126 package
9 01/02
BOM
Reduce cost
P28
Add R707 to connect VGATE to M_PWROK
10
01/02
P16
Add R699 to connect +VGASENSE
Modify power sequence
11
01/02
P16
Remove U3.P1
12
01/02
P19
Add R700 to connect GND
13
01/02
P11
Add C707
for +VCC_DMI
14
01/02
P16
Add C788
for nvidia request for +PEX_PLLVDD
15
02/27
P08
change R147 from 511 ohm 1% to 499 ohm 1%
16
02/27
P23
change D4 location
17
02/27
P23
Add D25 , D26
18
02/27
P25
Add D27 , D28 & D29
19
02/27
P29
Add R713 connect to 1.5V
20
02/27
P31
change C550 , C570 , C506 & C507 to 0.1uF 0603
21
05/08
P05
Add R726 1k ohm & C808 0.1uF to fix issue.
22
05/08
P16
Remove R48 for EMI request.
23
05/08
P27
Change R554 from 0 ohm to 33 ohm for EMI request.
24
05/08
P28
Add R566 10 ohm & C733 10pF for EMI request.
25
05/08
P30
Add R327 47 ohm & C458 33pF for EMI request.
26
05/08
P35
Change C501 & C514 from 15pF to 12pF
27
05/08
P37
Add D31 (PJDLC05_SOT23-3) for ESD request.
28
05/08
P41
Add C494C522C564 & C568 220pF for EMI request
for ESD
for ESD
Fix pop noise issue
Title
<Title>
[email protected]
5
Size
Document Number
CustomJIWA3/A4_LA4212P
Date:
4
Rev
1.0
Sheet
1
53
of
53

Lenovo g530 n500 - Compal La-4212p Jiwa3 Jiwa4 - Rev 1

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Document Informationclick to expand document informationCOMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT.

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Lenovo g530 n500 - Compal La-4212p Jiwa3 Jiwa4 - Rev 1

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A

Mobile Penryn uFCPGA

Wednesday, May 14, 2008

Compal Secret Data

Compal Electronics, Inc.

Size Document Number

Swithch & CAP SENSE LEDs Board

Right LED Board

Left LED Board

DDR2 -667 (1.8V)

Intel Cantiga GMCH

CRT & TV OUT

Compal Secret Data

Compal Electronics, Inc.

Size Document Number

Monday, May 12, 2008

SMBUS Control Table

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.9V switched power rail for DDR terminator

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

1.8V switched power rail

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Compal Secret Data

Compal Electronics, Inc.

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for GPU

1.1V switched power rail

1.8V power rail for DDR

1.8V switched power rail

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail

PEX_VDD can ramp up any time

Compal Secret Data

Compal Electronics, Inc.

RSVD pins on the CPU

XDP_BPM#5 reserve a via for debuging

H_THERMDA, H_THERMDC routing together,

Compal Secret Data

Compal Electronics, Inc.

Trace Close CPU < 0.5'

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)

For testing purpose only

VCCA_DAC_BG: 2.68mA (0.1UF1, 0.01UF1)

VCCA_CRT_DAC: 73mA (0.1UF1, 0.01UF1)