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54208-mt - Design For Testability

This document contains questions that appear to be from an exam on design for testability of digital circuits. The questions cover several topics: 1) The difference between testing and design for testability of digital circuits and modeling digital circuits at the logic and register level. 2) Logic fault models like stuck-at faults and bridging faults, and how redundancy can help detect faults. 3) How ATPG/ATG can detect stuck-at faults in combinational circuits using examples. 4) Commonly used DFT techniques in digital circuits and testability trade-offs.

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SRINIVASA RAO GANTA
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832 views2 pages

54208-mt - Design For Testability

This document contains questions that appear to be from an exam on design for testability of digital circuits. The questions cover several topics: 1) The difference between testing and design for testability of digital circuits and modeling digital circuits at the logic and register level. 2) Logic fault models like stuck-at faults and bridging faults, and how redundancy can help detect faults. 3) How ATPG/ATG can detect stuck-at faults in combinational circuits using examples. 4) Commonly used DFT techniques in digital circuits and testability trade-offs.

Uploaded by

SRINIVASA RAO GANTA
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Code No: 54208/MT

NR
M.Tech. – II Semester Regular Examinations, September, 2008

DESIGN FOR TESTABILITY


(Common to Embedded Systems/ VLSI System Design/
VLSI & Embedded Systems)

Time: 3hours Max. Marks:60

Answer any FIVE questions


All questions carry equal marks
---
1.a) Differentiate between testing and design for Testability (DFT) of
digital circuits.
b) Discuss in detail about modeling of digital circuits at logic level
and register level.
c) What is a structural model?

2.a) Discuss about logic fault models of stuck at faults and Bridging
faults.
b) What is redundancy? With an example, explain how redundancy is
useful in making the digital circuits fault detectable.

3.a) With an example, explain how ATPG/ATG is useful in detection of


SSFs in combinational circuits.
b) What is vector simulation, give an example?

4.a) Describe the commonly used DFT techniques in digital circuits.


b) Discuss about Testability trade – offs.

5.a) Define the terms:


(i) Controllability (ii) Observability
b) Discuss about DFT approaches at
(i) Board level (ii) System level

6.a) With neat diagrams, discuss briefly about the following BIST
architectures:
(i) CSBL (ii) STUMPS (ii) RTD
b) What are the memory test requirements for MBIST?

7.a) What is automatic in circuit testing (AICT). Give an examples.


b) Discuss indetail about JTAG Testing features.

8. Write short notes on the following:


(a) Delay models and Hazard detection
(b) Embedded memory testing.

&_&_&_&

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