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VLSI - Algorithm of Binary Image Labeling and Parameter Extracting Based On FPGA

This algorithm labels binary images and extracts parameters using FPGA to identify rail profiles in real-time. It overcame issues with previous methods by not needing to repeatedly scan pixels or require large memory. The FPGA implementation labels connected components and extracts features during blank periods, accurately identifying image connectivity faster than software. Testing on rail measurement scenes showed it meets requirements for real-time image recognition systems.

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38 views1 page

VLSI - Algorithm of Binary Image Labeling and Parameter Extracting Based On FPGA

This algorithm labels binary images and extracts parameters using FPGA to identify rail profiles in real-time. It overcame issues with previous methods by not needing to repeatedly scan pixels or require large memory. The FPGA implementation labels connected components and extracts features during blank periods, accurately identifying image connectivity faster than software. Testing on rail measurement scenes showed it meets requirements for real-time image recognition systems.

Uploaded by

ncctprojects
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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NC CT

Promise for the Best Projects

IEEE PROJECTS 2010-11

VLSI & FPGA

ALGORITHM OF BINARY IMAGE LABELING AND PARAMETER EXTRACTING BASED ON FPGA


ABSTRACT
For the real-time detection and identification requirements of the rail profile image, A quickly algorithm using connectivity labeling of binary image and parameter extracting to remove the speckle disturbing was presented in this paper, based on FPGA, it can use the limited hardware resources of the system to realize high-speed and accurate binary image labeling and feature extraction, obtain the bright band image and region. This method overcomes the shortcoming of previous methods which must scan pixel repeated and require a large memory to record the relationship of the connected components, and a large computation to merge the labeling. Also, it is rapid, simple, rules, and extensibility, the processing speed will be increased by providing a quick effective way to identify and record the complex relationship between regions, and by completing the label merge or parameter extraction during the line or field blanking realizing of FPGA can accurately and effectively identify the complex connectivity between images, produce the correct label results and extract the characteristic parameters of each connected component which can limit the subsequent processing in a rectangle and save the time and resource greatly, provide guarantee for subsequent identification. The algorithm is used and we have a good effect on the scene testing of rail measurement, it is enough to meet the requirement of real-time image recognition system.

Tools used Language FPGA

: Xilinx Platform Studio :C : SPARTAN 3 XC3S200

Compiler code : Verilog/VHDL SPARTAN 3 EDK KIT EMBEDDED SYSTEMS PROJECTS / IEEE PROJECTS

NC CT

MICROCONTROLLERS * VLSI * DSP * MATLAB


, 28235816, 93801 02891, 98411 93224 , www.ieeeprojects.net , [email protected]

www.ncct.in

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