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The document discusses different modeling types for digital circuits including gate level, dataflow, and behavioral modeling. It provides examples of modeling common logic components like a full adder, multiplexer, demultiplexer, encoder, and decoder using the different modeling styles. Code snippets in Verilog are shown for implementing these components as gate level, dataflow, and behavioral models.

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49 views

C CC CCC CCC CCC CC CC CCCCCCC CCC!CCC"C ###########################C C CCC$C CCC CCCC"C% CC

The document discusses different modeling types for digital circuits including gate level, dataflow, and behavioral modeling. It provides examples of modeling common logic components like a full adder, multiplexer, demultiplexer, encoder, and decoder using the different modeling styles. Code snippets in Verilog are shown for implementing these components as gate level, dataflow, and behavioral models.

Uploaded by

avinashthegreat9
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Modeling types 1.gate level 2.data flow 3.behavioural 4.structural 5.

RTl ( combination of - data flow & behavioural ) ___________________________

General pattern for programming ( modeling ) :Gate level :module fn(ip,sel,op) input []ip; output []op; wire; not; not; and; and; and; and; or; or; endmodule

Dataflow :-

module fn(ip,sel,op) input []ip; output []op; assign; assign; endmodule

Behavioural model :module fn(ip,sel,op) input []ip; output []op; reg []op; always@(ip or sel ) begin case (ip or sel) _ b0000 :op=_ b0000; _ b0000 :op=_ b0000; _ b0000 :op=_ b0000; _ b0000 :op=_ b0000; default:op= _ ; end case end endmodule

programmes for various logics

..

FULL ADDER :Dataflow :module fa(a,b,cin,sum,cout) input a,b,cin; output sum, cout; assign sum=a^b^cin; assign cout=(a&b)!(a&cin)!(b&cin); endmodule

MUX 4x1 :Gate level :module mux41(ip,sel,op) input [3:0]ip , [1:0]sel; output op; wire t1,t0,w0,w1,w2,w3; not n1(t1,sel[1]); not n2(t0,sel[0]); and a1(w0,i[0],t1,t0); and a2(w1,i[1],t1,s[0]); and a1(w2,i[2],s[1],t0); and a1(w3,i[3],s[1],s[0]); or o1(op,w0,w1,w2,w3); endmodule

Dataflow :module mux41(ip,sel,op) input [3:0]ip , [1:0]sel; output op; assign= ( ( (~s[1])&(~s[0])&(i[0] ) )! ( (~s[1])&(s[0])&(i[1]) ) ! ( (s[1])&(~s[0])&(i[2]) ) ! ( (s[1])&(s[0])&(i[3]) ) ); endmodule

Behavioural model :module mux41(ip,sel,op) input [3:0]ip , [1:0]sel; output op; reg op; always@(ip or sel ) begin case (sel) 2 b00 :op=_ip[0]; 2 b01 :op=_ip[1]; 2 b10 :op=_ip[2]; 2 b11 :op=_ip[3]; default:op= 1 b0 ; end case end endmodule

DEMUX 1x4 :Gate level :module fn(ip,sel,op) input []ip; output []op; wire; not; not; and; and; and; and; or; or; endmodule

Dataflow :module fn(ip,sel,op) input []ip; output []op; assign; assign;

endmodule

Behavioural model :module fn(ip,sel,op) input []ip; output []op; reg []op; always@(ip or sel ) begin case (ip or sel) _ b0000 :op=_ b0000; _ b0000 :op=_ b0000; _ b0000 :op=_ b0000; _ b0000 :op=_ b0000; default:op= _ ; end case end endmodule

ENCODER 4x2:Gate level :module fn(ip,sel,op) input []ip;

output []op; wire; not; not; and; and; and; and; or; or; endmodule

Dataflow :module fn(ip,sel,op) input []ip; output []op; assign; assign; endmodule

Behavioural model :module fn(ip,sel,op) input []ip; output []op; reg []op;

always@(ip or sel ) begin case (ip or sel) _ b0000 :op=_ b0000; _ b0000 :op=_ b0000; _ b0000 :op=_ b0000; _ b0000 :op=_ b0000; default:op= _ ; end case end endmodule

DECODER 2x4 :Gate level :module fn(ip,sel,op) input []ip; output []op; wire; not; not; and; and; and;

and; or; or; endmodule

Dataflow :module fn(ip,sel,op) input []ip; output []op; assign; assign; endmodule

Behavioural model :module fn(ip,sel,op) input []ip; output []op; reg []op; always@(ip or sel ) begin case (ip or sel) _ b0000 :op=_ b0000; _ b0000 :op=_ b0000; _ b0000 :op=_ b0000; _ b0000 :op=_ b0000;

default:op= _ ; end case end endmodule

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