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Lecture Schedule

This document provides the lecture schedule for the course Digital Electronics at B. S. A. College of Engineering & Technology for the third year of 2010-11. It outlines 52 lectures over the course topics which are divided into 5 units - Digital systems and binary numbers, Combinational Logic, Synchronous Sequential logic, Memory and programmable logic, and Asynchronous sequential logic. The lectures cover various digital design concepts like gates, adders, decoders, registers, counters, RAM, ROM, PLA, PAL and their analysis and design procedures. Revisions of the units are scheduled at the end along with a final test.

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Farhan Aziz
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63 views2 pages

Lecture Schedule

This document provides the lecture schedule for the course Digital Electronics at B. S. A. College of Engineering & Technology for the third year of 2010-11. It outlines 52 lectures over the course topics which are divided into 5 units - Digital systems and binary numbers, Combinational Logic, Synchronous Sequential logic, Memory and programmable logic, and Asynchronous sequential logic. The lectures cover various digital design concepts like gates, adders, decoders, registers, counters, RAM, ROM, PLA, PAL and their analysis and design procedures. Revisions of the units are scheduled at the end along with a final test.

Uploaded by

Farhan Aziz
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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B. S. A.

College of Engineering & Technology, Mathura


(Established & Governed by Agarwal Shiksha Mandal)

Digital Electronics (EEC-302) Semester: 3rd Year: 2010-11 Lecture Schedule


L. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Date Topic Unit 1: Digital system and binary numbers: Signed binary numbers, binary codes Cyclic codes, error detecting and correcting codes Error detecting and correcting codes, Hamming codes. Floating point representation Gate-level minimization: The map method up to five variable, dont care conditions Gate-level minimization: The map method up to five variable, dont care conditions POS simplification, NAND and NOR implementation Quine Mc-Clusky method (Tabular method) Quine Mc-Clusky method (Tabular method) Revision Unit 2: Combinational Logic: Combinational circuits Analysis procedure, design procedure Analysis procedure, design procedure Binary adder- subtractor Decimal adder, binary multiplier Magnitude comparator Decoders Encoders Multiplexers Revision Unit 3: Synchronous Sequential logic: Sequential circuits Storage elements: latches, flip flops Storage elements: latches, flip flops Analysis of clocked sequential circuits State reduction and assignments Design procedure Registers and counters: Shift registers, ripple counter Synchronous counter Other counters Revision Reference

Branch: EC

1.6, 1.7, 7.4

3.1 to 3.7, 3.10

4.1 to 4.11

5.1 to 5.5, 5.7 to 5.8 6.1 to 6.5

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L. No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Date

Topic Unit 4: Memory and programmable logic: RAM ROM PLA PAL Design at the register transfer level ASMs, design example ASMs, design example Design with multiplexers Design with multiplexers Revision Unit 5: Asynchronous sequential logic: Analysis procedure Circuit with latches, design procedure Reduction of state and flow table Reduction of state and flow table Race free state assignment Hazards Revision of Unit 1 Revision of Unit 2 Revision of Unit 3 Revision of Unit 4 Revision of Unit 5 Test of complete syllabus

Reference

7.1 to 7.3, 7.5 to 7.7 8.4, 8.5, 8.10

9.1 to 9.7

Text Book: 1. M. Morris Mano and M. D. Ciletti, Digital Design, 4th Edition, Pearson
Education.

Reference Book : 1. Hill & Peterson, Switching Circuit & Logic Design, Wiley.

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