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Modeling of Switched-Capacitor DeltaSigma Modulators in SIMULINK

Hashem Zare-Hoseini, Izzet Kale, and Omid Shoaei, Member, IEEE

op-amps thermal noise), clock jitter, nonidealities of integrators and op-amps including nite dc-gain (DCG) and unity gain bandwidth, slew-limiting, DCG nonlinearities and the input parasitic capacitance, quantizer hysteresis, switches clock-feedthrough, and charge injection, exhaustive behavioral simulations that are close models of the transistor-level ones can be performed. The DCG nonlinearity of the integrators, which is not considered in many modulators modeling attempts, is analyzed, estimated, and modeled. It is shown that neglecting this parameter would lead to a signicant underestimation of the modulators behavior and increase the noise oor as well as the harmonic distortion at the output of the modulator. Evaluation and validation of the models were done via behavioral and transistor-level simulations for a second-order modulator using SIMULINK and HSPICE with a generic 0.35- m CMOS technology. The effects of the nonidealities and nonlinearities are clearly seen when compared to the ideal modulator in the behavioral and actual modulator in the circuit-level environment.

16 modulators is presented. Considering noise (switches and

AbstractPrecise behavioral modeling of switched-capacitor

16

Index TermsCharge injection, clock feedthrough, correlated double sampling, deltasigma modulators, hysteresis, nonideality, nonlinearity, SIMULINK, switched capacitor.

I. INTRODUCTION MONG the oversampling converters, ones have achieved the most attraction recently in high-resolution applications due to their noise shaping behavior that leads them to inherent superior linearity, simple realization, and low sensitivity to circuit imperfections [1]. Such converters reduce the need for complex analog circuit implementation and, due to their oversampling nature, act as the most suitable architectures for accurate low to moderately high frequency applications. modulators can be realized in either the continuous-time (CT) or switched-capacitor (SC) approach. While CT modulators have the advantages of lower power consumption, higher speed, and intrinsic anti-aliasing ltering, they suffer from the difculty of designing, sensitivity to clock jitter, and also excess loop delay [2]. As far as the implementation technique is concerned, SC modulators are preferred to CT modulators because they can be more efciently realized in standard CMOS technology [1], [3]. Moreover, they provide a highly controllable

Manuscript received June 15, 2004; revised April 15, 2005. H. Zare-Hoseini and I. Kale are with the Applied DSP and VLSI Research Group, Department of Electronic Systems, University of Westminster, London, W1W 6UW, U.K. (e-mail: [email protected]) O. Shoaei is with the IC Design Laboratory, Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran. Digital Object Identier 10.1109/TIM.2005.851085

design as well as being more robust to clock jitter and feedmodulators are back delay problems. In this paper, the SC considered. modulators have relatively straightforward Although realizations, the appropriate architecture selection, including single loop or MASH, loop lter type, order and coefcients, and the number of bits of the quantizer, would be a difcult task. Also, the requirements of the building blocks such as integrators bandwidth, dc-gain (DCG), slew rate and output swings, the quantizer threshold, the digital-to-analog converter (DAC), the switches, and the clock and power supply accuracy cannot be easily estimated. Several techniques have been used for time-domain analysis of these modulators listed and discussed briey in [3], such as SPICE, SWITCAP, and table-lookup models. For instance, the SPICE simulations are precise, but they take extremely long times especially for very high-resolution narrow-band modulators because of both long period cycles and the high accuracy needed. Hence, choosing the optimized architecture and estimating the requirements of building blocks is a very time-consuming procedure in transistor-level design and simulation (SPICE). There is a need for a time-efcient and accurate simulation environment. To this effect, the user friendly, versatile SIMULINK tool was chosen to develop detailed models of the modulators building blocks. The popular SIMULINK simulator proved to be an excellent time-efcient candidate for this initial task. In this paper, detailed analytical models of the basic building blocks (integrators and op-amps) and also the nonidealities of a typical modulator are presented, followed by SIMULINK modulator models have models of them. Most previous not considered the effect of DCG nonlinearity in integrators, leading to a signicant underestimation of the modulators behavior and harmonic distortion. In this paper, this is analyzed, estimated, and modeled in SIMULINK, as well as other blocks modulator. Moreover, several behavioral and of a typical transistor-level simulations were performed in SIMULINK and HSPICE using a generic 0.35- m CMOS technology to validate the analyses and models. Since in the rst stage of very high-resolution modulators correlated-double-sampled (CDS) integrators are routinely used to attenuate the effect of offset and icker noise, for comparison purposes, both typical and CDS integrators are discussed in this paper. In Section II, the integrator characteristics such as nite DCG, nonlinear DCG, and settling behavior are presented. Section III presents noise contributors such as sampling and op-amp thermal noise. Switch nonidealities are considered next following with a discussion about clock jitter. In Section VI, a brief review of quantizer nonidealities are discussed. Then the

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Fig. 2. A typical op-amps DCG versus output voltage with the rail-to-rail voltage of V . Fig. 1. Single-ended SC integrators. (a) Typical and (b) CDS.

a leakage in the integrator. The precise transfer function of the two integrators shown in Fig. 1(a) and (b) is (2)

simulation results and evaluation of the models will be presented in Section VII.

II. INTEGRATOR NONIDEALITIES The -domain transfer function of an ideal delayed integrator is (1) where and are the integrators gain and leakage, respectively [4]. Although zero delay integrators can be used to realize the desirable lter, most often delay integrators are used in the rst stage of the modulators as they are easily implemented in circuit level. In the case of a nonideal integrator, deviates from unity. There are several architectures to realize this transfer function of the integrator. Fig. 1 shows a typical and a CDS integrator (for simplicity of illustration, we have opted to deploy the single-ended conguration. However, all our practical investigations were carried out on full differential versions of these integrations). While the typical integrators are widely modulators, the CDS ones used in moderate accuracy are used for very high-resolution approaches for attenuating offset and Flicker noise of the front-end integrator [4]. The size of the op-amps input transistors are kept large to minimize the op-amps noise in very high-resolution modulators; consequently the op-amps input capacitance is also increased. These capacitors have also been considered in the models of the integrators. There are many nonidealities that alter the ideal transfer function of (1), including the integrators nite DCG and bandwidth, slew-limiting, and DCG nonlinearities. These effects, which are the major causes of performance degradation in SC modulators, are discussed in this section. A. Finite DCG The nite DCG moves the pole of the ideal integrator in (1) from dc ( ) to another frequency. This effect is known as where , , and and are the op-amps input parasitic capacitance and the nite DCG, respectively. Equations (2) and (3) clearly show that the nite DCG degrades the integrators gain and moreover introduces leakage which is different in the two integrators. B. Settling Behavior Slew rate (SR) and unity-gain bandwidth (UGBW) are the two distinct parts of the settling behavior of the op-amps. While in SR-limited region, the output of the op-amp operates in its nonlinear part, in the bandwidth-limited region (small-signal settling period) it behaves linearly [5], [6]. In the high-resolution applications, the integrator is forced to settle in fast regime wherein the settling time constant is smaller than an upper limit and the SR is larger than a lower limit [7]. Therefore, for an integrator, in the presence of its op-amps UGBW and SR, its settling behavior will be linearly/nonlinearly affected. With the assumption of a single-pole model for the integrator, (4) and (5) show the output voltages of the integrators in Fig. 1 in the integrating phase, respectively (4) (5) , where is the integrator time-constant, , and are the clock period and the integrating period (phase in Fig. 1), respectively. The settling behavior of the two integrators is different because the CDS integrator resets at each sampling phase while the typical one does not. If the integrator (3)

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SR is greater than the maximum slope of the output voltage (at ), slew-limiting never occurs. Otherwise, the output will slew before the time instant where the slew-limitation ends and is derived from the relation [5] (6) The output voltages of the integrators in Fig. 1 in the th integrating phase are obtained from (7) and (8), respectively, as shown at the bottom of the page. For implementing the above equations in single expressions to be incorporated as a SIMULINK functions, (7) and (8) can be merged and resume up to

will hence produce the odd harmonic in the output, as will be seen in the results section of this paper. In [10], for the sake of simplicity, we have extracted the DCG-nonlinearity equations without using the absolute value function. However, from the SIMULINK modeling point of view, we can use this function in the blocks modeling. To derive the output voltage of the typical integrator in Fig. 1(a), the nonlinear DCG in (11) is substituted into terms and in (2)

(9)

(12) Using the SIMULINK function, direct estimation of the output voltage of an integrator with the nonlinear-DCG is a very difcult task because and are functions of instantaneous output voltage that itself depends on and at the same time and so creates a delayless loop. Here, for rst-order estimation of and , is approximated by its ideal value that is the term . As a result, the terms and in (12) will be

(10) where denotes the Signum function. The Signum function and the absolute value of are incorporated to contemplate both the rise and fall slopes. In the above analysis of settling behavior for both integrators, it is assumed that the valid data are produced at the end of the ). However, this is only true for the CDS one. second phase ( For the typical integrator, the output data are sampled by the next stage of the modulator at the end of the next phase. As the integrator characteristic in this phase is changed (the input capacitor is disconnected and also the output capacitance is changed), the integrator will show a transient behavior which will affect the output voltage. The output at the end of this phase can be derived in the same way as for the previous phase using (9). This dynamic transient behavior is discussed in [8]. Moreover, there is a more precise settling behavior analysis in [6]. C. Nonlinear DCG Although the nite DCG of the integrators affects the position of the dominant pole and changes the integrators gain, it does not directly contribute to distortion. Distortion is introduced by the integrators DCG nonlinearity resulting from its dependency on the output voltage as shown in Fig. 2, where the rail-to-rail output swing is assumed to be . This important effect is not modeling attempts, for example, considered in the previous as was the case with [3]. The op-amps DCG can be expressed as that in [9] (11) From (11) and Fig. 2 it is apparent that the op-amps DCG in fully differential congurations is nearly an even function and

(13) Likewise, the term in (3) will be

(14) and will be like in (13). The discussed DCG nonlinearity can be taken into account by the integrator model shown in Fig. 3. As shown, the nonlinear DCG introduces an additional loop to the single-loop conguration of the integrator. Furthermore, although the effect of the nonlinear DCG, modeled by and , is taken into account, the saturation levels of the op-amp are ensured by the saturation block as shown in Fig. 3. This DCG nonlinearity model enables us to estimate the maximum permitted output swing of the integrators. Two ways

(7) (8)

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Fig. 3. Model of an integrator with nonlinear DCG. Fig. 4. Model of sampling and input referred op-amps noise sources in SIMULINK.

can decrease the effect of it: rst, decreasing the integrators output swing that can lead to the decrement of the modulators signal-to-(noise plus distortion) ratio (SNDR), and second, increasing the nite DCG and designing an op-amp with high linear DCG which both increase the power consumption of the integrator. So, a tradeoff between these two factors should be considered. III. NOISE Sampling noise and the op-amps thermal and icker noise of the rst integrator are the fundamental limitation in the design modulators [4]. The noise of the other of high-resolution stages is suppressed and shaped due to the nature of the modulator. In our models, icker noise is not considered because some techniques like CDS approach substantially reduce its effect [11]. A. Sampling Noise Sampling noise is dened as the thermal noise of the switch resistance sampled by a capacitor [1]. It is bandlimited by the equivalent time-constant of the sampling circuit and has the power of (15) where , , and are Boltzmanns constant, the temperature in kelvin, and the sampling capacitor, respectively [5]. To model noise, the input-referred sampling noise of the effect of the integrator should be calculated and consequently added to the input signal. The input-referred sampling noise of the integrators in Fig. 1 is approximately (16) which results from the thermal noise of the input switches in both sampling and integrating phases. B. Op-Amps Thermal Noise This noise that is due to the thermal noise of its transistors is modeled in a similar fashion to the sampling noise. The input-referred thermal noise of the typical integrator shown in Fig. 1(a) is [7] (17)

Fig. 5.

A typical S/H.

and for the CDS one shown in Fig. 1(b) is (18) denotes the input-referred thermal noise of the where op-amp. Both the sampling and thermal noise can be taken into account by the SIMULINK model shown in Fig. 4. IV. SWITCH NONIDEALITIES Switches are one of the major elements in SC circuits. The ideal role of them is to have zero or innite resistance when they are on or off. However, as switches in CMOS technology are realized by using nMOS and pMOS transistor, they manifest some nonidealities such as nonlinear on-resistance, clockfeedthrough, and charge injection [12]. Nonlinear on-resistance which is a signal-dependent variation of the on-resistance of the switch introduces harmonic distortion into the circuit. There are many ways to degrade this nonlinearity, such as decreasing the sample and hold (S/H) time constant, using transmission gates, clock-boosting and bootstrapping (in low-voltage applications), etc. [12], [13]. Clock-feedthrough is due to the charge of the gate-to-source overlap capacitors of the switch injected to the sampling capacitor when it turns off. The error charge due to the clockfeedthrough for the S/H shown in Fig. 5 is (19) and represent the overlap capacitors on where nMOS and pMOS transistors, respectively. This error is signal

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Fig. 6. The BPS realization. (a) An S/H schematic. (b) First, switch S turns off and releases some signal-independent charge into the sampling capacitor C . (c) Then, while C is almost oating, the input switch S turns off and releases some signal-dependent charge that mostly folds back to the input source.

independent and in a fully differential integrator is attenuated by the common-mode rejection ratio (CMRR) of its op-amp. Charge injection is due to mobile channel charge injected to the sampling capacitor when the switch turns off. This charge ows out from the channel mostly to the drain and the source and a little to the substrate [11]. The fraction of the charge going to each terminal depends on the ratio of the terminals capacitance, the switch parameters, and the slope of the clock. So, the charge going to the sampling capacitor cannot be predicted easily. If the clock is sharp enough or the terminals (the drain and the source) have the same impedance, the channel charge will split symmetrically; otherwise, it will mostly ow to the terminal showing the lower impedance [11]. For the CMOS switch shown in Fig. 5, the error charge due to this nonideality is

Fig. 7.

Clock-jitter modeling in the input front-end of the modulator.

(20) where , , , and are the gate-to-oxide capacitance, channel width, channel length, and threshold voltage of the is nMOS or the pMOS transistor, respectively. The factor the fraction of the charge coming into the sampling capacitor rather than coming back to the input source. Taking a quick look, (20) shows that the error charge is linearly proportional is a function of the input to the input signal. However, as signal [5], the charge error will be a nonlinear function of the input signal and introduces harmonic distortion into the circuit. If the nMOS and the pMOS transistor have the same dimension size, this error will be eliminated. However, to have a linear on-resistance in the CMOS switch, i.e., to have a switch with maximum dynamic range, different sizes are considered for these two transistors resulting to the charge injection. A more precise charge-injection modeling can be found in [13]. Several techniques are used to attenuate this problem such as using fully differential structure, bigger capacitors, dummy switches, and shifting clocks [bottom plate sampling (BPS)] [11]. modulators is shown A BPS mechanism widely used in in Fig. 6. As demonstrated in this gure, when the switches are going off, rst, the bottom switch ( ) turns off and a few moments later, the input switch ( ) turns off. The amount of turns off is charge injected to the sampling capacitor when signal-independent as it is connected to the ground. When turns off, the sampling capacitor is oating and so the switch charge ows back to the input source. Therefore, in this mechanism, only some signal-independent charge enters into the cir-

Fig. 8. (a) Quantizer functions including hysteresis and offset. (b) SIMULINK model of it.

cuit, which can be greatly attenuated using fully differential conguration. Although BPS reduces the switch charge injection, there are still some leakages. When is off, the sampling capacitor is not ideally oated and is in series with the capacitor , the parasitic capacitance of switch , and the following stage of it. Hence, a portion of the charge will ow to the sampling capacitor. To model this leakage, the factor in (20) should be replaced by (21) For rst-order estimation, in the integrators of Fig. 1, this leakage charge is compensated in the integrating phase ( ) as the parasitic capacitor becomes in parallel with the sampling capacitor . For second-order estimation these charge errors leak to the integrating capacitor as a function of op-amps DCG and CMRR.

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Fig. 9.

(a) Ideal second-order single-loop single-bit

16 modulator. (b) Its nonideal model.

error power is decreased by either increasing OSR or decreasing the input bandwidth [1]. VI. QUANTIZER A quantizer suffers from some nonidealities such as offset modulators, the quantizer is a comand hysteresis. For 1-bit parator. Offset of the comparator is attenuated by the dc gain of the previous stages, and so the modulator is almost insensitive to it. The hysteresis occurrence shown in Fig. 8(a) has a twofold worsening effect: increasing the noise power and shifting the noise spectrum toward the signal band [14]. Both offset and hysteresis were modeled in SIMULINK using the simple Relay block shown in Fig. 8(b). Their effects were found to be insignificant for moderately small level of deviation from ideal. It was further observed that to have a noticeable effect, the hysteresis parameters had to be substantially increased. VII. SIMULATION AND EVALUATION RESULTS In order to validate the behavioral model derived in this paper and compare the effects of nonidealities and nonlinearities with modthe ideal modulator, rst, the second-order low-pass ulator shown in Fig. 9 with the parameters listed in Table I was used. As mentioned before, in the behavioral simulations, only the nonidealities of the rst integrator were considered, as the others are substantially shaped and suppressed. Fig. 10 shows the output SNDR of the modulator as a function of the integrator time-constant and SR of the rst integrator. It shows that decreasing the SR or increasing will decrease the output SNDR. In the case of non-slew-limiting, the large (nite UGBW) ideally acts as an integrator gain-reducer that modulators are less sensitive to. However, in an actual modulator, because of the nonlinear DCG of the integrators,

TABLE I PARAMETERS OF THE MODULATOR SHOWN IN FIG. 9

V. CLOCK JITTER Clock jitter, the intrinsic uncertainty in the transition time of the clock, increases the in-band noise of the modulator [1]. It has less effect on the sampled-data part of the modulators. The effect of clock jitter on an SC modulator is dominated by its is effect on the sampling time of the analog input signal. If the analog input signal, the error resulting from an inaccuracy of in the clock transition time will be (22) Under the assumption that the time jitter is an uncorrelated Gaussian random process having standard deviation , implementation of (22) can be done in SIMULINK by the model shown in Fig. 7. The upper bound of the in-band error power at the output of the modulator for a sinusoidal input will be [1] (23) where OSR, , and are the oversampling ratio, the maximum input signal frequency, and its amplitude, respectively. This equation shows the well-known fact that the total in-band

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TABLE II SPECIFICATION OF THE MODULATOR SHOWN IN FIG. 9 WITH THE PARAMETERS LISTED IN TABLE I USED FOR SIMULINK SIMULATIONS

Fig. 10.

The output SNDR as a function of time-constant and SR.

Fig. 13. The output PSD of the ideal and leaky modulator ( 0:001 for both stages) of Fig. 9 with parameters of Table I versus hysteresis or offset voltage relative to the reference voltage.

Fig. 11. The PSDs of the modulator output with the rst integrator nonlinear DCG of 9, 18, and 37 dB.

Fig. 12. The output PSDs of the ideal, thermal noise affected, and CJA modulator with the parameters shown in Table II.

this nominally ideal gain-reducer will be nonlinear [7] and so introduces harmonic distortion into the output, as will be shown in the next paragraph. Fig. 11 shows the output spectrum of the modulator with the rst integrators nonlinear DCG. It is clearly seen that the non-

linear DCG introduces odd harmonic distortion to the output of the modulator and moreover increases the in-band noise level. The amount of linearity needed for the DCG of the rst integrator is subject to the whole desired SNDR, and as shown in Fig. 11, with 37 dB linearity, the SNDR equals 96 dB. The most efcient way to increase the DCG linearity is to decrease the output levels of the integrators, which can be done by signalscaling [7]. Fig. 12 shows the output power spectral densities (PSDs) of the ideal, thermal noise affected, and clock jitter affected (CJA) modulator with the parameters shown in Table II. It is clearly seen that these nonidealities increase the in-band noise oor as expected. In the case of clock jitter, it is shown that the noise oor is dependent on the input sinusoidal frequency as suggested by (22). To see the effect of the quantizer hysteresis and offset, the output SNDR of the modulator versus hysteresis and offset relative to the reference voltage is shown in Fig. 13. The ideal and leaky modulators (the modulator with leaky integrator modeled) were used to illustrate how leakages in integrators worsen the effect of these imperfections on the output SNDR. It has been observed that the modulators are almost insensitive to the offset voltage of the quantizer, and they are more sensitive to hysteresis than offset. Moreover, it is clearly seen that the less the integrator leakage in the modulator stages, the more the output SNDR. However, this is not a big constraint, and such a quantizer can be easily designed. To be more precise, for the comparison between the behavioral models, derived in this paper, and the circuit-level (transistor-

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TABLE III PARAMETERS

OF THE MODULATOR SHOWN IN CIRCUIT-LEVEL SIMULATION

FIG. 9 USED

FOR

behavior and harmonic distortion. Evaluation and validation of the models were done via behavioral and circuit-level simulations for two second-order modulators using SIMULINK and HSPICE with a generic 0.35- m CMOS technology. The effects of the nonidealities and nonlinearities which were modeled are clearly seen when compared to the ideal and transistor-level simulated modulator. ACKNOWLEDGMENT The authors would like to thank A. Zahabi ([email protected]) for kindly providing the circuit-level modulator netlist used in this paper for verication of the SIMULINK models. REFERENCES
[1] B. E. Boser and B. A. Wooley, The design of sigma-delta modulation analog-to-digital converters, IEEE J. Solid-State Circuits, vol. 22, no. 12, pp. 12981308, Dec. 1988. [2] O. Shoaei, Continuous-time delta-sigma A/D converters for high speed applications, Ph.D. dissertation, Carleton Univ., Ottawa, ON, Canada, 1996. [3] P. Malcovati et al., Behavioral modeling of switched-capacitor sigmadelta modulators, IEEE Trans. Circuits Syst., vol. 50, no. 3, pp. 352364, Mar. 2003. [4] S. R. Northworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters. Piscataway, NJ: IEEE Press, 1997. [5] D. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997. [6] Y. Geerts, M. S. J. Steyaert, and W. Sansen, A high-performance CMOS ADC, IEEE J. Solid-State Circuits, vol. 35, no. multibit 12, pp. 18291840, Dec. 2000. [7] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators. Norwell, MA: Kluwer, 1999. [8] R. del Rio et al., Reliable analysis of settling errors in SC integrators: Application to modulators, Electron. Lett., vol. 36, pp. 503504, Mar. 2000. [9] F. Medeiro et al., Modeling opamp-induced harmonic distortion for switched-capacitor SD modulator design, in IEEE Int. Symp. Circuits Systems, vol. 5, May-Jun. 1994, pp. 445448. [10] H. Zare-Hoseini and I. Kale, On the effects of nite and nonlinear DC-gain on the switched-capacitor delta-sigma modulators, in Proc. IEEE Int. Symp. Circuits Systems, May 2005, pp. 25472550. [11] C. Enz and G. C. Temes, Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization, Proc. IEEE, vol. 48, no. 11, pp. 15841614, Nov. 1996. [12] J. Shieh, M. Patil, and A. J. Sheu, Measurement and analysis of charge injection in MOS analog switches, IEEE J. Solid-State Circuits, vol. SSC-22, no. 4, pp. 277281, Apr. 1987. [13] X. Weize and E. G. Friedman, Clock-feedthrough in CMOS analog transmission gate switches, in Annu. IEEE Int. ASIC/SOC Conf., Sep. 2002, pp. 181185. [14] R. Khoini-Poorfard and D. A. Johns, On the effect of comparator hysteresis in interpolative modulators, in IEEE Int. Symp. Circuit Syst., vol. 2, May 1993, pp. 11481151.

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Fig. 14. Output PSD of the ideal, SIMULINK-modeled, and HSPICE (circuit-level) modulator shown in Fig. 9 with the parameters of Table III.

level) modulator, the second-order modulator shown in Fig. 9 with the parameters listed in Table III for GSM application was performed and simulated in HSPICE using a generic 0.35 m CMOS technology. Fig. 14 shows the output PSD of the SIMULINK modeled and transistor-level modulators. The SNDRs of the transistor-level and the SIMULINK behaviorallevel modulators are 80 and 78.5 dB, respectively. These outputs show a good agreement between the behaviorally modeled and circuit-simulated modulator. VIII. CONCLUSION In this paper, a discussion and precise behavioral model of modulator including noise (switches and op-amps the SC thermal noise), clock jitter, the nite DCG and UGBW of the integrators, slew-limiting, DCG nonlinearities, input parasitic capacitance, hysteresis, switches clock-feedthrough, and charge injection are presented. The effect of DCG nonlinearity in inmodulator modeling attempts undertegrators, which most taken in the past did not consider, has been analyzed, estimated, and modeled in SIMULINK, as well as the other blocks of a modulator. It is shown that neglecting DCG nonlintypical earity leads to a signicant underestimation of the modulators

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Hashem Zare-Hoseini was born in Gonabad, Khorasan, Iran, in 1978. He received the B.Sc. degree from Sharif University, Iran, in 2000 and the M.Sc. degree from the University of Tehran, Iran, in 2003. He is currently pursuing the Ph.D. degree at the University of Westminster, London, U.K. In 2003, he joined the Applied DSP and VLSI Research Group, Department of Electronic Systems, University of Westminster, working on design of continuous-time deltasigma modulators with reduced sensitivity to clock jitter used in interfaces for Electret microphones. His research interests include the design of switched-capacitor/continuous-time deltasigma modulators, analog and mixed-signal integrated circuit design, and high-precision analog circuit design.

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Izzet Kale was born in Cyprus. He received the B.Sc. (honors) degree in electrical and electronic engineering from the Polytechnic of Central London, London, U.K., the M.Sc. degree in the design and manufacture of microelectronic systems from Edinburgh University, Scotland, U.K., and the Ph.D. degree in techniques for reducing digital lter complexity from the University of Westminster, London. He joined the Staff of the University of Westminster (formerly the Polytechnic of Central London) in 1984, where he is currently Professor of applied DSP and VLSI systems. He is also Founder and Director of the Applied DSP and VLSI Research Group at the University of Westminster, where he has undertaken numerous applied research and development projects and contracts for European, U.S., and Japanese corporations. His research and teaching activities include digital and analog signal processing, silicon circuit and system design, digital lter design and implementation, and A/D and D/A sigmadelta converters. He is currently working on efciently implementable, low-power DSP algorithms/architectures and sigmadelta modulator structures for use in the communications and biomedical industries.

Omid Shoaei (M96) received the B.Sc. and M.Sc. degrees from the University of Tehran, Iran, in 1986 and 1989, respectively, and the Ph.D. degree from Carleton University, Ottawa, ON, Canada, in 1996, all in electrical engineering. From 1994 to 1995, he was with BNR/NORTEL, Ottawa, as a Ph.D. intern student, working on highspeed deltasigma modulators. In 1995, he was with Philsar Electronics Inc., Ottawa, working on the design of a bandpass deltasigma data converter. From December 1995 to February 2000, he was a Member of Technical Staff with Bell Labs, Lucent Technologies, Allentown, PA, where he was involved in the design of mixed analog/digital integrated circuits for LAN and fast Ethernet systems. From February 2000 to March 2003, he was with Valence Semiconductor Inc., a design center in Dubai, UAE, as Director of the mixed-signal group, where he worked on pipelined and deltasigma analog-todigital converters. He has been an Associate Professor in the Department of Electrical and Computer Engineering, University of Tehran, since 1999. He has received three U.S. patents and is the author or coauthor of more than 73 international and national journal and conference publications on analog integrated circuits. His research interests include high-speed wide-band as well as high resolution analog-to-digital converters, low-pass and bandpass deltasigma analog-to-digital converters, and new architectures and devices in deep submicrometer CMOS technologies for precision analog circuits.