WEMPEC

PCB Design for EMI/EMC Compliance

Eric Benedict

WEMPEC Seminar 21 July 2000

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References
Unless noted otherwise, everything is from the 1st two references
PCB Design Techniques for EMC and Signal Integrity Short Course, 27-29 June, UWMadison, Mark Montrose, Instructor Printed Circuit Board Design Techniques for EMC Compliance, Mark Montrose, 1996 IEEE Press Electronic Manufacturing, Sheldon Kohen and Michael Rose, 1982 Reston Publishing Company Linear Design Seminar, Analog Devices, October 1987 Electronic Manufacturing Processes, Thomas Landers, William Brown, Earnest Fant, Eric Malstrom and Neil Schmitt, 1994 Prentice Hall Electronics Assembly Handbook, Keith Brindly, 1990 Newnes 1

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Presentation Overview
Denitions PC Board Materials & Construction EMC Fundamentals EMI Suppression Signal Integrity Bypassing & Decoupling Trace Routing ESD Protection

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Denitions
Printed Circuit Board (PCB) Also known as a Printed Wire Board (PWB). A device used to mechanically hold components while providing electrical interconnection via a transmission line. It consists of one or more layers of an insulating material and one or more layers of a conductive foil. land The part of a PCB trace allocated for the connection to a component. via A hole in the PCB with conductive plating on the inside and which connects to one or more condutive layers. Through-hole Technology (THT) Standard leaded components which are mounted by inserting the leads into vias and then lling the vias and surrounding land/pad with solder. Surface-mount Technology (SMT) Leadless components which are soldered directly onto the lands located on the surface of the PCB. 3

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Electromagnetic Compatibility (EMC) The capability of electical and electronic systems, equipment, and devices to operate in their intended electromagnetic environment within a dened margin of safety, and at design levels of performance, without suffering or causing unacceptable degradation as a result of electromagnetic interference. (ANSI C64.14-1992) Electromagnetic Interference (EMI) The process where disruptive electromagnetic energy is transmitted from one electronic device to another via radiated or conducted paths. Radiated Emissions The component of RF (roughly 10kHz to 100GHz) energy transmitted through a medium, usually free space (air), as an electromagnetic eld. Conducted Emissions The component of RF energy transmitted as a propagating wave generally through a wire or interconnect cable. LCI (Line conducted interference) refers to RF energy in the power cord. Susceptibility The measure of a devices ability to be disrupted or damaged by EMI exposure. 4

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Immunity The measure of a devices ability to withstand EMI exposure and still operating at a designated level. Electrostatic Discharge (ESD) A transfer of electric charge between bodies of different electrostatic potential in proximity or through direct contact. Radiated Immunity The ability to withstand electromagnetic energy which is propagated through free space. Conducted Immunity The ablity to withstand electromagnetic energy which is enters through external cables and connections (power or signal). Containment Keeping RF energy inside of an enclosure by providing a metal shield or plastic housing with RF conductive paint. Similarily, external RF energy can be kept out. Suppression Design techniques which reduce or eliminate RF energy from entering or leaving without using a secondard method like a shield or metal chassis. 5

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Board Materials and Construction

The base material or core Copper Layers 2-Layer boards Multilayer boards Types of Traces Transmission Line Calculations

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Core Materials
The most common material is a berglass resin called FR-4. Material CTE Loss Tangent () r ppm/oC FR-4 glass 4.1-4.8 +250 0.02-0.03 GTEK 3.5-4.3 +250 0.012 woven glass/ceramic loaded 3.38 +40 0.0027 PTFE/ceramic (Teon) 2.94 0 0.0012 Cost per sq. ft. $2.5 $3.5 $9.50 $100.00

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Copper Layers
The conductive layer of a PCB is usually a sheet of copper which has been etched to form the circuit traces. The copper sheets nominal thickness is designated by the weight of 1 square foot of copper of the nominal thickness. Copper Thicknesses Weight (oz) Thickness (in) Weight (oz) Thickness (in) 1/8 0.00017 4 0.0056 1/4 0.00035 5 0.0070 1/2 0.0007 6 0.0084 1 0.0014 7 0.0098 2 0.0028 10 0.0140 3 0.0042 14 0.0196
Electronic

Manufacturing

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2-layer Boards
Route power traces radially from the power supply Route power and ground traces parallel to each other Signal ow should parallel the ground paths. Dont create current loops by tieing different branches together.
Decoupling Capacitors

Ground trace

Power Connector

Power trace

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Multilayer Boards
Multilayer boards are formed by etching several double-sided boards and then gluing them together with a material called prepreg. The thickness and material for both the core and the prepreg can be specied and controlled. Vias are holes which are electroplated after drilling and connect the different layers.
Layer 1 2 3

Solder Mask Core Prepreg Core Solder Mask

Vias

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Types of Traces
There are two basic types of trace topology: Microstrip and Stripline. Microstrip
h

Dielectric, r Ground Plane

Ground Plane

h1

Dielectric, r

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Greatly reduced RF emissions, but slower signals

h2

Stripline

Power Plane W t B

Faster signals possible due to lower capacitive coupling, but greater radiated RF

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Impedance & Delay Calculations

Microstrip
Z0 =

87
r + 1.414

(ps/in) tpd = 85 0.475 r + 0.67 0.67( r + 1.414) (pF/in) C0 = 5.98h ln 0.8W +t 5.98H 2 L0 = Z0 C0 = 5071.23 ln 0.8W + t
see

ln

5.98h 0.8W + t

(pH/in)

also Lines and Electromagnetic Fields for Engineers in the WEMPEC Library

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Stripline
Z0 =

tpd = 85 C0 =

4h 60 ln t 0.67W 0.8 + W r
r

(ps/in)

1.41 r

3.81h ln 0.8W +t 2 (pH/in) L0 = Z0 C0

(pF/in)

see

also Lines and Electromagnetic Fields for Engineers in the WEMPEC Library

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EMC Fundamentals
The coupling path is frequency dependent High frequencies are radiated Low frequencies are conducted The boundary is typically about 30 MHz There are 5 aspects to EMC when nding the problem Frequency - Where in the spectrum is the problem observed? Amplitude - How strong is the energy source? Time - Is it continuous or intermittent with operation? Impedance - What is the Z of the source and receiver? Dimensions - What are the physical dimensions of the device which will allow emissions? (RF currents will leave through openings which are fractions of a wavelength!) 14

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How PCBs Radiate RF Energy

Digital signals with fast rise/fall times contain very high frequency compo1 nents even for low clock frequencies! Fmax = tr The RF currents from the switching choose the low impedance path The Z0 of air is about 377. RF Discontinuities in the RF return path ZP CB 377 RF current leaves the board in favor of the air = EMI

Low Frequency Equivalent Circuit

High Frequency Equivalent Circuit

long return path e.g. slot in gnd plane

Zair

Zair

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Radiated Emissions
Radiated Energy

return current Loop Area

signal current

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EMI Suppresion
Image Planes The 20-H Rule System Level Grounding Partitioning

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Image Planes
An image plane is a layer of copper (either a voltage or a ground plane) which physically adjacent to the signal routing plane. The image plane provides a low impedance path for the RF currents and reduces the EMI emissions since the RF currents use the plane instead of the air.

Signal Path

RF Return Path

DC Return Path

Signal Plane Image Plane

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Image Plane Violations

Routing traces in the image plane will create slots in the RF return path and create a large loop area and potential EMI!!

RF Return Path

Signal Path

Image Plane Traces Signal Plane Image Plane

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The 20-H Rule

RF currents fringing between the power and ground planes at the edge of the board can result in RF emissions. Reducing the size of the power plane with respect to the ground plane will reduce these emissions. This increases the intrinsic self-resonant frequency of the PCB. The ground plane should exceed the power plane by 20H where H is the total thickness between the power and ground planes 20-H provides for approximately a 70% reduction of the fringing ux and changing to 100-H will provide about a 98% reduction.

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The 20-H Rule in Action

20H

power pin in void area

Power Plane

20H Signal plane Power plane Ground plane Signal Plane

Ground Plane

20H

Board top view

Board side view

If a power pin needs to be located near the edge of the board, then it is ok for the plane to extend into the 20-H void to surround the pin. 21

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System Level Grounding

There are three main system grounding methods Single-Point Grounding Either Series or Parallel Best for frequencies below 1 MHz Has the largest amount of ground loop currents Multi-point Grounding Preferred for frequencies above 1 MHz. Minimizes loop currents and ground impedance of planes. Lead Lengths must be kept extremely short Provides for maximum EMI suppression at the PCB level 22

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Hybrid A mixture of both Single-Point and Multi-Point Grounding in the same system. Ground loops cause RF energy to be radiated when high inductance returns are provided. Note: Do not count on mounting screws to provide low inductance connections. They are highly inductive and can act as helical antennae at high frequencies (100 MHz-1 GHz)!! (Use conductive gaskets in addition to the screws.) In a Multi-point ground system, the distance between the screws should not exceed /20 of the highest edge rate on the PCB.

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Partitioning
Partioning consists of breaking a board up into functional areas with respect to the bandwidth of the functional block. Grounding connections are made around the perimeter of each functional block using spring nger, screws, gaskets, etc, provided that the method has a sufciently low inductance between the ground plane and the chassis ground.

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Signal Integrity
Ringing and Reection Cross-Talk Power and Ground Bounce

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Ringing and Reection

Transmission line properties which occur between the source and load. Possible causes: Changes in trace width Improperly matched termination networks Lack of terminations T-stubs, branched or bifurcated traces Varying loads and logic families Large power plane discontinuities Connectior transitions Changes in trace impedance 26

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Signal Distortion

Ringing means reections (due to excessive inductance)

Rounding is due to excessive capacitance or trace resistance

Ringing is minimized by proper terminations (e.g. series R) Rounding means the net is overdamped. Dont forget about the shunt capacitance of the trace as well as the load capacitance. 27

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Cross-Talk (aka Board-level EMI!)

Lm a
  

Victim Trace

Vs

Z vs

C vg

Z vl

ground plane

cross-talk requires a 3-wire circuit! Terminating resistors with a common pin susceptible!

C sv

Source Trace

C sv

Z ss

Lm

C sv Z sl

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Preventing Cross-Talk
First, note the following observations: Decreasing the trace seperation increases the mutual capacitance Cm and the cross-talk. With parallel traces, longer parallel lengths increase the mutual inductance Lm and the cross-talk. Decreasing the rise time of the signal, increases the cross-talk. Some Solutions are: 1. Group and locate logic devices according to functionality. 2. Minimize routed distance between components 3. Minimize parallel routed trace lengths 29

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4. Locate components away from I/O interconnects and other areas susceptible to data corruption. 5. Provide proper terminations on impedance controlled traces or routed traces rich in harmonic energy 6. Avoid routing traces parallel to each other. Provide sufcient seperation between traces to minimize inductive coupling (The 3 W Rule) or use guard traces. 7. Route adjacent signal layers orthogonal to reduce capacitive coupling between the layers. 8. Reduce signal-to-ground reference distance seperation 9. Reduce trace impedance and/or signal drive level 10. Isolate signal layers which must be routed in the same axis with a solid planar structure. 30

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The 3-W

Rule

This rule for trace seperation will reduce the cross-talk ux by approximately 70%. (For a 98% reduction, change the 3 to 10.) The distance of seperation between traces must be three times the width of the traces, measured center-line to center-line.
Via

C L

C L

C L

Note that the traces near the edge of the plane need to be > 1W from the edge!
First

described by W. Michael King

>2W

>W

W W W W W W

W W W

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For Differential Pair Traces

C L

Other Traces Differential Pair

W W W

Vertical Axis Differential Pair

W W W W W >2W >2W Ground Plane

Horizontal Axis Differential Pair

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Guard/Shunt Traces
Guard traces surround the high-threat traces (clocks, periodic signals, differential pairs, etc.) and are connected to the ground plane. They are very useful in 2-layer boards. The guard trace should be smallest, tolerable manufacturable spacing from the signal. The guard trace is connected to ground. If a ground plane is available, make ground connections no farther than /20 apart. Shunt traces are traces located immediately above a high-threat trace and follow the trace along the entire route. They are best used in multi-layer (6 or more) boards.

1 10fmax

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Guard & Shunt Trace Examples

Reference Plane

Reference Plane

/20

Guard Trace

Shunt Trace

Guard Traces

Signal Traces

Shunt Trace (3W wide) Signal Trace

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Power and Ground Bounce

Ground bounce is caused by the simultaneous switching of drivers in an IC package and may cause functionality as well as EMI concerns. Ground bounce presents a situation where the ground reference system is not at a constant 0 V reference value. Be sure to provide a seperate ground connection for each ground pin directly to the ground plane. Connecting two ground terminals together with a trace to a single via defeats the purpose of having independent ground leads on the device package! Also, choose component packaging carefully: use devices with a ground reference in the center of the device to reduce the Lgnd (4nH vs 15nH). Surface mount devices are preferred over through-hole packages for this reason. 35

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Bypassing and Decoupling

Capacitor Usage and Resonance Parallel Capactitors Placement

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Types of capacitor usage

There are three primary uses for capacitors: 1. Bulk Used to maintain constant DC voltage and currents when all signal pins switch. Also prevents power drop out due to dI/dt current surges from the components. 2. Bypassing Removes unwanted common-mode RF noise from components or cables by placing an AC-short to ground. This keeps the unwanted energy from entering a protected area as well as limiting the bandwidth. Bypassing is also used to divert RF energy from one area to another. 3. Decoupling Removes RF energy injected into the power planes from high frequency components consuming power at the devices switching speed. They also provide a small amount of energy to function as localized bulk capacitors. 37

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Resonance Effects
Remember, the capacitors really have an ESL and ESR. Through-hole: ESL35nH and ESR50m Surface Mount: ESL1nH and ESR5m
10 10 10 10 10 10 10
4

Resonance of ThroughHole Capacitors 10 10 100 pF 10 10 10 10 10

Resonance of SMT Capacitors

100 pF
2

0.001 F |Z| ( ) 0.01 F 0.1 F

0.001 F
1

|Z| ( )

0.01 F 0.1 F

10

10

10 Frequency (MHz)

10

10

10

10 Frequency (MHz)

10

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Parallel Capacitors
Remember that the power planes form a capacitor.
10 10 10 10 10 10 10
4

Resonance of ThroughHole Capacitors + Plane

AntiResonance! 5 in @ 100pf/in
2 2

|Z| ( )

0.1 F

10

10

10 Frequency (MHz)

10

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Tips on Paralleling Capacitors

Parallel capacitors of the same value will increase the net capacitance and reduce the ESL and ESR. The reduction of the ESL and ESR is the most important property. Improvements of 6dB have been observed (replacing one capacitor with multiple smaller ones). Be careful to remember that the values will be different and anti-resonance will occur. Choose values such that the anti-resonance will not occur at a harmonic of a generated signal (either a switching or transition frequency). See Printed Circuit Board Design Techniques for EMC Compliance, pg. 55 for capacitor value design procedure. (Giris book)

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Capacitor Placement
Key idea is to reduce path inductance location location location the location of the components is limited by mechanical contstraints SMT parts can be closer than THT parts trace inductance will be 3-10x larger than plane inductance each via adds 1-3 nH of inductance

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Trace Routing
Keep signal traces AWAY from high frequency devices, e.g. clocks. Do NOT use auto routers since they typically choose the worst possible layout for EMI/EMC concerns... Remember the 3-W rule Remember the 20-H rule Use isolation (moats) in conjunction with the partitioning

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Isolation/Moating
Intentionally introducing breaks in the power and/or ground planes.

WHY???
Consider the following:

power connector

power connector + V gnd

Power Devices

Power Devices

Linear Design Seminar

power

+ V gnd

Analog Circuitry

Moat (notch in plane)

Analog Circuitry

power

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Moat Violations
Moat violations will virtually always generate lots of EMI, even if the violating trace is quiet.
Moat Violation

Moat (no plane) Moat Bridge

Correct moat usage

Signal Returns

Ground plane

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Bridging Moats
Make the bridge wide enough for just the required traces (observing 3W) Use a ferrite to provide ltering in the power trace, but do not put one in the ground traces. If a violation must occur, place a bypass capacitor across the moat as close to the violation as possible. (capacitor is connected ground to ground). choose for proper ltering bandwith (RF return current) Peak surge voltage capability for ESD protection

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ESD Protection
Provide good shielding with the chassis and connectors Provide good grounding connections; wire braid with a 5:1 width:height aspect ratio is good (Solder wick works nicely!). Avoid pigtail wiring harnesses. (they make good RF antennae!) Filling un-used signal plane with a ground ll helps prevent ESD, not EMI. Guard Bands

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Guard Bands
Different from guard, shunt or groung traces Prevents ESD damage from handling of PCB A NON-continuous trace around the edge of the PCB on both the top and bottom layers (introduce some moats to prevent ground loops!). Should not be covered with the soldermask and should frequently be connected to the ground reference with vias.

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A Guard Band
Exposed Guard Trace

moats

Ground Vias

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