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Module FIR

This document describes a finite impulse response (FIR) Gaussian lowpass filter module and a generic FIR filter generator module. The FIR lowpass filter module is an 8th order Gaussian filter that takes in input data and clock signals and outputs filtered data. The generic FIR filter generator module uses parameterized values to generate a FIR filter with a configurable length, input/output bit widths, and multiplier pipeline stages. It multiplies input data by filter coefficients, sums the products, and outputs the filtered results.

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ashik_na
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214 views

Module FIR

This document describes a finite impulse response (FIR) Gaussian lowpass filter module and a generic FIR filter generator module. The FIR lowpass filter module is an 8th order Gaussian filter that takes in input data and clock signals and outputs filtered data. The generic FIR filter generator module uses parameterized values to generate a FIR filter with a configurable length, input/output bit widths, and multiplier pipeline stages. It multiplies input data by filter coefficients, sums the products, and outputs the filtered results.

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ashik_na
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as DOC, PDF, TXT or read online on Scribd
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module FIR_Gaussian_Lowpass (Data_out, Data_in, clock, reset); // Eighth-order, Gaussian Lowpass FIR parameter order = 8; parameter word_size_in = 8; parameter

word_size_out = 2*word_size_in + 2; output [word_size_out -1: 0] Data_out; input [word_size_in-1: 0] Data_in; input clock, reset; parameter b0 = 8'd7; // Filter coefficients parameter b1 = 8'd17; parameter b2 = 8'd32; parameter b3 = 8'd46; parameter b4 = 8'd52; parameter b5 = 8'd46; parameter b6 = 8'd32; parameter b7 = 8'd17; parameter b8 = 8'd7; reg [word_size_in-1: 0] Samples [1: order]; integer assign Data_out = + + + + + + + b2 b3 b4 b5 b6 b7 b8 * * * * * * * Samples[2] Samples[3] Samples[4] Samples[5] Samples[6] Samples[7] Samples[8]; k; b0 * Data_in + b1 * Samples[1]

always @ (posedge clock) if (reset == 1) begin for (k = 1; k = order; k = k+1) Samples [k] = 0; end else begin Samples [1] = Data_in; for (k = 2; k = order; k = k+1) Samples [k] = Samples[k-1]; end endmodule //********************************************************* // IEEE STD 1364-1995 Verilog file: fir_gen.v // Author-EMAIL: [email protected] //********************************************************* // This is a generic FIR filter generator // It uses W1 bit data/coefficients bits module fir_gen (clk, Load_x, x_in, c_in, y_out); parameter W1 = 9, // Input bit width W2 = 18, // Multiplier bit width 2*W1 W3 = 19, // Adder width = W2+log2(L)-1 W4 = 11, // Output bit width L = 4, // Filter length Mpipe = 3; // Pipeline steps of multiplier input clk, Load_x; // std_logic input [W1-1:0] x_in, c_in; // Inputs output [W3-1:0] y_out; // Results

reg [W1-1:0] x; wire [W3-1:0] y; // 2D array types i.e. memories not supported by MaxPlusII // in Verilog, use therefore single vectors reg [W1-1:0] c0, c1, c2, c3; // Coefficient array wire [W2-1:0] p0, p1, p2, p3; // Product array reg [W3-1:0] a0, a1, a2, a3; // Adder array wire wire [W2-1:0] sum; clken, aclr; // Auxilary signals

assign sum=0; assign aclr=0; // Default for mult assign clken=0; //----> Load Data or Coefficient always @(posedge clk) begin: Load if (! Load_x) begin c3 <= c_in; // Store coefficient in register c2 <= c3; // Coefficients shift one c1 <= c2; c0 <= c1; end else begin x <= x_in; // Get one data sample at a time end end //----> Compute sum-of-products always @(posedge clk) begin: SOP // Compute the transposed filter additions a0 <= {p0[W2-1], p0} + a1; a1 <= {p1[W2-1], p1} + a2; a2 <= {p2[W2-1], p2} + a3; a3 <= {p3[W2-1], p3}; // First TAP has only a register end assign y = a0; // Instantiate L pipelined multiplier lpm_mult #("lpm_mult",W1,W1,W2,W2,"SIGNED",Mpipe) mul_0 // Multiply p0 (.clock(clk), .dataa(x), .datab(c0), .result(p0), .sum(sum), .clken(clken), .aclr(aclr)); // Unused ports // defparam mul_0.lpm_widtha = W1; // defparam mul_0.lpm_widthb = W1; // defparam mul_0.lpm_widthp = W2; // defparam mul_0.lpm_widths = W2; // defparam mul_0.lpm_pipeline = Mpipe; // defparam mul_0.lpm_representation = "SIGNED"; lpm_mult #("lpm_mult",W1,W1,W2,W2,"SIGNED",Mpipe) mul_1 // Multiply p1 // // (.clock(clk), .dataa(x), .datab(c1), .result(p1), .sum(sum), .clken(clken), .aclr(aclr)); // Unused ports defparam mul_1.lpm_widtha = W1; defparam mul_1.lpm_widthb = W1; x*c0 =

x*c1 =

// // // // p2 // // // // // // p3 // // // // // //

defparam defparam defparam defparam

mul_1.lpm_widthp = W2; mul_1.lpm_widths = W2; mul_1.lpm_pipeline = Mpipe; mul_1.lpm_representation = "SIGNED"; x*c2 =

lpm_mult #("lpm_mult",W1,W1,W2,W2,"SIGNED",Mpipe) mul_2 // Multiply (.clock(clk), .dataa(x), .datab(c2), .result(p2), .sum(sum), .clken(clken), .aclr(aclr)); // Unused ports defparam mul_2.lpm_widtha = W1; defparam mul_2.lpm_widthb = W1; defparam mul_2.lpm_widthp = W2; defparam mul_2.lpm_widths = W2; defparam mul_2.lpm_pipeline = Mpipe; defparam mul_2.lpm_representation = "SIGNED"; lpm_mult #("lpm_mult",W1,W1,W2,W2,"SIGNED",Mpipe) mul_3 // Multiply (.clock(clk), .dataa(x), .datab(c3), .result(p3), .sum(sum), .clken(clken), .aclr(aclr)); // Unused ports defparam mul_3.lpm_widtha = W1; defparam mul_3.lpm_widthb = W1; defparam mul_3.lpm_widthp = W2; defparam mul_3.lpm_widths = W2; defparam mul_3.lpm_pipeline = Mpipe; defparam mul_3.lpm_representation = "SIGNED"; assign y_out = y[W3-1:W3-W4]; endmodule

x*c3 =

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