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Newvhdl Syllabus (It&Cse)

This document outlines a course on VHDL programming with the following key points: The course aims to discuss the syntax of VHDL to model digital systems. It is divided into 5 modules covering VHDL basics, language elements, behavioral, dataflow and structural modeling, components like generics and FSMs, and design examples. Student performance will be evaluated through class tests, assignments, seminars and a final exam. The course references several texts on VHDL and digital design.

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Mude Kishore Naik
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119 views2 pages

Newvhdl Syllabus (It&Cse)

This document outlines a course on VHDL programming with the following key points: The course aims to discuss the syntax of VHDL to model digital systems. It is divided into 5 modules covering VHDL basics, language elements, behavioral, dataflow and structural modeling, components like generics and FSMs, and design examples. Student performance will be evaluated through class tests, assignments, seminars and a final exam. The course references several texts on VHDL and digital design.

Uploaded by

Mude Kishore Naik
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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VHDL PROGRAMMING

Course Code: BTC 501 Credit Units: 03

Course Objective:
VHDL is commonly used as a design-entry language for field-programmable gate arrays and application-
specific integrated circuits in electronic design automation of digital circuits. The course aims to discuss the
syntax of the language to model a digital system.

Course Contents:
Module I (Introduction to VHDL)
VHDL basics, Benefits of VHDL, VHDL levels of abstraction, design flow, design units (Library, Entity,
Architecture, Configuration Declaration, Package declaration, and Package body)

Module II (Language Elements)


Data Types; Pre-Defined Data Types, User-Defined Data Types, Subtypes, Arrays, Port Array, Records,
Signed and Unsigned Data Types, Data Conversion, Operators, Data Objects, Identifiers.

Module III: (Types of Modeling)


Behavioral Modeling – Variable Assignment & Signal Assignments Statements, Other statements, Delay
Models
Dataflow Modeling – Concurrent & sequential Statements, Multiple Drivers, Statements with Delay issues.
Structural Modeling – Component declaration, Component instantiation, signal values.

Module IV (Other Components of VHDL)


Generics and Configurations, Basics of Subprograms, Overloading, Packages and Libraries, Introduction to
Modelling Moore FSM, Mealy FSM,

Module V (VHDL Designs )


Design of a Binary Multiplier, Design of a Serial Adder, Standard combinational modules, Overview of
PAL, PLA, FPGA, CPLD.

Examination Scheme:

Components A CT S/V/Q HA EE
Weightage (%) 5 10 8 7 70
CT: Class Test, HA: Home Assignment, S/V/Q: Seminar/Viva/Quiz, EE: End Semester Examination; Att:
Attendance

Text & References:


Text:
 J. Bhaskar, “A VHDL Primer”, Addison Wesley, 1999.
 Volnei A. Padroni, “Circuit Design with VHDL.”
 M. Ercegovac, T. Lang and L.J. Moreno, ”Introduction to Digital Systems”, Wiley,2000
 C. H. Roth, “Digital System Design using VHDL”, Jaico Publishing, 2001

References:
 VHDL Programming by Examples by Douglas L. Perry, TMH, 2000
 Hardware Description Languages by Sumit Ghose, PHI, 2000
 The Designer Guide to VHDL by P.J. Ashendern; Morgan Kaufmann Pub. 2000
 Digital System Design with VHDL by Mark Zwolinski; Prentice Hall Pub. 1999
 Designing with FPGA & CPLDs by Zeidman; CMP Pub. 1999
 HDL Chip Design by Douglas J. Smith; Doone Pub. 2001

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