Lcd+Profilo Telra+PT1000

26”-32” LCD-TV
PT1000
26'' - 32 '' LCD-TV PT1000 Service Manual
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CONTENTS
1. Assembling/Disassembling Procedure .................... 04
2. Safety Instructions and Warnings .................... 09
3. Specifications .................... 12
4. Block Diagrams and Connections .................... 17
5. Menu Structure .................... 30
6. Circuit Diagrams and Printed Circuit Board Layouts .................... 34
7. Troubleshooting .................... 52
8. Data Sheets
TECH2949PS40A(D) .................... 53
CAT24WC01/02/04/08/16
1K/2K/8K/16K-Bit Serial EEPROM .................... 55
74HC4066; 74HCT4066
Quad bilateral switches .................... 56
CD4069UBC
Inverter Circuits .................... 58
EDD1232AAFA (4M wordsx32 bits)

128M bits DDR SDRAM .................... 59
EN29LV040
4 Megabit (512k x 8-bit) Uniform Sector,
CMOS 3.0 Volt-only Flash Memory .................... 61
FDC6326L
Integrated Load Switch .................... 63
IL1117A-x
1.0A Low Dropout Positive Voltage Regulator ..................... 64
MST6181LDA
SXGA/WXGA LCD Multi-Function Monitor
Controller with Dual LVDS transmitter
Preliminary Data Sheet Version 0.2 ..................... 66
MTV512M
8051 Embedded Monitor Controller with
64K Flash ROM ..................... 76
RC1117
1A Adjustable/Fixed Low Dropout
Linear Regulator ..................... 79
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26'' - 32'' LCD-TV PT1000 Service Manual
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TPA3004D2
12-W STEREO CLASS-D AUDIO POWER
AMPLIFER WITH DC VOLUME CONTROL .................... 81
TPA6110A2
150-m W STEREO AUDIO POWER
AMPLIFIER .................... 85
TW9906
3x10-bit Multi-Standard Comb Filter Video
decoder with YcbCr Component Input .................... 87
VCT 49xyl, VCT 48xyl .................... 89
WM8725
99dB Stereo DAC ....................101
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1. Assembling/ Disassembling Procedure
Please follow the assembly instructions explained below;

NOTE: Make sure that the power cord is disconnected from the outlet.
• Pay special attention not to break or damage the parts.
• When removing each board, remove the connectors as required.
• Taking notes of the connecting points (connector numbers) makes service
procedure manageable.
• Make sure that there is no bent or stain on the connectors before inserting, and
firmly insert the connectors.
• Be sure that all cables are free. If necessary fix the cables firmly to avoid any kind
of squeezing while placing the boards back.
• If possible before starting every each stage of disassembly take a photo.
• Keep all screws and other components in safety place.
• Do not store components in a moist , dusty and dirty place.
Disassambly ordering:
1-) Remove Back Cover

2-) Remove Stand Group
3-) Remove DVD Holder and DVD (or wireless holder and PCB)
4-) Remove Switch Box
5-) Remove Power Board and Main Board
6-) Remove Board Base Metal (or plastic)
7-) Remove Power Cable
8-) Remove LCD Panel keepers (plastics or metals)
9-) Remove LCD panel
10-) Remove all cables and connectors from Side AV.
11-) Remove Side AV holder and PCB
12-) Remove Multibutton holder and PCB from Cabinet
13-) Remove Multibutton PCB and Multibuttons from Multibutton_Holder
14-) Remove Tweeters and Speakers from Cabinet
15-) Remove Standby&Infrared PCB from its holder
16-) Remove Acrylic standby button, and LED holder from Cabinet.
17-) Remove Eject button and PCB
Assembly ordering:
The assembly ordering is exactly reverse of disassembly ordering. In any doubt, look
photos, which you have taken before, and check, exploded view.
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EXPLODED WIEW PART LIST
NO. DESCRIPTION
1. FRONT CABINET
2. LCD PANEL
3. LCD PANEL HOLDER
4. LCD PANEL HOLDER SCREW
5. MULTIBUTTON
6. MULTIBUTTON PCB
7. MULTIBUTTON PCB SCREW
8. SIDE AV HOLDER
9. SIDE AV HOLDER SCREW
10. SIDE AV PCB
11. SIDE AV PCB SCREW
12. REFLECTOR
13. INFRA LED PCB
14. INFRA LED PCB SCREW
15. SPEAKER
16. SPEAKER SCREW
17. EJECT BUTTON
18. EJECT BUTTON PCB
19. EJECT BUTTON PCB SCREW
20. STAND HOLDER SHEET
21. STAND HOLDER SHEET SCREW
22. COVER PART
23. COVER PART SCREW
24. MMC CARD HOLDER
25. MMC CARD HOLDER SCREW
26. MMC CARD PCB
27. MMC CARD PCB SCREW
28. MAIN BOARD HOLDER
29. MAIN BOARD HOLDER SCREW
30. MAIN BOARD AVISOL
31. MAIN BOARD SCREW
32. POWER BOARD HOLDER
33. POWER BOARD HOLDER SCREW
34. POWER BOARD
35. DVD LOADER HOLDER
36. DVD LOADER HOLDER SCREW
37. DVD LOADER
38. VESA STANDARD SHEET
39. VESA STANDARD SHEET SCREW
40. PLASTIC STAND
41. PLASTIC STAND SHEET
42. PLASTIC STAND SHEET SCREW
43. PLASTIC STAND BOTTOM SHEET
44. PLASTIC STAND BOTTOM SHEET SCREW
45. BACKCOVER DVD
46. BACKCOVER DVD SCREW
EXPLODED WIEW PART
LIST
NO. DESCRIPTION
1. FRONT CABINET
2. FRAME CMO/FRAME OTHER
3. PANEL CMO/SM/AUO/LG
4. BOARD HOLDER (METAL)
5. PANEL HOLDER (TOP-BOTTOM)
6. PANEL HOLDER (SIDE)
7. EJECT PCB
8. EJECT BUTTON
9. VESA METAL 200X200
10. BACK COVER
11. PHILIPS SPEAKER
12. SPEAKER RUBBER
13. SIDE AV
14. MULTIBUTTON
15. MULTIBUTTON PCB
16. CONTROL PCB
17. CMO PANEL FIXING (LEFT)
18. CMO PANEL FIXING (RIGHT)
19. CASON SLOT DVD
20. DVD HOLDER
21. POWER BOARD
22. AVISOL MAIN BOARD
23. CABLE STOPPER
24. MAINS CORD
25. PANEL HOLDER (LEFT)
26. PANEL HOLDER (RIGHT)
27. BOTTOM COVER
28. HOLDER FIXING METAL
29. STAND
30. HOLDER METAL
31. STAND SHIELD
32. FOOT RUBBERS
33. LABEL
34. ON-OFF SWITCH
35. LG FIXING (BOTTOM)
36. LG FIXING (TOP)
37. LG HOLDER (BOTTOM)
38. LG HOLDER (TOP)
NO. DESCRIPTION
1. FRONT CABINET V01 INSERT
2. LCD PANEL (LG / AUO / SAMSUNG)
3. BACK COVER (DVD INSERT)
4. PANEL COVER METAL
5. POWER BOARD
6. EJECT BUTTON HOLDER

7. EJECT BUTTON
8. EJECT PCB
9. DVD LOADER
10. PANEL FIXING PLASTICS
11. DVD HOLDER
12. MAIN BOARD
13. SWITCH COVER
14. AV PCB(20" COLORFUL)
15. I/O SWITCH
7
16. MULTI BUTTON
17. MULTI BUTTON PCB
18. AV PCB / MULTI BUTTON PCB HOLDER
19. SPEAKER VIBRATION RUBBER
20. SPEAKER VIBRATION PLASTIC
21. SPEAKER
22. STAND-BY PCB
23. MCR HOLDER
24. MCR PCB
25. REFLECTOR
26. STAND-BY REFLECTOR
27. STAND-BY BUTTON
28. METAL FOOD
29. FRONT SHUTTER
30. PLASTIC STAND
31. STAND SHIELD
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NO. DESCRIPTION
1. FRONT CABINET V02 INSERT
2. LCD PANEL (LG / AUO / SAMSUNG)
3. BACK COVER V02 (DVD INSERT)
4. PANEL COVER METAL
5. POWER BOARD
6. EJECT BUTTON HOLDER
7. EJECT BUTTON
8. EJECT PCB
9. DVD LOADER
10. PANEL FIXING PLASTICS
11. DVD HOLDER
12. MAIN BOARD
13 . SWITCH COVER
14. AV PCB(20" COLORFUL)
15. I/O SWITCH
8
16. MULTI BUTTON V02
17. MULTI BUTTON PCB V02
18. SIDEAV PCB HOLDER V02
19. SPEAKER VIBRATION RUBBER
20. SPEAKER VIBRATION PLASTIC
21. SPEAKER
22. STAND-BY PCB V02
23. MCR HOLDER
24. MCR PCB
25. REFLECTOR V02
26. STAND-BY REFLECTOR V02
27. MENU BUTTON
28. METAL FOOD V02
29. FRONT SHUTTER V02
30. PLASTIC STAND V02
31. STAND SHIELD V02
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2. SAFETY INSTRUCTIONS AND PRECAUTIONS

1. Use only the original spare parts with the same specifications for replacement.
2. Only the original fuse value should be used.
3. Safety components should be replaced by components identical to the original
ones.
4. Main leads and connecting leads should be checked for external damage before
connection. Insulation must be checked.
5. Parts contributing to the safety of the product must not be damaged or obviously
unsuitable. This is valid especially for insulators and insulating parts.
6. Thermally loaded solder pads are to be sucked off and re-soldered.
7. Ensure that the ventilation slots are not obstructed.
8. Servicing should not be attempted by anyone who is not thoroughly familiar with
precautions necessary when working on high voltage equipment. Perfectly
discharge the high potential of the picture tube before handling it. The picture
tube is highly evacuated and if broken. Glass fragments will be violently expelled.
Always discharge the picture tube anode to the receiver chassis to keep of the
shock hazard before removing the anode cap.
9. Keep wire away from the high voltage or high temperature components.
10. When replacing a wattage resistor, keep the resistor 10mm away from the circuit
board.
HANDLING THE MOS CHIP COMPONENTS
MOS circuit requires special attention with regard to static charges. Static charges
may occur with any highly insulated plastics and can be transferred to persons
wearing clothes and shoes made of synthetic materials. Protective circuits on the
inputs and outputs of MOS circuits give protection to a limited extend only due to
time of reaction.
Please observe the following instructions to protect the components against ESD.
1. Keep MOS components in conductive package until they are used. Most
components must never be stored in styropor materials or plastic magazines.
2. Personnel must not touch the MOS components to avoid electrostatic
discharging.
3. Hold the component by the body touching the terminals.
4. Use only grounded instruments for testing and processing purposes.
5. Remove or connect MOS Ics when operating voltage is disconnected.
6. Personnel in charge must make sure that they are connected with the same
potential as the mass of the set by a wristband with resistance.
2.1. Precautions
Please pay attention to the followings when you use this TFT LCD module.
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2.1.1. Mounting Precautions

(1) You must mount a module using holes arranged in four corners or four sides.
(2) You should consider the mounting structure so that uneven force (ex. Twisted
stress) is not applied to the module. And the case on which a module is
mounted should have sufficient strength so that external force is not
transmitted directly to the module.
(3) Please attach the surface transparent protective plate to the surface in order
to protect the polarizer. Transparent protective plate should have sufficient
strength in order to the resist external force.
(4) You should adopt radiation structure to satisfy the temperature
specification.
(5) Acetic acid type and chlorine type materials for the cover case are not
desirable because the former generates corrosive gas of attacking the
polarizer at high temperature and the latter causes circuit break by electro-
chemical reaction.
(6) Do not touch, push or rub the exposed polarizer with glass, tweezers or
anything harder than HB pencil lead. And please do not rub with dust clothes
with chemical treatment. Do not touch the surface of polarizer for bare hand
or greasy cloth. (Some cosmetics are detrimental to the polarizer.)
(7) When the surface becomes dusty, please wipe gently with absorbent cotton or
other soft materials like chamois soaks with petroleum benzine. Normal-
hexane is recommended for cleaning the adhesives used to attach front / rear
polarizers. Do not use acetone, toluene and alcohol because they cause
chemical damage to the polarizer.
(8) Wipe off saliva or water drops as soon as possible. Their long time contact
with polarizer causes deformations and color fading.
(9) Do not open the case because inside circuits do not have sufficient strength.
2.1.2 Operating Precautions

(1) The spike noise causes the mis-operation of circuits. It should be lower than
following voltage: V=±200mV(Over and under shoot voltage)
(2) Response time depends on the temperature. (In lower temperature, it becomes
longer.)
(3) Brightness depends on the temperature. (In lower temperature, it becomes
lower.) And in lower temperature, response time (required time that brightness is
stable after turned on) becomes longer.
(4) Be careful for condensation at sudden temperature change. Condensation makes
damage to polarizer or electrical contacted parts. And after fading condensation,
smear or spot will occur.
(5) When fixed patterns are displayed for a long time, remnant image is likely
to occur.
(6) Module has high frequency circuits. Sufficient suppression to the electromagnetic
interference shall be done by system manufacturers. Grounding and shielding
methods may be important to minimize the interference.
(7) Please do not give any mechanical and/or acoustical impact to LCM. Otherwise,
LCM can’t be operated its full characteristics perfectly.
(8)A screw, which is fastened up the steels, should be a machine screw. (if not, it
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causes metallic foreign material and deal LCM a fatal blow)

(9) Please do not set LCD on its edge.
2.1.3. Electrostatic Discharge Control

Since a module is composed of electronic circuits, it is not strong to electrostatic
discharge. Make certain that treatment persons are connected to ground through
wrist band etc. And don’t touch interface pin directly.
2.1.4. Precautions for Strong Light Exposure

Strong light exposure causes degradation of polarizer and color filter.
2.1.5. Storage
When storing modules as spares for a long time, the following precautions are
necessary.
(1) Store them in a dark place. Do not expose the module to sunlight or fluorescent
light. Keep the temperature between 5°C and 35°C at normal humidity.
(2) The polarizer surface should not come in contact with any other object. It is
recommended that they be stored in the container in which they were shipped.
2.1.6. Handling Precautions for Protection Film

(1) The protection film is attached to the bezel with a small masking tape. When the
protection film is peeled off, static electricity is generated between the film
and polarizer. This should be peeled off slowly and carefully by people who
are electrically grounded and with well ion-blown equipment or in such a
condition, etc.
(2) When the module with protection film attached is stored for a long time,
sometimes there remains a very small amount of glue still on the bezel after
the protection film is peeled off.
(3) You can remove the glue easily. When the glue remains on the bezel surface or
its vestige is recognized, please wipe them off with absorbent cotton waste or
other soft material like chamois soaked with normal-hexane.
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3.Specifications
3.1 Technical Specifications
Panel 26" 32"
Aspect Ratio 16:9 16:9
Resolution (*) 1366 x 768 1366x768
Active Area(mm) (*) 284.16 x 213.12
Brightness (typ) (*) 500 cd/m2 500 / 550 cd/m2
Contrast Ratio (typ) (*) 600:1 / 800:1 800:1 / 1000:1 /1200:1
Viewing Angle (H/V degree) (typ) (*) H/V: 140/115
Response Time (typ) (*) 8ms(GtG) 8ms(GtG)
Picture
Full HD(1080p) support --
INVATEK Engine z
3D DNR (Digital Noise Reduction) z
3D MADI (Motion Adaptive De-Interlacer) z
Digital Comb Filter z
DLTI/DCTI z
DLC (Dynamic Luminance Control) z
3/2 - 2/2 motion pull down z
STC (Skin Tone Control) z
BWS (Black & White Stretch) z
PMR(Picture Mode Recognition) z
Freeze z
Color Temperature Selection Cool1/2, Warm1/2, Normal
Pre-set Picture Modes Standart-Dynamic-Soft-User
Picture Formats 16:9, 14:9, Cinema, 4:3, Auto
Tuning
Tuner PLL
TV-Standards PAL BG / DK / I ; SECAM BG/ DK / LL' z
NTSC 4.43MHz / 3.58MHz Playback z
Auto Programming z
ATS Euro Plus Tuning System z
Fine-tuning z
Program storage capacity 99
VHF / UHF z
Ch. coverage CATV / Hyperband (S1-S41) z
Teletext
Flof teletext z
Teletext capability in OSD Languages z
T.Text Page Memory 250 pages
General Features
HD Ready z
Bitmap GUI (Graphic OSD) z
OSD Menu in multi languages z
On/Off Timer z
Auto shut-off z
Program Lock z
Program naming z
PIP Options
PIP via PC/Component/HDMI(or DVI) available with PIP double tuner
PIP via AV available with PIP double tuner
PIP double tuner {
PAP available w/ PIP double tuner {
PIP(Analog/ Digital) optional for IDTV {
PIP size/Position Adjustment {
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Sound
A2 + Nicam stereo z
Auto Volume Level z
Sound Effect(Spatial Effect) z
Pre-set sound modes flat, speech, music, movie, user
Balance z
Treble z
Bass z
Audio output power (rms) 2 x 8W (<10%THD)
Connections
Side Connections
Video CVBS In, Audio L/R In z
Headphone Output z
Rear Connections
Antenna input ( 75 ohm IEC ) z
1st Scart (RGB, CVBS In/Out, Audio L/R) z
2nd Scart (CVBS In/Out, , Audio L/R) z
Video CVBS Out, Audio L/R Out (AV-OUT) z
YPbPr Video In, Audio L/R In z
480i : 59.94/60Hz, 480P : 59.94/60Hz 576i : 50Hz,
COMPONENT (YPbPr) Modes
576P : 50Hz 720P : 59.94/60Hz, 1080i : 50/59.94/60Hz
S-Video In, Audio L/R In(Cinch) z
VGA Analog PC Input (D-Sub 15P ) z
HDMI(w/ HDCP) z
2nd HDMI(w/ HDCP) w/ full hd chassis --
HDMI / PC Audio In z
CI Slot (available w/ IDTV) {
Accessories
Remote Control Unit TM3602 / TM64 DVD-TV / TM4901IDTV
z : standard { : optional
* These specifications are dependent on the panel brand/ver. & panel manufacturer's changes.
Specifications are subject to change without notice.
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3.2Electrical Specifications
Electrical Specifications
No. Item Description Remarks
Min Typ Max
V
For Audio 11.4 12.0 12.6
For Stand- 4.8 5.0 5.2 V
Power Supply
by
1 For Logic 4.8 5.0 5.2 V
For Tuner 32.5 33.0 33.5 V
Power Consumption normal
operation
Stand-by Power Consumption
DPMS Sync (V/H) VIDEO Power (V/A) LED
Stand By, Sleep & Suspend Off/On &
2 Off 3W DARK RED
Mode On/Off
POWER OFF - - 3W RED
Typical 10Wrms + 10Wrms ( ± 10%) Volume: Adjust
Power
Max 12Wrms + 12Wrms Volume: Max
Response Frequency 100Hz ~ 10KHz
Audio
3
AMP T.H.D 10%
Input 0.700Vrms
S/N 40dB
Type External
4 Speaker
Impedance 8
System System PAL/SECAM
Tuning Frequency Synthesizer System
5 TV
1) VHF LOW: 46.25~127.25MHz
Channel HIGH: 133.25~361.25
2) UHF 367.25~863.75MHz
Video Level 0.7±0.15 V p-p 75

Termination
Sync Level 0.286±0.075 V p-p 75
Termination
Color Burst 0.214±0.072 V p-p 75
Termination
6 AV
0.7±0.1 V rms PC Input
Audio Level 0.5±0.05 V rms NTSC

0.4±0.05 V rms PAL
Video Cross-Talk 43 dB
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3.3 Supported Resolutions

PC Mode
Frequency H- Display Front Sync. Back
CLOCK
M Item Pol [kHz]/[Hz] Total (A) Porch(B) (D) Porch(F) Res.
[MHz]
(E)
1 H(Pixels) + 31.469 800 640 16 96 48 640
V(Lines) - 25.175 70.8 449 350 37 2 60 x
350
2 H(Pixels) - 31.468 900 720 18 108 54 720
V(Lines) + 28.321 70.8 449 400 12 2 35 X
400
3 H(Pixels) - 31.469 800 640 16 96 48 640
V(Lines) - 25.175 59.94 525 480 10 2 33 x
480
4 H(Pixels) - 37.5 840 640 16 64 120 640
V(Lines) - 31.5 75 500 480 1 3 16 x
480
5 H(Pixels) - 43.269 832 640 56 56 80 640
V(Lines) - 36.0 85.0 509 480 1 3 25 x
480
6 H(Pixels) + 37.879 1056 800 40 128 88 800
V(Lines) + 40.0 60.317 628 600 1 4 23 x
600
7 H(Pixels) + 49.5 46.875 1056 800 16 80 160 800
V(Lines) + 75.0 625 600 1 3 21 x
600
8 H(Pixels) + 53.674 1048 800 32 64 152 800
V(Lines) + 56.25 85.061 631 600 1 3 27 x
600
H(Pixels) 49.725 1152 832 32 64 224 832
9 +/- x
57.283
V(Lines) 74.55 667 624 1 3 39 624
+/-
10 H(Pixels) - 48.363 1344 1024 24 136 160 1024
V(Lines) - 65.0 60.0 806 768 3 6 29 x
768
11 H(Pixels) - 60.123 1312 1024 16 96 176 1024
V(Lines) - 78.75 75.029 800 768 1 3 28 x
768
12 H(Pixels) + 68.68 1376 1024 48 96 208 1024
V(Lines) + 94.5 85.00 808 768 1 3 36 x
768
13 H(Pixels) + 44.772 1664 1280 64 128 192 1280
V(Lines) + 74.5 59.855 748 720 3 5 20 x
720
14 H(Pixels) + 47.72 1776 1360 72 136 208 1360
V(Lines) + 84.75 59.799 798 768 3 5 22 x
768
15 H(Pixels) + 63.981 1688 1280 48 112 248 1280
V(Lines) + 108.0 60.02 1066 1024 1 3 38 x
1024
H(Pixels) + 79.98 1688 1280 16 144 248 1280
16 V(Lines) + 135.00 75.02 1066 1024 1 3 38 x
1024
DTV Mode (Component Video Input: Y/Pb/Pr)
- 50Hz: 576i, 576p, 720p, 1080i - 60Hz: 480i, 480p, 720p, 1080i
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16
AM0005 BLOCK DIAGRAM
MULTIBUTTON LED/INFRA
MAIN TUNER PLL TUNER IF1
FLASH SRAM
(512K) (4M)
PIP TUNER PLL TUNER PIP CVBS

VCTi
MTV512
SUB MICOM
. MICOM
. VIDEO DECODER. IP PORT
. AUDIO DECODER EXT CTRL.
. TXT DECODER
SCART CVBS INPUT . IF DEM
SCARTS SCART AUDIO OUT
SCART AUDIO INPUT DDR RAM
17
SCART RGB/FB
74HC4052
AUDIO S/W
MST6***
S-VIDEO AUDIO IN
S-VIDEO AUDIO SCALER
ITU656 .OSD
DEINTERLACE.
TW9906 PIP LCD
S-VIDEO Y/C IN
S-VIDEO ITU656
.VIDEO
DECODER
WM8725
AV AUDIO OUT AUDIO

DECODER
AV CVBS OUT
AV OUT
VGA INPUT
PC INPUT PC AUDIO INPUT SIDE AV CVBS INPUT

TPA3004
SIDE AV AUDIO INPUT
PC/DVI AUDIO HDMi AUDIO INPUT TPA6110 MAIN SPEAKER L/R AUDIO
AMP
DVI-D (Single Link) INPUT HP AMP
HDMi INPUT
YPbPR AUDIO INPUT
YpPbPr INPUT
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FRONT AV HEADPHONE
POWER BLOCK DIAGRAM
+3.3V_VID
TUNER +3.3V_VID +1.8V_VCTi +5V_TUNER
DRAM
VIDEO/AUDIO/MAIN
+3.3V_MICOM K6R4008V1
+5VS RC1117_3. +8V MICOM
+5V +33V
+3.3V_VID /TXT PROCESSOR
+5V_TUNER
+12V 7805
+5VS VCTi
FLASH
+12V +8V DDC IC

7808 EN29LV040 +5VS +2.5V_SCALER
+3.3V_SCALER +1.8V_SCALER
24LC02
+1.8V_VCTi SUB
+5V_OFF RC1117_1. +1.8V_SCALER +8V SCALER
+3.3V_VID MCU
MST6181LDA
+2.5V_VID SWITCH MTV512
+5V_OFF RC1117_2. +2.5V_SCALER
EEPROM
18
4052
24LC32
+3.3V_VID
+5V_OFF +5V_TUNER
RC1117_3. +3.3V_SCALER
+3.3V_VID +12V
I2S
+8V +33V EEPROM AUDIO AMP
4069
AUDIO +3.3V_VID +2.5V_VID
24LC32 TPA3004
WM872
+5VS +5V_OFF +12V +5V_OFF PIP VIDEO DECODER
+5VS 5
TW9906
H.P +2.5V_SCALER
SWITCH
POWER BOARD
AMP
4066 DDR RAM
TPA611
AC INPUT
0A2
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I2C BLOCK DIAGRAM
079
5
7:
5
5
0&8
5
96'$
5
781(5
96&/
5
5
5
6'$B9
6&/B9
((3520
781(5
5
5
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1) J916: For IR, LED - Wafer
Pin No. Symbol Description I/O Remarks

1 LED-WARNING
2 LED-RED LED drive for RED Color O
3 GND Ground
4 IR-RCVR IR Receive Signal I
5 5V 5V Power for IR Receiver O
2) J917: For Local Key - Wafer

1 KEY-AD1 Local Key Value Detection I
2 GND Ground
3) J909: For Debugging - Wafer

1 VCT_RXD Receiver Line O
2 VCT_TXD Transmitter Line I
3 GND Ground
4 3.3V_VID 3.3V Power for Debugging Tool O
4) J912: For Debugging - Wafer

1 VCT_SDA Data Line B DPMS AMBER
2 VCT_SCL Clock Line B
3 GND Ground
5) J915: For HDCP Writing - Wafer

1 GND Ground
2 EEPROM_SCL Clock Line B
3 EEPROM_SDA Data Line B DPMS AMBER
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6) J924: For DVD interface, Wafer

1 DVD_AR Right Sound Signal of DVD/DVB I
2 GND Ground
3 DVD_AL Left Sound signal of DVD/DVB I
4,5 NC No Connection
6 GND Ground
7 NC No Connection
8 GND Ground
9 DVD_Y Luma signal of DVD/DVB I
10 GND Ground
11 DVD_C Chroma signal of DVD/DVB I
12 GND Ground
7) J925: For DVD/DVB Power Supply, Wafer

1 5V-DVD 5V Power for DVD/DVB
2,3 GND Ground
4 12V-DVD 12V Power for DVD
8) J926: For DVB Upgrade Interface, Wafer

1 GND Ground
2 TXD_DVB Transmitter Line I
3 RXD_DVB Receiver Line O
4 GND Ground
9) J927: For IR, Interface (DVB), Wafer

TV_MENU TV OSD MENU Detect Signal O
DVB_MENU DVB OSD MENU Detect Signal I
GPIO No Connection
DVB_ON DVB PWR ON Status I
GND Ground
IR_RCVR IR Receive Signal I
__________________________________________________________________________
21
__________________________________________________________________________________________________________________
10) J919: For Headphone Drive, Wafer

1 HP-R Right Sound signal for Headphone O
2 GND Ground
3 HP-L Left Sound signal for Headphone O
4 HP-SENSE
11) J920: For LCD Speaker Output, Wafer

Speaker Left Positive Class-D Output
1 LOUT+ Signal O
Speaker Left Negative Class-D Output
2 LOUT- Signal O
Speaker Right Negative Class-D Output
3 ROUT- Signal O
Speaker Right Positive Class-D Output
4 ROUT+ Signal O
12) J922: For PDP Speaker Output, Wafer

Speaker Left Positive Class-D Output
1 LOUT+ Signal O
Speaker Left Negative Class-D Output
2 LOUT- Signal O
3 GND Ground
Speaker Right Negative Class-D Output
4 ROUT- Signal O
Speaker Right Positive Class-D Output
5 ROUT+ Signal O
13) J502: For LCD Side AV, Wafer

VCR_ARIN_R Side Right Sound Signal I
GND Ground
VCR_ALIN_L Side Left Sound signal I
GND Ground
VCR_IN Side CVBS Signal Input I
HP-R Right Sound signal for Headphone O
GND Ground
HP-L Left Sound signal for Headphone O
__________________________________________________________________________
22
__________________________________________________________________________________________________________________
14) J923: For PDP Side AV, Wafer

1 NC No Connection
2 GND Ground
3 VCR_ALIN_L Side Left Sound signal I
4 GND Ground
5 VCR_ARIN_R Side Right Sound Signal I
6 GND Ground
7 NC No Connection
8 GND Ground
9 VCR_IN Side CVBS Signal Input I
10 GND Ground
15) J701: For Logic Power Supply – LCD, Wafer

1 P_CTRL1 SMPS Power On Control Signal O 3.3V(High) :On
2,3 GND Ground
4 5V_OFF_CD 5V Logic Power Supply I
5 5V_DVD_CD 5V DVD Power Supply I
6 5VS 5V Standby Power Supply I
7,8 GND Ground
9 12V_CD 12V Power Supply I Max 3.0A
10 12V_DVD_CD 12V DVD Power Supply I Max 1.0A
11 INV_DIM Inverter Dimming Control Signal O Max 1.0A
12 INV_CTRL Inverter ON/OFF Control Signal O
16) J702: For Logic Power Supply – SDI PDP, Wafer

1,3,4 GND Ground
2 NC No Connection
5 12V_DVD_SS 12V DVD Power Supply I Max 1.0A
6 12V_AMP_SS 12V Audio Amp. Power Supply I
7 GND Ground
8 12V_SS 12V Power Supply I Max 3.0A
9 GND Ground
10 5V_DVD_SS 5V DVD Power Supply I
__________________________________________________________________________
23
__________________________________________________________________________________________________________________
17) J921: For Logic Power Supply – SDI PDP, Wafer

1 THD_SS VS On Control Signal
2 5VS 5V Standby Power Supply I
3 GND Ground
4 P_CRTL_SS SMPS Power On Control Signal O 3.3V(High) :On
5 NC No Connection
6,7 GND Ground
8,9 3.3V_OFF_SS 3.3V Logic Power Supply I
10 GND Ground
11 5V_OFF_SS 5V Logic Power Supply I
18) J704: For Logic Power Supply – LG PDP, Wafer

1,2 NC No Connection
3,4 GND Ground
5 12V_LG 12V Power Supply I
6 12V_DVD_LG 12V DVD Power Supply I
7,8,9 GND Ground
10,11 5V_OFF_LG 5V Logic Power Supply I
12 5V_DVD_LG 5V DVD Power Supply I

1,2 GND Ground
3,4 24V_LG 24V Power Supply I

NC No Connection
5V_D 5V Detection I
SW_PANEL_P VS On Control Signal O
GND Ground
5VS 5V Standby Power Supply I
P_CRTL SMPS Power On Control Signal O 3.3V(High) :On
ACD AC Detection I
__________________________________________________________________________
24
__________________________________________________________________________________________________________________
21) J913: For LCD VDD Selection – LCD, Wafer

1 12V_CD 12V Power Supply I
2 LCD_VDD Selected LCD_VDD Power Supply O
3 5V_OFF 5V Power Supply I
22) J102: LVDS Interface for LCD - PDP - DLP, Wafer
Pin No Symbol Function Remark

1 PDP_DLP_SCL PDP_DLP Clock Line
350mVpp
2 RA- LVDS A Channel Negative Signal
±5%
3 GND Ground
350mVpp
4 RA+ LVDS A Channel Positive Signal
±5%
5,6 GND Ground
7 PDP_DLP_SDA PDP_DLP Data Line
350mVpp
8 RB- LVDS B Channel Negative Signal
±5%
9 GND Ground
350mVpp
10 RB+ LVDS B Channel Positive Signal
±5%
11 LVDS_OPTION LVDS Option selection
12,13 GND Ground
350mVpp
14 RC- LVDS C Channel Negative Signal
±5%
15 GND Ground
350mVpp
16 RC+ LVDS C Channel Positive Signal
±5%
17,18,19 GND Ground
350mVpp
20 RCLK- LVDS Clock Channel Negative Signal
±5%
21 LVDS_MAP_SEL LVDS Map Selection
350mVpp
22 RCLK+ LVDS Clock Channel Positive Signal
±5%
23 LCD_VDD LCD Power or Ground
24 GND Ground
350mVpp
26 RD- LVDS D Channel Negative Signal
±5%
350mVpp
28 RD+ LVDS D Channel Positive Signal
±5%
30 GND Ground
__________________________________________________________________________
25
__________________________________________________________________________________________________________________
23) J21: LVDS Interface for LCD-PDP-DLP, Wafer
Pin No Symbol Function Remark

1,2 GND Ground
4 PDP_DLP_SDA PDP_DLP Data Line
5 GND Ground
350mVpp
6 RD+ LVDS D Channel Positive Signal
±5%
350mVpp
7 RD- LVDS D Channel Negative Signal
±5%
8 GND Ground
350mVpp
9 RCLK+ LVDS Clock Channel Positive Signal
±5%
350mVpp
10 RCLK- LVDS Clock Channel Negative Signal
±5%
11 GND Ground
350mVpp
12 RC+ LVDS C Channel Positive Signal
±5%
350mVpp
13 RC- LVDS C Channel Negative Signal
±5%
14 GND Ground
350mVpp
15 RB+ LVDS B Channel Positive Signal
±5%
350mVpp
16 RB- LVDS B Channel Negative Signal
±5%
17 GND Ground
350mVpp
18 RA+ LVDS A Channel Positive Signal
±5%
350mVpp
19 RA- LVDS A Channel Negative Signal
±5%
20 GND Ground
21 INV_CTRL Inverter Brightness Control
22 LVDS_MAP_SEL LVDS Map Selection
23, 24
GND Ground
25, 26
27,28
VDD LCD Power
29, 30
__________________________________________________________________________
26
__________________________________________________________________________________________________________________
24) J905: Full SCART
1 SCART_ROUT SCART Audio Right Output O
2 SCART_ARIN_R1 SCART Audio Right Signal Input I
3 SCART_LOUT SCART Audio Left Output O
4,5 GND Ground
6 SCART_ALIN_L1 SCART Audio Left Signal Input I
7 SCART_VBIN1 SCART Blue Video Signal Input I
8 SCART_AVSW1 ID detection Signal
9 GND Ground
10 NC No Connection
11 SCART_VGIN1 SCART Green Video Signal Input I
12 NC No Connection
13 GND Ground
14 NC No Connection
15 SCART_VRIN1 SCART Red Video Signal Input I
16 SCART_FBLNK1 SCART R/G/B Video FB Signal Input I
17,18 GND Ground
19 SCART_VOUT1 TV Video Signal Output O
20 SCART_VIN1 SCART CVBS Signal Input I
__________________________________________________________________________
27
__________________________________________________________________________________________________________________
25) J907: Half SCART
1
SCART_ROUT2 Selected Audio Right Output O
2
SCART_ARIN_R2 SCART Audio Right Signal Input I
3
SCART_LOUT2 Selected Audio Left Output O
4,5
GND Ground
6
SCART_ALIN_L2 SCART Audio Left Signal Input I
7
NC No Connection
8
SCART2_AVSW2 ID detection Signal
9
GND Ground
10
TXD_DVB DVB Upgrade Line
11
NC No Connection
12
RXD_DVB DVB Upgrade Line
13, 14
GND Ground
15
SCART_CIN2 SCART Chroma Signal Input I
16
NC No Connection
17,18
GND Ground
19
SCART_VOUT2 Selected Video Signal Output O
20
SCART_VIN2 SCART CVBS or Luma Signal Input I
__________________________________________________________________________
28
__________________________________________________________________________________________________________________
Rear Connection
Side AV Connection
Audio / Video In
- Video CVBS (1 Vpp / 75 ƻ)
- Audio L
- Audio R
- Headphone 3.5 mm
__________________________________________________________________________
29
__________________________________________________________________________________________________________________
5. MENU STRUCTURE
MAIN Menu PICTURE
SOUND
PIP/PAP
FEATURES
INSTALLATION
PICTURE Menu COLOR TEMP NORMAL, COOL, WARM

PICTURE PRESET DYNAMIC, STANDARD, SOFT, USER
Brightness 100 Steps
Contrast 100Steps
Colour 100Steps
Sharpness 100Steps
TINT -50, +50
SOUND Menu Volume 100 Steps

SOUND PRESET FLAT, MUSIC, MOVIE, SPEECH, USER
SURROUND ON / OFF
AVL ON / OFF
BALANCE L50,R50
BASS 100Steps
TREBLE 100Steps
PIP/PAP Menu ON/OFF OFF/PIP/PAP1/PAP2

SOURCE ALL SOURCE
PIP SIZE SMALL/LARGE
PIP POSITION
FEATURES Menu Language (English /GERMAN /FRENCH/ITALIAN/

SPANISH/DUTCH/GREEK/DANISH/
SWEDISH/FINNISH/TURKISH/RUSSIAN
CZECH/HUNGARIAN/PORTUGISH/
NORWEGIAN/HIRVATSKI/SLOVENCE/
BULGARSKI/ARNAVUT/SLOVAKCA/
POLSKI/SIRPSKI/MAKEDONSKI/ARABIC)
TRANSPARENCY 100 Steps

RESET
TIMER
CLOCK HH:MM
OFF TIME HH:MM ON/OFF
ON TIME HH:MM ON/OFF
PR NUMBER
VOL 100Steps
AUTO SHUT OFF ON/OFF
INSTALLATION
AUTO TUNNING
COUNTRY SELECTION (BELGIUM/FRANCE/GERMANY/ITALY/ NETHERLAND/
SPAIN/SWEDEN/SWITZERLAND/UK/TURKEY
POLAND/OTHER)
MANUAL TUNING PROGRAMME NUMBER
SYSTEM EURO/FRANCE
NAME
SEARCH
FINE TUNE
PROGRAM LOCK ON/OFF
__________________________________________________________________________
30
__________________________________________________________________________________________________________________
Service Menu
(Will be displayed by pressing the digits “1923” while the top level Main menu is active)
Service Main
VCTI
MSTAR
ADJUST
AUTO COLOR
OPTION
RESET
DEFAULT
ISP
SOFTWARE INFORMATION
SOFTWARE DATE THE DATE OF MAKING THE SOFTWARE
MAIN VERSION THE MAIN MCU SOFTWARE REVISION NUMBER
SUB VERSION THE SUB MCU SOFTWARE REVISION NUMBER
DISPLAY DEVICE INFORMATION LCD AUO 32
VCTI ,MSTAR
(THIS ITEM MUST NOT CHANGED WHEN SERVICE, ONLY FOR ENGINEERING TEST)
ADJUST
(THIS ITEM IS USED WHEN NEED TO ADJUST THE WHITHE BALANCE)
__________________________________________________________________________
31
__________________________________________________________________________________________________________________
WE CAN ADJUST THE WHITE BALANCE BY CHANGING THE GAIN/OFFSET. IF ADJUSTING THE HIGH
BRIGHTNESS PART, PLEASE CHANGE THE GAIN. IF ADJUSTING THE LOW BRIGHTNESS ,PLEASE
CHANGE THE OFFSET.BUT THIS ADJUSTING IS NOT EFFECT IN OTHER SOURCE.
AUTO COLOR
THIS IS USED ONLY IN PC ANALOG OR COMPONENT SOURCE. WHEN ADJUSTING THE AUTO COLOR,
WE MUST USED THE SPECIAL COLOR PATTERN.
__________________________________________________________________________
32
__________________________________________________________________________________________________________________
OPTION
= HOTEL MODE ON/OFF
TXT AREA DON’T TOUCH
TXT TOP DON’T TOUCH
LVDS TI/NORMAL
* WHEN WE HAVE WRONG COLOR, PLEASE CHANGE THIS OPTION
TUNER 1/2
* ACCORDING TO 1 TUNER OR 2TUNER MODEL.
PIP ON OFF/PC/AC
* DEPENDING ON THE TV MODEL
SIDE AV ON/OFF
* DEPANDING ON THE TV MODEL
EXTERNAL NO/DVB/WIRELESS/DVD
* DEPENDING ON THE TV MODEL
CUSTUM TELRA/GRUNGDIG/PHILIPS
* DEPANDING ON THE TV MODEL
LCD SELECT THE DISPLAY DEVICE
RESET
WHEN WE FINISH THE SERVICE, PUSH THE RESET THIS FUNCTION INITIALISE THE EEPROM
DEFAULT
DON’T TOUCH THIS ITEM.
ISP
OFF/ISP
WHEN WE UDATE THE SOFTWARE, PLEASE THIS ITEM
WE NEED THE SPECIAL JIG AND SOFTWARE WHEN UPDATING S/W.
__________________________________________________________________________
33
5 4 3 2 1
+5V_1TUNER
RED+ L9031 2 HB-1608-300 R985 1 2 100 C9191 2 100nF
GREEN+ L9021 RED_IN 5
2 HB-1608-300 R927 1 2 100 C9171 2 100nF GREEN_IN 5
BLUE+ L9011 2 HB-1608-300 R925 1 2 100 C9151 2 100nF
2
2
2
BLUE_IN 5
2
2
2
R956
2
J903 R994 R995 R996 470 18K
1
75 75 75 R326 Q905 R958 C940
L-DSUB
VGA_SLIM_DVIMTG 75 A1504 1uF
1
1
16
COMMON
MTZJ5.6B
MTZJ5.6B
1
1
1
1
GND-R 6 RED- RED- R986 1 2 100 C9471 2 100nF R976 2 1 * ZD932 ZD946
6
R_GND_S 5
+
ID0 11 R 1 RED+ GREEN- R928 1 2 100 C9181 2 100nF J905 Q903 1 2
11 1
GND-G GREEN- BLUE- R926 G_GND_S 5 KSC1623 SCART_VOUT1 3
7 1 2 100 C9161 2 100nF B_GND_S 5 21
SDA 12 G 2 GREEN+ 20 C935 100UF/16V
GND_B BLUE- SCART_VIN1 3
8 +3.3V_SCALER 22 19 R977 2 1 75 2 1
HSYNC 13 B 3 BLUE+ 18
2
2
2
2
2
5V D910 D911 D912 R971 150
9 17
1
1
VSYNC ID2 DDC5V_DSUB C906 BAV99 BAV99 BAV99 R970 R957
14 4 16 R319 2 1 0 SCART_FBLNK1 3
GND 10 1 2 ZD906 C905 1uF 3 3 3 J912 15 140 10K
10 SCART_VRIN1 3
SCL 15 GND 5 MTZJ5.6B 1uF 14
2
2
15 5 1
D R916 * D
13
1
1
2 VCT_SCL 3,6,7,8
12
1
1
1
Main Board
3 VCT_SDA 3,6,7,8
11 SCART_VGIN1 3
COND3P 10
17
CHK_DSUB 6 9
8 R975 2 1 10K SCART_AVSW1 6
R909 1 2 1K R904 1 2 * 7
R908 1 PC_VSYNC_IN 5 SCART_VBIN1 3
2 1K R903 1 2 * PC_HSYNC_IN 5 6 R954 2 1 15K SCART_ALIN_L1 4 C936
5
2
2
4 22UF/16V
1
1
+
DDC_SCLA 3 R907 R910 C902 C903 +3.3V_VID
DDC_SDAA 3 23 3 R962 2 1 330 2 1 SCART_LOUT1 3
2.7K 10K 22PF 100P R1022 1K 2 R955 2 1 15K
+
ZD903 ZD950 ZD908 ZD909 ZD912 L103 SCART_ARIN_R1 4
1 R963 2 1 330 2 1
2
2
COND5P SCART_ROUT1 3
10 * R453
1
1
2
+3.3V 5 R1000 1 2 C937
P5 +5VS
MTZJ5.6BMTZJ5.6B MTZJ5.6BMTZJ5.6B MTZJ5.6B IR 4 R1001 10 * SCART JACK C970 22UF/16V
2
2
P4 IRRCVR 6 *
3
1
GND P3
2 R918 100 R965 R964
2
D909 KDS184 LED_RED P2 LEDRED 6 56K 56K
P1 1 LEDWARNING 6
C901 +5VS R485 R486 C971
0.1uF DDC5V_DSUB *
J916
1
1
1
COND4P
+5V_DDC 1K 1K
U901 R984 1 ZD935 ZD938 ZD936 ZD940
2 10K C734 2 1 470U/16V 4
1
P4
+
1 A0 VCC 8 R902 1 2 10K P3 3
2 7 C788 2 1 0.1uF 2
A1 WP E_DDC_CTL 7 P2 VCT_TXD 3
3 6 R9121 2 100 1
2
2
2
2
2
2
A2 SCL DDC_SCLA 3 C955 15PF P1 VCT_RXD 3 ZD942 ZD943 ZD944 ZD945 ZD933
4 5 R9141 2 100
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
2
2
2
2
2
VSS SDA DDC_SDAA 3 +3.3V_SCALER R344 R324 ZD934 ZD939 ZD937 ZD941
J909
24LC02 150 150
1
1
1
1
4.7K R936 COND2P
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
1
1
1
1
1
2
2
2
2
2
2
2
2
D904 D908 D903 D907 D902 D906 D901 D905
2 1 2
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
1
7 E_DDC_CTL +5V_DDC * * * * * * * * GND P2 C943 C942 +5V_1TUNER
4.7K R951 3 3 3 3 3 3 3 3 R321 R322 R974 * *
Q902 2 1 ZD905 KEY 1 R323 3.3K C945 C944
KSC1623 M_DDC_CTL 6 * P1 KEY_AD1 6 75 75 75 1.5nF 1.5nF
1
2
2
J917
1
1
1
1
1
1
1
1
2
C789 R961 R960
0.1uF 470 18K C941
2
2
DVI_RX0- R110 10 RX0- Q906 1uF
1 2
1
DVI_RX0+ R109 10 RX0+ RX0- 5 R329 A1504
1 2
1
1
20
21
HDMI_CONN_V DVI_RX1- R108 10 RX1- RX0+ 5 75
1 2 RX1- 5
MTZJ5.6B
MTZJ5.6B
DVI_RX1+ R107 1 2 10 RX1+
T1
T2
HOT_PLUG DVI_RX2- R106 10 RX2- RX1+ 5
19 1 2 R938 2 1 *
1
C HPDET RX2- 5 C
+
18 DDC5V-DVI DVI_RX2+ R105 1 2 10 RX2+ J907 ZD918 ZD919 Q904 1 2

+5V DVI_CHK R112 10 RXC- RX2+ 5 3,8 KSC1623 SCART_VOUT2 3
CEC/GND 17 1 2 RXC- 5 21
16 DDC_SDAB R111 1 2 10 RXC+ 20 C934 100UF/16V
SDA DDC_SCLB RXC+ 5 SCART_VIN2
SCL 15 DVI_RX0- 7 22 19 R937 2 1 75 2 1
14 18 2
2
NC R469 0 DVI_RX0+ 7 R973 150

CEC 13 DVI_RX1- 7 17
12 DVI_RXC- 16 R972 R959
CLK- DVI_RXC- 2 DVI_RX1+ 7 140 10K
CLKS 11 DVI_RX2- 7 15 SCART_CIN2 8
P402 10 DVI_RXC+ 14
CLK+ DVI_RX0- DVI_RXC+ 2 DVI_RX2+ 7
9 13
1
1
DATA0- DVI_RX0- 2 DDC_SCLB

DATA0S 8 DDC_SCLB 12 RXD_DVB 5
7 DVI_RX0+ DDC_SDAB 11
DATA0+ DVI_RX1- DVI_RX0+ 2 DDC5V-DVI DDC_SDAB
DATA1- 6 DVI_RX1- 2 DDC5V-DVI 10 TXD_DVB 5
5 DVI_CHK R901 1 2 100 9
DATA1S DVI_RX1+ DVI_RXC- CHK_DVI 6
DATA1+ 4 DVI_RX1+ 2 DVI_RXC- 7 8 R939 2 1 10K SCART_AVSW2 6
3 DVI_RX2- DVI_RXC+ 7
DATA2- DVI_RX2- 2 DVI_RXC+ 7
2 6 R942 2 1 15K
2
DATA2S DVI_RX2+ ZD902 ZD949 ZD948 ZD947 SCART_ALIN_L2 4 C924
1 5
*
*
*
*
DATA2+ DVI_RX2+ 2 R905 22UF/16V
4
+
1K 23 3 R950 2 1 330 2 1 SCART_LOUT2 3

2 R935 2 1 15K
+
SCART_ARIN_R2 4
6.CIRCUIT DIAGRAMS AND PCB LAYOUTS
1 R934 2 1 330 2 1
1
HOT_PLUG SCART_ROUT2 3
2
2
R906 1K C929
2
2
1 2 Q901 SCART JACK 22UF/16V

D913 5 HDCP_CONTROL KSC1623 R930 R949
1
1
J910 56K 56K

+5VS DDC5V-DVI WHITE R945 2 1 15K C972 C973
KDS184 SVHS-LIN 4 * *
1
1
C946 1 2 0.1uF RED R943 2 1 15K SVHS-RIN 4

ZD958 ZD957 ZD921 ZD922 ZD923 ZD924
U902 R983 1 RCAJACK2P_R14222S
2 4.7K
1 A0 VCC 8 R982 1 2 4.7K
2 7 J902
2
A1 WP E_DDC_CTL 7 ZD920
3 6 R981 1 2 100 DDC_SCLB R979 1 2 100 3
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
2
A2 SCL DVI_DDC_CLK 5 ZD959 ZD956 R458 ZD913 ZD914 ZD915 ZD916

4 VSS SDA 5 R978 1 2 100 DDC_SDAB R980 1 2 100 DVI_DDC_DAT 5 4 R911 2 1 15K PC-AIN-R 4
75 R929 ZD917 5 R913 2 1 15K
2
2
2
2
3.3K PC-AIN-L 4
24LC16 2
ZD910 ZD907
MTZJ5.6B
1
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
1
1
1
1
1
PHONEJACK STEREO
MTZJ5.6B
C931 C930 C925 C923 R915 2 1 *

1.5nF * 1.5nF *
MTZJ5.6B
MTZJ5.6B
B B
J11 ZD911 ZD904
1 COMP-Y COMP-PR-GND R991 2 1 100 C953 2 1 47nF
P1 COMP-PB-GND COM_PR_GND 5
P2 2 R987 2 1 100 C948 2 1 47nF COM_PB_GND 5
3 COMP-Y-GND R989 2 1 100 C950 2 1 47nF
P3 COM_Y_GND 5 C968
4
MTZJ5.6B
MTZJ5.6B
2
2
2
P4 SVHS_CIN 22UF/16V
5
+
P5 SVHS_YIN R999 R997 R998
P6 6 4 LOUT_M
R1016 2 1 330 2 1 SCART_LOUT2 3
7 75 75 75
P7 COMP-PB
P8 8
9 C969 COND12P
1
1
1
P9 COMP-PR R992 100 22UF/16V
10 2 1 12
+
P10 COMP-PR COMP-PB R988 100 COM_PR 5 GND P12
P11 11 2 1 COM_PB 5 4 ROUT_M
R1017 2 1 330 2 1 SCART_ROUT2 3 P11 11
12 VOUT_M COMP-Y R990 2 1 100 C 10
P12 R993 470 COM_Y 5 ZD967 ZD965 GND P10
13 2 1 9
2
2
2
2
P13 COMP-LIN COM_SYNC 5 Y P9

P14 14 P8 8
15 LOUT_M COMP-RIN R940 2 1 15K C736 C735 GND 7
P15 COMP-LIN DTV_AIN_R 4 J925 220uF/16V
+ +
220uF/16V CVBS P7 DVD_Y 5
P16 16 R941 2 1 15K DTV_AIN_L 4 P6 6
17 COMP-RIN Monitor COND4P GND 5
MTZJ5.6B
MTZJ5.6B
1
1
P17 ROUT_M ZD966 ZD964 SPDIF P5 R967 15K DVD_C 5

18 4
1
1
P18 ZD969 ZD928 ZD929 TV_MUTE P4

P19 19 Output OPTION P1 1 +12V_DVD P3 3 2 1 DVD_AL 5
2 A-L 2
RCAJACKX2 P2 R968 * GND P2
P3 3 +5V_DVD P1 1 2 1 DVD_AR5
COMP-Y-GND R1019 R1018 A-R
MTZJ5.6B
MTZJ5.6B
4 2 1
1
2
2
COMP-PB-GND ZD951 ZD953 56K 56K P4 J924 R966 15K R481
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
COMP-PR-GND +5V_1TUNER + 12P FCC CABLE 75
ZD952 ZD930 ZD931 DVD/DVB POWER 2.5mm C727 DVD/DVB R482
220uF/16V 75
2
CHK_SVIDEO
MTZJ5.6B
MTZJ5.6B
R1030 2 1 *
1
1
2
2
SVHS_CIN CHK_SVIDEO 6 SIDE A/V IS BOARD A/V INPUT VCR_ARIN_L near the connector R1027 *
2
SVHS_YIN SVHS_CIN 3,8 R1015 R1011
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
R1031 2 1 * 2 1
SVHS_YIN 3,8 R10302,R10312 1)SIDE A/V OPTION VCR_ARIN_R 470 18K C966 J926
R10322 DELETE BOX DELETE Q909 1uF +5VS
1
2
2
ZD925 ZD927 ZD926 2)R10302,R10312 15KOHM A1504 COND4P
1
1
R947 R327 3)R10322 0OHM R1032 2 1 * R969

2
2
75 75 3 VCR_IN R1026 4.7K

P4 4
P3 3 RXD_DVB 5
+
Q908 1 2 2 100
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
1
1
R1010 KSC1623 SCART_VOUT2 P2 TXD_DVB 5 C974 1nF
3 P1 1
75 C967 100UF/16V 2 1
1
1
2 1 2 1 R1029 470 R1028 0

2
2
3 VOUT_M Q910 2 1 2 1 2 1 IRRCVR 5

R1014 150 R1012 R1013 DVB UPGADE 2.5mm KSC1623
COND6P
140 10K D18 1N4148
A SIDE A/V OPTION R565 1K 75 ZD968 6 2 1 Q911 A
1
2
R325 MTZJ5.6B P6 KSC1623 IRR_MUTE 5

2 1 5
1
1
+5V_OFF P5
R554 * H:TV L:DVB 4 R1025 150
2
COND8P P4 DVB_ON 6
10 1 2 HP-L GPIO 3
P10 HP L HP-L H:MENU L:CLOSE FOR DVB P3 GPIO 6 R1023
P9 9 P8 8 HP-SENSE 3 P2 2 DVB_MENU 6
8 GND 7 2 1 H:MENU L:CLOSE FOR TV 1 470
2
1
P8 HP R P7 R563 * R555 * HP-R 3 P1 TV_MENU 6 R1024

P7 7 P6 6 1 2 HP-R
6 V IN 5 J927 140
1
P6 P5 VCR_IN COND5P
5 GND 4
P5 P4 COND4P
4 A-L 3 R556 2 1 0 5 COMMUNICATION 2.0mm
P4 P3 VCR_ARIN_L COND4P P5 ROUT+
3 GND 2 SP R+ 4 4
P3 A-R P2 SP R- P4 ROUT- HP L P4 HP-SENSE 3
P2 2 P1 1 R557 2 1 0 VCR_ARIN_R P4 4 ROUT+ P3 3 P3 3 HP-L
1 ZD504 SP R+ 3 2 GND 2
P1 ZD502 MTZJ5.6B MTZJ5.6B ZD505 SP R- P3 ROUT- SP L- P2 LOUT- P2 DVD_OPTION,IDTV Date
J502 2 1 HP R 1
SP L- P2 LOUT- SP L+ P1 LOUT+ P1 HP-R INS60256487 CONFIDENTIAL Thursday, April 27, 2006
J923 P1 1 LOUT+
COND10P LCD ONLY ZD501 MTZJ5.6B MTZJ5.6B SP L+ J922 J919 option Title Sheet 2 of 8
PDP ONLY J920 AM0005 Size Rev Document Number
ZD503 <Doc>
MTZJ5.6B
2.5mm for Custom A4
LCD ONLY PDP ONLY 02. DVI/DSUB/SCART/RS232C
future,delete Note
Designer
AddressDaeil Plaza #602, 528-3, Chonchun-Dong, Jangan-Gu,Suwon, Kyounggi-Do, 440-330, Korea
5 4 3 2 1
5 4 3 2 1
+3.3V_MICOM +1.8V_VCTi VSUP1.8DIG VSUP1.8FE

+3.3V_VID VSUP3.3BE VSUP3.3DIG
1 2 C346 1 2 +3.3V_VID VSUP3.3DAC
0.1uF R385 * R334 2 1 *
U306 R360 2 1 *
7 VSS VDD 14 R304 2 1 *
R402 * 2 1
1
1
1 2 1 13 1 2 C326 C332 R365 2 1 * R335 *
1
1
1
5 IRRCVR IN 1 CNTL 1 P_CTRL5 C315 C321 C302
2 1 2
1
1
1
OUT 1 IRRCVR_VCTI 6
R397 * R398 * 0.1uF 3.3uF/50V 1uF C335 C320 C316
2
2
1
1 2 4 5 0.1uF 0.1uF C337 1uF
2
2
2
5 KEY_AD1 IN 2 CNTL 2 0.1uF 0.1uF
3 1 2
2
2
2
OUT 2 KEY_AD1_VCTI 6 5
R395 * R388 * 0.1uF
1
1
RF_CVBS 1 2 8 6 C327 C328
IN 3 CNTL 3 SUB_RFSW
OUT 3 9 1 2 SUB_TUNER_CVBS 6
R394 * R401 * 1nF 1nF +3.3V_VID
2
2
1 2 11 12 +8V_SW_OFF VSUP8.0VAU +5V_1TUNER VSUP5.0BE VSUP5.0IF VSUP5.0FE
D DVD_C IN 4 CNTL 4 LOUD_OUT_L 4 D
10
1
OUT 4 +3.3V_MICOM LOUD_OUT_R 4
R393 * * R261
SCART_LOUT1 2 VSUP3.3EIO VSUP3.3IO VSUP3.3FE
74HC4066 R337 R342 2 1 * R351
SCART_ROUT1 2
6.8K R341 2 1 *
SCART_LOUT2 2
* R336 R338 *
SCART_ROUT2 2
+3.3V_VID Q205 * R260 6.8K 6.8K R333 2 1 *
2
AV_DTV_L 4 2 1 *
C312 1 2 0.1uF R332 2 1 *
AV_DTV_R 4 C331 R361 2 1 *
1
1
1
U302 HDMI_AIN_L 4
R302 4.7K C330 1uF C325 R3115
1
1
1
HDMI_AIN_R 4
1 8 R301 4.7K R339 2 1 * C314 C324 C319 R309 2 1 *
A0 VCC 0.1uF 0.1uF
2 7 R340 2 1 *
2
2
2
VSUP8.0VAU
A1 WP
VSUP5.0BE
3 6 R306 100 EEPROM_SCL 0.1uF 0.1uF 0.1uF
2
2
2
1
1
1
1
A2 SCL EEPROM_SCL 6 TAGC

4 5 R307 100 EEPROM_SDA C364 C336 C301 C313
VSS SDA EEPROM_SDA 6
1uF
IF-
VSUP5.0BE 0.1uF 0.1uF 0.1uF
2
2
2
2
1
24LC32B IF+ +33V_T
C329
0.1uF L709
2 1
2
1
J915
+
2
1 C602 HH-2012-121
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
2 EEPROM_SCL 3 VSUP5.0FE
U301 R601 10UF/50V
2
1
1
3 EEPROM_SDA 3 C318 C317 *
1
1
0.1uF 1uF
EW
BIN
COND3P C334 C333
RIN
GIN
IFIN-
FBIN
P145
IFIN+
TEST
AIN3L
AIN2L
AIN1L
TAGC
VCT-X1 C322
GND6
GND7
ROUT
GOUT
RSW1
RSW2
AIN3R
AIN2R
VERT-
2
2
1
GNDM
VERT+
SENSE
VREFIF
AOUT1L
AOUT2L
0.1uF 4.7uF/35V 22pF
VREFAU
AOUT1R
AOUT2R
2
2
SVMOUT
AIN1R/SIF
1 108 U639
SPEAKERL
2
VSUP5.0BE
SPEAKERR
VCT_RESETQ 6
VSUP8.0AU
BOUT RESETQ COIL-3.3UH L601
2 VRD VSUS5.0FE 107
R363 1K 3 106 X301 1Tuner:TECH2949PS40B(D) 2 1
XREF VSUP5.0FEI VSUP5.0IF +5V_1TUNER
4 105 20.25MHz 2Tuner/DVB:TECH2949PS40A(D)
1
1
VSUP3.3BE VSUP3.3BE VSUP3.3DIG VSUP3.3DIG

5 104
1
1
GND2 GND4 C601 C603 + C604 +

6 GND3 GND5 103
VSUP3.3IO 7 102 VSUP1.8DIG VCT-X2 C323 0.01uF *
VSUP3.3IO VSUP1.8DIG VCT-X1 22pF 470U/16V
8 101
2
2
2
VSUP3.3DAC VSUP3.3DAC XTAL1

9 100 VCT-X2 1
GNDDAC XTAL2 AGC
C 10 99 EEPROM_SCL 6 2 C
SAFETY P22 NO_PIN1
11 HFLB P23 98 EEPROM_SDA 6 SAS 3
R343 * 12 97 VCT_PSENQ 4 R622 1 2 100
HOUT PSENQ VCT_ADB10 SCL VCT_SCL 2,6,7,8
13 VPROT ADB10 96 SDA 5 R621 1 2 100 VCT_SDA 2,6,7,8
VCT_ADB11 14 95 VCT_DB7 6
1
1
VCT_ADB9 ADB11 DB7 VCT_DB6 NO_PIN2

15 ADB9 DB6 94 B+ 7
VCT_ADB8 16 93 VCT_DB5 8 C624 C623 +5V_1TUNER
VCT_ADB13 ADB8 DB5 VCT_DB4 NO_PIN3 20pF 20pF
17 92 9
2
2
VCT_ADB14 ADB13 DB4 VCT_DB3 BT

18 91 15 10 2 1
2
VCT_ADB17 19
ADB14 VCT49XYI DB3
90 VCT_DB2 14
CHASSIS2 IF2
11 IF-OUT
VCT_PSWEQ ADB17 DB2 VCT_DB1 CHASSIS3 IF1 R603
20 PSWEQ DB1 89 13 CHASSIS4 0
VCT_ADB18 21 88 VCT_DB0 12 R623 8.2K
VCT_ADB16 ADB18 DB0 VCT_ADB0 CHASSIS1
22 ADB16 ADB0 87
VCT_ADB15 23 86 VCT_ADB1
1
VCT_CS R366 2 ADB15 ADB1 VCT_ADB2 TECH2949PG40B

1 * 24 STOPQ ADB2 85
25 84 VCT_ADB3 MAIN TUNER
1
1
VCT_ADB12 ENEQ ADB3 TAGC

26 ADB12 P24/656CLKIO 83 L904 1 2 HB-1608-102 VCT656_CLK 5
VCT_ADB7 27 82 near the VCTif and use GND line. R602 R604
VCT_ADB6 ADB7 P25/656HIO use inside layer. L602 +5V_1TUNER 100K
28 ADB6 P26/656VIO 81 *
VCT_ADB5 29 80 C609 C605 HH-2012-121
VCT_ADB4 ADB5 P30/656IO0 R3116 * 0.01uF
30 79 100UF/16V 2 1
2
ADB4 P31/656IO1 ALE_SCALER 5

31 78
1
1
1 2
ADB19 P32/656IO2 IRRCVR_VCTI 2,6

RDQ_JACK 32 77
1
1
1
1
WRQ_JACK RDQ VSUP3.3EIO + C610

33 WRQ GNDEIO 76 VSUP3.3EIO
34 75 C913 C910 C911 R608 R607 L603 0.01uF
2
OCF P33/656IO3 * 1nF 560nH

35 74
2
2
2
2
2
ALE P34/656IO4 100pF 1.3K 150 U603 X6966M

2 1 36 RSTQ P35/656IO5 73
2
C339 10uF/16V C607 1 2 0.01uF 1 4 IF+

IN1 OUT1
C608 0.01uF 2 5 IF-
Q601 IN2 OUT2
1 2
1
VCT656[0..7] 5 IF-OUT
PWMV
DFVBL
SDA
SCL
P21
P20
P17
P16
P15
P14
P13
P12
P11
P10
XROMQ
EXTIFQ
VSUP3.3FE
GND0
GND1
VSUP1.8FE
VOUT3
VOUT2
VOUT1
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
VIN11
P37/656IO7
P36/656IO6
GND
47 8 1 RA104VCT6560 KSC1623
7 2 VCT6561 R610
3
VCTI49xyi
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
6 3 VCT6562 R606 27 0
5 4 VCT6563
47 8 1 RA105VCT6564 R609
2
B 7 2 VCT6565 near the VCTif and use GND line. R605 C606 B
6 3 VCT6566 use inside layer. 510 0.01uF
+5VS 5 4 VCT6567 4.7
2
R303
R472 4.7K
R470 4.7K R305 2 1 100
R471 100 C311 1 SCART_FBLNK1 2
2,6,7,8 VCT_SDA 2 100nF R318 2 1 100
*
R473 100 C310 1 R317 100 SCART_VBIN1 2
2,6,7,8 VCT_SCL 2 100nF SCART_VGIN1 2
C309 1 2 100nF R308 100 +3.3V_MICOM
SCART_VRIN1 2
2 VCT_RXD
2 VCT_TXD C343 1 2 100nF R381 100 1 2 C342 1 2
R3111 * C308 1 R316 100 SCART_VIN2 2,8 0.1uF R376 *
5 RD_SCALER 2 100nF DVD_C 2
C307 1 2 100nF R315 100 U305
AD3
AD2
AD1
AD0
5 WR_SCALER DVD_Y 2
VSUP3.3FE
VSUP1.8FE
R3110 * 7 14
C306 100nF R314 100 VSS VDD
5
5
5
5
2,6 KEY_AD2 1 2 SVHS_CIN 2,8
2,6 KEY_AD1_VCTI C305 1 2 100nF R313 100 SVHS_YIN 2,8 6 DDC_SCLB 1 2 1 13 ISP_CTL2 5
C304 100nF R312 100 IN 1 CNTL 1 M_DDC_CTL ISP_CTL1 ISP_CTL2 FUNCTION
1 2 SCART_VIN1 2 OUT 1 2
C914 1 2 100nF C303 1 2 100nF R311 100 VCR_IN 4 R374 0
1 2 4 5 R377 * L L L ISP desable
6 DDC_SDAB IN 2 CNTL 2
C912 1 2 100nF 3 1 2 VCT_SDA 2
VCT_CVBS 8 R378 0 OUT 2 L L H HDCP Writing
SCART_VOUT1 2 1 2 VCT_SCL 2
SCART_VOUT2 2 2,6,7,8 DDC_SCLA 1 2 8 IN 3 CNTL 3 6
9 R375 * L H L VCTi down_load
SUB_TUNER_CVBS 2 R380 * OUT 3
+3.3V_VID
TTX 256 PAGE 3-1 U303
2,6,7,8 DDC_SDAA 1 2 11 IN 4 CNTL 4 12 ISP_CTL1 5
OUT 4 10
C341 1 2 0.1uF VCT_ADB0 12 13 VCT_DB0 R379 *
C340 1 VCT_ADB1 A0 Q0 VCT_DB1 +3.3V_VID 74HC4066
U304 2 0.1uF 11 A1 Q1 14
VCT_ADB2 10 15 VCT_DB2
VCT_ADB3 A2 Q2 VCT_DB3
1 NC0 NC4 44 9 A3 Q3 17
RA301 * 2 43 VCT_ADB4 8 18 VCT_DB4 R364
VCT_ADB0 8 NC1 NC5 VCT_ADB5 A4 Q4 VCT_DB5 *
1A0 3 A0 NC6 42 7 A5 Q5 19
VCT_ADB1 7 2A1 4 41 R373 1 2 * VCT_ADB6 6 20 VCT_DB6
VCT_ADB2 6 A1 A18 R372 VCT_ADB7 A6 Q6 VCT_DB7
3A2 5 A2 A17 40 1 2 * VCT_ADB18 5 A7 Q7 21
VCT_ADB3 5 4A3 6 39 A17 1 8 VCT_ADB17 VCT_ADB8 27
VCT_ADB4 8 A3 A16 A16 VCT_ADB16 VCT_ADB9 A8
1A4 7 A4 A15 38 2 7 26 A9
VCT_CS 7 2CS 8 37 3 6 VCT_DB7 VCT_ADB10 23 32
A +3.3V_VID R368 VCT_DB0 CS OE D7 VCT_DB6 VCT_ADB11 A10 VCC A
6 3D0 9 36 4 5 25
1
47K VCT_DB1 I/O1 I/O8 D6 VCT_ADB12 A11

5 4D1 10 I/O2 I/O7 35 4 A12
1 2 RA302 * 11 34 * RA306 VCT_ADB13 28 31 VCT_PSWEQ C338
WRQ_JACK R369 1 VCC0 VSS1 RDQ_JACK VCT_ADB14 A13 WE# 0.1uF
2 12 33 29
2
* * RA305
D2 VSS0 VCC1 D5 VCT_ADB15 A14
13 I/O3 I/O6 32 1 R371 * 2 VCT_DB5 3 A15
VCT_DB2 1 8 14 31 D4 1 2 VCT_DB4 VCT_ADB16 2 22
VCT_DB3 I/O4 I/O5 VCT_ADB14 VCT_ADB17 A16 CS#
2 7D3 15 WE A14 30 A141 8 30 A17
VCT_ADB5 3 6A5 16 29 A132 7 VCT_ADB13 R370 * VCT_ADB18 1
VCT_ADB6 4 A5 A13 VCT_ADB12 A18 VCT_PSENQ
5A6 17 A6 A12 28 A123 6 OE# 24
VCT_ADB7 1 8A7 18 27 A114 5 VCT_ADB11 16
VCT_ADB8 2 A7 A11 A10 VSS Date
7A8 19 A8 A10 26 INS60256487 CONFIDENTIAL Thursday, April 27, 2006
VCT_ADB9 3 6A9 20 25 * RA303
VCT_ADB10 4 A9 NC7 Title Sheet 3 of 8
5 21 NC2 NC8 24 EN29LV040 AM0005 Size Rev Document Number
22 NC3 NC9 23 A4
* RA304 Custom <Doc>
K6R4008V1D 03. Vcti49X7R&TUNER Note
Designer
AddressDaeil Plaza #602, 528-3, Chonchun-Dong, Jangan-Gu,Suwon, Kyounggi-Do, 440-330, Korea
5 4 3 2 1
5 4 3 2 1
+
R1004 2 1 100 C362 2 1 4.7UF/16V
2 PC-AIN-L R1006 2 1 100
+
2 PC-AIN-R C363 2 1 4.7UF/16V
1
1
C520 0.01uF
U308 1 2
C961 C960 R387 * L509 HH-2012-121 L506 HH-2012-301
1.5nF 1.5nF 12 13 1 2 1 2 1 2
2
2
2
2
X0 X HDMI_AIN_L 3 ROUT+
14 R383 * R547 2 1 0/2012
X1 C549 C538 R551 0/2012 +5VS
15 3 1 2 2 1
2
2
X2 Y HDMI_AIN_R 3
C359 4.7UF/16V 11 R529 2 1 0/2012
1
1nF
1
1nF
+
R3104 2 X3 C550 C539 R530 0/2012
HDMI1_AUDIOL 1 100 2 1 R1008 2 1 100 2 1
1 R505
1
*
1
*
2
2
R1009 Y0
5 1 2C516 10K
+
R3105 2 Y1 12V-AMP C551 L510 HH-2012-121 L507 HH-2012-301 0.01uF
HDMI1_AUDIOR 1 100 2 1 2 1 100 2 Y2
4 1 2 1 2
1
1nF
1
1
1
1
D C361 4.7UF/16V Y3 ROUT- D
C360 C358 R1021 R1020 10 +3.3V_MICOM C540
1.5nF 1.5nF * * A +8V_SW_OFF +3.3V_SCALER
9
2
2
B 1nF C528 2 10.1uF 12V-AMP
*
+
6 2
2
2
EN 2,3,7,8 POP_NOISE1 Q907 12V-AMP 2 1 KSC1623 HP-SENSE 5
1
1
2
2
2
7 +5VS R922 * Q503
1
VEE C514 47uF/50V R504 10K
16 C348 C345 R561 R562 R560 R531 100 C522 C525
1
1
+
R1002 2 VDD 1uF 0.1uF C515 + 0.1uF 0.1uF
1 100 C957 2 1 4.7UF/16V R532 2 1 3.3K 2 1
2
2
2 DVD_AL 0 * *
R1003 2 1 100 47uF/50V
48
47
46
45
44
43
42
41
40
39
38
37
+
2 DVD_AR C959 2 74HC4052 U502
1 4.7UF/16V
1
1
1
2
2
2
1
1
R528 2 1 1K Q504
1
C958 C956 C553 KSC1623 Q501 R501
1
AUDIO_MUTE 5
BSRP
1.5nF 1.5nF + KSC1623 10K
BSRN
2
2
R392 47uF/50V
PVCCR1
PVCCR2
ROUTP1
ROUTP2
PVCCR3
PVCCR4
ROUTN1
ROUTN2
PGNDR1
PGNDR2
R558 2 1 1K Q506 1 36 1 2 C529
2
5 AMP_STANDBY /SD VCLAMPR
+
* KSC1623 R507 2 1 * 1 2 2 35 1uF
3 LOUD_OUT_R C513 1 RINN MODE_OUT
21uF 3 34 2 1
2
C510 C511 1 RINP MODE
21uF 4 33
+
R1005 2 1UF/16V V2P5 AVCC R541 * R539
2 SVHS-LIN 1 100 C963 2 1 4.7UF/16V C512 1 21uF 5 LINP VAROUTR 32 HEADPHONE_OUT_R 3 Q507
+
R1007 2 1 100 R510 2 1 * 1 2 6 31 1K
AV_SW_A
AV_SW_B
+
2 SVHS-RIN C965 2 3 LOUD_OUT_L LINN VAROUTL HEADPHONE_OUT_L 3 KSC1623
1 4.7UF/16V 7 30
1
1
C509 1UF/16V AVDDREF /FADE
8 29
1
C964 C962 VREF AVDD C527

9 28 1 2 300P
1
1.5nF 1.5nF VARDIFF COSC C552

10 27 R540 2 1 91K
2
2
VARMAX ROSC + 1K
11 VOLUME AGND 26 R559
12 25 C526 1 2 1uF 100uF/16V
1
1
1
+8V_SW_OFF +8V_SW_OFF AUDIO_SWB AUDIO_SWA FUNCTION REFGND VCLAMPL
1 2
2
2
R534 R536 R538

47K 8.2K 15K 49 + C534
H H VCTi 2:PC EPAD +5V_AUDIO
C 470U/16V C
BSLN
PVCCL1
PVCCL2
LOUTN1
LOUTN2
PGNDL1
PGNDL2
LOUTP1
LOUTP2
PVCCL3
PVCCL4
BSLP
R117 R115 VCTi 3:DTV Q505
2
2
2
2
4.7K TPA3004 KSC1623
13
14
15
16
17
18
19
20
21
22
23
R391 * 4.7K H L VCTi 2:HDMI1_MST6181 24
1
1
1
R390 * VCTi 3:VCR
AV_SW_A 12V-AMP
R533 R535 R537
AV_SW_B L H VCTi 2:DVD
R116 4.7K R114 4.7K * 43K 24K
1
1
Q102 Q101 VCTi 3:SCART1 C518 C521 C523

1
1
5 AUDIO_SWA 5 AUDIO_SWB 9
KSC1623 KSC1623 VCTi 2:SVHS R511 * + 0.1uF 0.1uF R542
2
2
2
1
1
C115 L L VCTi 3:SCART2 2 1 47uF/50V 1K
HEADPHONE-VOLUME
C116 *
2
2
2
2
2
2
1
1
C547 C541 3 HEADPHONE_OUT_L
1 2C517
1nF L503 1nF L502 HH-2012-301 0.01uF
LOUT- 1 2 1 2 3 HEADPHONE_OUT_R
HH-2012-121
2 2
2 2
AMP_STANDBY
2
2
C548 C542
+
R933 2 1 100 C357 2 1 4.7UF/16V 1 2C519 C532 C531
1
*
1
2 DTV_AIN_L * 5
R932 2 1 100 L508 L505 HH-2012-301 0.01uF 1uF
1
1uF
2
2
+
2 DTV_AIN_R C356 2 1 4.7UF/16V 1 2 1 2
1
1
2
2
U307 12V-AMP LOUT+ HH-2012-121
C927 C926 R386 * C546 C543
1.5nF 1.5nF 12 13 1 2
2
2
1
1nF
1
1nF
R544 *
X0 X AV_DTV_L 3
14 R382 *
1
1
1
1 R543 * 1
X1 +3.3V_MICOM +5V_1TUNER
15 X2 Y 3 1 2 AV_DTV_R 3
11 R546 R545
2
2
2
X3 * * * C545 1 10K 10K
2 0.1uF
+
R3100 2 1 100 C352 2 1 4.7UF/16V 1
VCR_ARIN_L Y0 +3.3V_MICOM R553
5 R549 2 1 5.1K
2
2
Y1 1K
B 2 R550 2 1 5.1K B
+
R3101 2 Y2 +5V_1TUNER +5V_AUDIO
1 100 C353 2 1 4.7UF/16V 4 1 2
R403
R405
1
R406
VCR_ARIN_R Y3
1
1
1 1
1 1
1
U503
10 A 1 2
C354 C355 9 +8V_SW_OFF + R227 R225 HP-R C536 2 1 8 1
B 3 HP-R IN1 BYP R548
+
* * * * R400 220uF/16V 7 2
2
2
C365
when side AV remove.1.5nF use * VO1 GND
6 U203 6 3 2 1
2
EN +5V_AUDIO VDD SD +5V_AUDIO
* 1 8 5 4
1
1
NC0 NC2 HP-L C537 VO2 IN2
7 2 7 2 1
1 2
1
VEE IN VCC 3 HP-L 1K

+
16 C347 C344 3 6 POP_NOISE 220uF/16V C533

1
TPA6110A2
+
R952 2 VDD 1uF 0.1uF R231 NC1 OUT 0.47uF
1 100 C932 2 1 4.7UF/16V 4 5 1 2
2
2
2 SCART_ALIN_L1 R953 2 * GND DCAP + C535
1 100
2
+
2 SCART_ARIN_R1 74HC4052 R552 100uF/16V
C933 2 1 4.7UF/16V *
1
1
1K
2
2
1
C938 C939 1 2 C207 1 2
1.5nF 1.5nF R389 * C544 0.1uF
2
2
*
2
Q502 * R502
KSC1623 AUDIO_MUTE 5
+
R948 2 1 100 C921 2 1 4.7UF/16V 100 R503
2 SCART_ALIN_L2 R931 2 5
1 100
AV_SW_A
AV_SW_B
+
2 SCART_ARIN_R2 C928 2 HEADPHONE_MUTE
1 4.7UF/16V
1
1
C922 C920
1.5nF 1.5nF
2
2
A A
Date
INS60256487 CONFIDENTIAL Tuesday, April 25, 2006
Title Sheet 4 of 8
AM0005 Size Rev Document Number
Custom A4 <Doc>
04. AUDIO SWITCH&AMP
Note
Designer
Daeil Plaza #602, 528-3, Chonchun-Dong, Jangan-Gu,Suwon, Kyounggi-Do, 440-330, Korea
Address
5 4 3 2 1
5 4 3 2 1
R713 0
9 INV_DIM R103 4.7K
TP108
3
3 VCT656[0..7] R710 * TP107
9 9 LCD_VDD
30 P30
R711 * 29 32
TXA0-
TXA1-
TXA2-
TXA3-
1
TXA0+
TXA1+
TXA2+
TXAC-
TXA3+
TXAC+
C707 R118 1K R113 1K P29 P32
28
1
1
HEADPHONE-VOLUME TXA3+ P28
1uF LG32;GND TP101 27
C118 C107 P27
26
2
VCT656_CLK
1uF 1uF TP104 TXA3- P26
25
2
2
TP102 P25
24
1
2RA125
3
4 22
1
2RA126
3
4 22
1
2RA127
3
4 22
P24
VCT6567
VCT6566
VCT6565
VCT6564
VCT6563
VCT6562
VCT6561
VCT6560
R121 23
R164 * P23
1M 22
2
+3.3V_SCALER TXAC+ P22
MST6_AUSCK
MST6_AUMCK
C105 1 2 22pF R101 * R163 * 21
MST6_AUSD
1
MST6_AUMUTE
MST6_AUWS
+5V_OFF P21
R102 20
8
7
6
5
8
7
6
5
8
7
6
5
Y101 * VDDP LVDS_OPTION R165 * TXAC- TP109 P20
19 P19
14.318MHZ VDDC 18
C162 TP103 P18
1 2 17
2
1
C106 22pF * P17
TXA2+
16 P16
LCD PDP TP110 15
VDD_MPLL open short open short P15
D
TXA2-
14 P14 D
13 P13
R189 R162 R162 R189 TP111 12
R192 R170 R170 R192 P12
11
266
256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
R193 R193 P11
TXA1+
10 P10
TP105 9 P9
XIN
8
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
GND
TXA1- P8
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
XOUT
7
PWM1
PWM0
LVB1P
LVB2P
LVB3P
LVA0P
LVA1P
LVA2P
LVA3P
LVB1M
LVB2M
LVB3M
LVA0M
LVA1M
LVA2M
LVA3M
VDDP3
LVBOP
VDDP4
VDDP5
GND21
GND22
GND23
GND24
GND25
GND26
GND27
P7
VDDC5
VDDC6
VDDC7
LVBOM
VI_CKB
AVDD_DVI TP106
LVBCKP
LVACKP
6
LVBCKM
LVACKM
P6
BUSTYPE
5 P5
AVDD_PLL1
VI_DATA[31]
VI_DATA[30]
VI_DATA[29]
VI_DATA[28]
VI_DATA[27]
VI_DATA[26]
VI_DATA[25]
VI_DATA[24]
1 GND1 BYPASS 192 C135 1 2 0.1uF TXA0+
4 P4
2 191 TP113 3
GND2 NC0 R136 * R714 * R189 * P3
2 RX2+ 3 DVI_R+ PWM5 190 TXA0-
2 P2 P31 31
4 189 R137 * +5V_OFF 1
2 RX2- DVI_R- PWM4 R135 * 9 INV_CTRL P1
5 GND6 PWM3 188 9 LCD_VDD
2 RX1+ 6 187 R275 J102
DVI_G+ NC1 TP701 MOLEX
2 RX1-
7 DVI_G- GPO[6] 186 UART_BALAST 9
8 185 R139 100 R712 1K
1
AVDD_DVI0 GPO[5] R175 10 HEADPHONE_MUTE 1K R181 * C729 PDP_DLP_SCL 2,6,7,8
2 RX0+ 9 DVI_B+ GPO[4] 184
10 183 R159 1K PDP_DLP_SDA 2,6,7,8
2 RX0- DVI_B- VDDP2 R183 * INV_CTRL 0.1uF
11 182
2
GND7 GND14 9
2 RXC+ 12 DVI_CK+ GND15 181 VDDC
13 180 Q208
2 RXC- DVI_CK- VDDC3 KSC1623
14 179
0 R162
0 R168
0 R169
0 R170
R104 390 AVDD_DVI1 GPO[3] HDCP_CONTROL 2
AVDD_DVI 15 REXT GPO[2] 178 DLP_RESET 9
C114 1 2 AVDD_DVI 16 177 Q104
0.1uF AVDD_PLL0 GPO[1] SW_PANEL 9 KSC1623 TP36
17 GND8 GPO[0] 176 AUDIO_SWB 4
18 175 LCD_VDD 30
2 DVI_DDC_DAT DDCD_DA GND16 4 LCD_VDD P30
2 DVI_DDC_CLK 19 DDCD_CK VDDM2 174 29 P29 P32 32
20 173 R140 22 FSDQS 28
1
GND9 DQS[0] 22 FSDATA0 P28
AVDDA 21 AVDD_ADC0 MDATA[0] 172 8 1 RA120 27 P27
22 171 7 2 FSDATA1 R184 * C367 + 26
2 PC_HSYNC_IN HSYNC1 MDATA[1] P26
23 170 6 3 FSDATA2 22uF/16V TP49 25 R715 0
2 PC_VSYNC_IN VSYNC1 MDATA[2] FSDATA3 TP50 P25
24 169 5 4 24
2
2 BLUE_IN BIN1P MDATA[3] +3.3V_SCALER P24
25 168 22 8 1 RA114 FSDATA4 R408 * 23
2 B_GND_S BIN1M MDATA[4] P23
26 167 7 2 FSDATA5 R409 * 22
SOGIN1 MDATA[5] FSDATA6 R615 * P22
2 GREEN_IN 27 GIN1P MDATA[6] 166 6 3 INV_CTRL
21 P21
2 G_GND_S 28 165 5 4 FSDATA7 TP37 TP38 20
GIN1M MDATA[7] 22 FSDATA8 9 TXA0- P20
2 RED_IN
29 RIN1P MDATA[8] 164 8 1 RA118 TXA0-
19 P19
30 163 7 2 FSDATA9 PDP OPTION TXA0+ 18
2 R_GND_S RIN1M MDATA[9] FSDATA10 TXA0+ TP39 TP40 P18
2 COM_PB_GND
31 BIN0M MDATA[10] 162 6 3 17 P17
C C949 0.047uF 32 161 5 4 FSDATA11 TXA1- 16 C
2 COM_PB BIN0P U101A MDATA[11] TXA1- TXA1+ P16
2 COM_Y_GND
33 GIN0M GND17 160 TXA1+
15 P15
C951 0.047uF 34 159 TP41 TP42 14
2 COM_Y C952 1nF GIN0P VDDM3 22 TXA2- P14
2 COM_SYNC
35 SOGIN0
MST6181 MDATA[12] 158 8 1 RA121 FSDATA12 TXA2-
13 P13
36 157 7 2 FSDATA13 TXA2+ 12
2 COM_PR_GND C954 0.047uF RIN0M MDATA[13] FSDATA14 TXA2+ TP43 TP44 P12
2 COM_PR
37 RIN0P MDATA[14] 156 6 3 11 P11
38 155 5 4 FSDATA15 TXAC- 10
AVDD_ADC1 MDATA[15] R147 22 FSDQS 2,6,7,8 PDP_DLP_SCL TXAC- TXAC+ P10
39 GND10 DQS[1] 154 TXAC+
9 P9
R127 10K 40 153 FSDQM0 TP45 TP46 8
R134 10K HSYNC0 DQM[0] TXA3- P8
41 VSYNC0 GND18 152 TXA3-
7 P7
1 2 C129 42 151 2,6,7,8 PDP_DLP_SDA TXA3+ 6 J21
0.1uF RMID VDDC4 22 TXA3+ TP47 TP48 P6 DF14A_30P_125H
43 REFP MADR[11] 150 8 1 RA119 FSADDR11 5 P5 FAN_STATUS 2
1 2 C130 44 149 7 2 FSADDR10 PDP/DLP OPTION 4
0.1uF REFM MADR[10] FSADDR9 P4 R721 100
45 GND11 MADR[9] 148 6 3 3 P3 UART_BALAST 9
46 147 5 4 FSADDR8 +3.3V_SCALER R438 * 2
GND12 MADR[8] R440 * P2 P31 31 R720 100
7 ADC-R[7..0] VDDP 47 VDDP1 GND19 146 +5V_OFF 1 P1 DLP_RESET 9
ADC-R0 48 145
ADC-R1 VI_DATA[16] VDDM4 22 FSADDR7 * R201 R718 100
49 VI_DATA[17] MADR[7] 144 8 1 RA122 ASIC_READY 2
ADC-R2 50 143 7 2 FSADDR6 2,6,7,8 VCT_SDA R719 100
VI_DATA[18] MADR[6] LAMP_STATUS 2
ADC-R3 51 142 6 3 FSADDR5 * R200 C366
ADC-R4 VI_DATA[19] MADR[5] FSADDR4 *
52 VI_DATA[20] MADR[4] 141 5 4
ADC-R5 53 140 22 8 1 RA123 FSADDR3 2,6,7,8 VCT_SCL
ADC-R6 VI_DATA[21] MADR[3] FSADDR2
7 ADC-G[7..0]
54 VI_DATA[22] MADR[2] 139 7 2
ADC-R7 55 138 6 3 FSADDR1
0 R199
0 R186
ADC-G0 VI_DATA[23] MADR[1] FSADDR0 LCD PDP DLP OPTION

56 VI_DATA[8] MADR[0] 137 5 4
ADC-G1 57 136 R152 22 open short open short
ADC-G2 VI_DATA[9] WEZ R153 22 /FSWE
58 VI_DATA[10] CASZ 135 /FSCAS
ADC-G3 59 134 R615 * * R615 +2.5V_MEM FSVREF
ADC-G4 VI_DATA[11] GND20 R200 * * R200 FSVREF
60 VI_DATA[12] VDDM5 133
ADC-G5 61 132 R148 22 R201 R201 R144
VI_DATA[13] RASZ /FSRAS +2.5V_MEM
62 131 R150 22 10K/1%
1
VDDC VDDC2 BADR[0] FSBKSEL0 DLP OTHERS

63 130 R151 22 C143
ADC-G6 GND13 BADR[1] FSBKSEL1 R141 add delete add delete
64 VI_DATA[14] AVDD_PLL2 129
0.1uF 12K/1%
2
2
8
14
22
59
67
73
79
86
96
15
35
65
95
58
ADC-G7 R718 R168 R168 R718

R719 R169 R169 R719
FSADDR[11..0]
R720 R186 R186 R720
R721 R199 R199 R721
VREF
VDD0
VDD1
VDD2
VDD3
FSADDR0 31 A0 FSDATA[31..0]
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
FSADDR1 32 R187 R187
VI_DATA[15]
DHSYNC
DE
VI_CKA
VI_DATA[0]
VI_DATA[1]
VI_DATA[2]
VI_DATA[3]
VI_DATA[4]
VI_DATA[5]
VI_DATA[6]
VI_DATA[7]
VDDC0
GND0
GND28
VDDP0
HWRESET
INT
ALE
RDZ
WRZ
DBUS[0]
DBUS[1]
DBUS[2]
DBUS[3]
DBUS[4]
DBUS[5]
DBUS[6]
DBUS[7]
DDCR_CK
DVSYNC
FIELD
DDCR_DA
PWM2
VDDC1
GND29
DQS[3]
MDATA[31]
MDATA[30]
MDATA[29]
MDATA[28]
VDDM0
GND3
MDATA[27]
MDATA[26]
MDATA[25]
MDATA[24]
MDATA[23]
MDATA[22]
MDATA[21]
MDATA[20]
MDATA[19]
MDATA[18]
MDATA[17]
MDATA[16]
DQS[2]
DQM[1]
VDDM1
GND4
MVREF
MCLKE
MCLKZ
MCLK
GND5
FSADDR2 A1 R170 R715
33 A2
FSADDR3 34 97 FSDATA0 R715 R713
A3 DQ0
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
B VDDM AVDD_PLL2 FSADDR4 47 98 FSDATA1 R713 B
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
FSADDR5 A4 DQ1 FSDATA2
48 A5 DQ2 100
FSADDR6 49 1 FSDATA3
FSADDR7 A6 DQ3 FSDATA4
50 A7 DQ4 3
R155 22 FSCLK+ FSADDR8 51 4 FSDATA5
7 HSYNC-HDMI FSCLK- FSADDR9 A8 DQ5 FSDATA6
22
R154 22 45 6
7 DE-HDMI A9 DQ6
ADC-B0
ADC-B1
ADC-B2
ADC-B3
ADC-B4
ADC-B5
ADC-B6
ADC-B7
FSCKE FSADDR10 FSDATA7
22
R156 22 36 7
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
7,8 VCLK-HDMI R157 22 FSVREF FSADDR11 A10 DQ7
37 A11
R166
R149 * 60 FSDATA8
7,8
FSBKSEL0 DQ8 FSDATA9
29 61
4
3
2
4
2
4
2
4
2
FSBKSEL0 BA0 DQ9
3
3
3
3
3
3
3
C142 1 2 * FSBKSEL1 30 63 FSDATA10
FSBKSEL1 BA1 DQ10 FSDATA11
22 1
22 1
22 1
22 1
AD0
AD1
AD2
AD3
C140 1 2 * 64
VDDP
DQ11
VDDC
FSDQS
FSDQM1
68 FSDATA12
R167
ADC-B[7..0]
DQ12
RA115
RA113 3
RA117 3
RA116 3
FSCLK- 54 69 FSDATA13
6,7 SCALER_RESET FSCLK- FSCLK+ /CLK DQ13 FSDATA14
55 71
1
FSCLK+ CLK DQ14
RD_SCALER
C168 FSCKE FSDATA15
WR_SCALER
53 72
ALE_SCALER
0.1uF FSCKE CKE U102 DQ15
28 /CS
VDDM
/FSRAS 27
2
7 HPD_CONTROL /FSRAS /RAS
FSDATA31
FSDATA30
FSDATA29
FSDATA28
FSDATA27
FSDATA26
FSDATA25
FSDATA24
FSDATA23
FSDATA22
FSDATA21
FSDATA20
FSDATA19
FSDATA18
FSDATA17
FSDATA16
HY5DU283222Q4H
FSDQS
/FSCAS 26 9 FSDATA16
AVDD_DVI AVDDA VDDP 4 AUDIO_SWA VDDM /FSCAS /FSWE /CAS DQ16 FSDATA17
4 AUDIO_MUTE /FSWE
25 /WE DQ17 10
FIELD-HDMI
FSDQS 94 12 FSDATA18
VSYNC-HDMI
4 AMP_STANDBY R1144 * FSDQS DQS DQ18 FSDATA19
+3.3V_SCALER DQ19 13
7
7
4.7K R171 R1145 0 17 FSDATA20
SUB_RFSW 3 +2.5V_MEM DQ20
FSDQM0 R145 22 23 18 FSDATA21
R143 22 DM0 DQ21 FSDATA22
56 20
1
C112 C109 C110 C111 C104 C102 C413 C113 C132 C167 1uF FSDQM1 R146 22 DM1 DQ22 FSDATA23
24 DM2 DQ23 21
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C166 +2.5V_SCALER +2.5V_MEM R142 22 57
+3.3V_SCALER AVDD_DVI VDD_MPLL AVDDA VDDP AVDD_PLL2 R1146 * DM3
2
38 74 FSDATA24
NC0 DQ24 FSDATA25
39 NC1 DQ25 75
R1141 * 1 2 40 77 FSDATA26
R174 22 MST6_AUMCK +2.5V_MEM NC2 DQ26 FSDATA27
41 78
1
+1.8V_SCALER VDDC NC3 DQ27 FSDATA28
42 NC4 DQ28 80
C173 43 81 FSDATA29
VDDM R1140 * NC5 DQ29 FSDATA30
44 83
2
22pF
1
1
1
1
1
1
VDD_MPLL AVDD_PLL2 VDDC C157 C161 C159 C160 C158 C155 NC6 DQ30 FSDATA31
U103
87 NC7 DQ31 84
88 NC8
+5V_1TUNER 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 89
2
2
2
2
2
2
NC9
MST6_AUWS
1 2 1 LRCIN SCKI 14 90 NC10
R158 1 2 22 2 13 1 2 R1142 * 91
A C108 C141 C137 C127 C169 C165 C133 C103 C101 C163 C139 C164 C136 C138 C134 MST6_AUSD R172 1 DIN FORMAT NC11 A
MST6_AUSCK 2 22 3 BCKIN DEEMPH 12 R176 1 2 10K 93 NC12
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R173 22 4 11 R177 10K +2.5V_MEM
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSS0
VSS1
VSS2
VSS3
MCL
C170 C171 C172 NC0 NC1

5 CAP MUTE 10 1 2 MST6_AUMUTE
R3102 2 11K 22pF 22pF 22pF 6 9 R178 22
5
4 HDMI1_AUDIOR VOUTR VOUTL

11
19
62
70
76
82
92
99
16
46
66
85
52
7 8
2
1
1
1
1
1
1
1
1
1
1
1
1
GND VDD C175 C176 C149 C144 C154 C153 C152 C151 C150 C145 C146 C147 C148
R396 +
1
* 0.1UF 10uF/16V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
2
2
2
2
2
2
2
2
2
2
2
1
1
1
WM8725
+ C174 DCAP_50D250
2
10uF/16V
1
2
2
2
2
Date
1 2
INS60256487 CONFIDENTIAL Thursday, April 20, 2006
2
R3103 1K HDMI1_AUDIOL 4
Title Sheet 5 of 8
R399 AM0005 Size Rev Document Number
* Custom A4 <Doc>
05. MST6181A & DDR SDRAM Note
1
Designer
Address Daeil Plaza #602, 528-3, Chonchun-Dong, Jangan-Gu,Suwon, Kyounggi-Do, 440-330, Korea
5 4 3 2 1
5 4 3 2 1
+3.3V_MICOM
+3.3V_MICOM
1K R258
1
C202
D 1uF R252 2 1 100 D
SDI PDP ONLY
2
R204 2 1 100 LEDWARNING4
+3.3V_MICOM R253 2 1 100 LEDRED 2
+5VS R206 1 2 10K R247 2 1 * SCALER_RESET 5,7
R208 1 2 10K R254 2 1 *
SW_REG_EN 9
+3.3V_MICOM
1
1
2 FAN_STATUS
R5 R6 2 M_DDC_CTL R207 1 2 *
2.4K 2.2K 2 LAMP_STATUS CHK_DSUB 10K R237
U1 2 ASIC_READY CHK_DVI 10K R239
1 8 ASIC_READY 10K R210
2
NC0 NC2 LAMP_STATUS 10K R212
2 7
1 2
IN VCC * DTV_IDENT 10K R214
3 NC1 OUT 6 2 CHK_DSUB 1 2 R236
R13 4 5 THD_SS 10K R251
1K GND DCAP ACD 10K R216
M51958
6
5
4
3
2
1
44
43
42
41
40
2
1 2 C2 2 CHK_DVI * 1 2 R238 U202 KEY_AD2 1K R233
C 0.1uF KEY_AD1 1K R259 C
NC5
P1.1
P1.2
P1.3
VCC
+3.3V_MICOM C208 ISP_CTL1 1K R250
* ISP_CTL2 1K R269
P1.0/ET2
1
DA4/P5.4
DA3/P5.3
DA2/P5.2
DA1/P5.1
DA0/P5.0
7 39 R248 2 1 *
2
DA5/P5.5 P1.4 TW_RESET 8
R240 2 1 * 8 38 R249 2 1 * VCT_RESETQ 3
R241 2 P5.6/HSCL2 P1.5 R209 *
1 * 9 P5.7/HSDA2 P1.6 37 2 1 ISP_CTL1 2
R242 2 1 0 10 36 R211 2 1 * ISP_CTL2 2
R232 1 * RST P1.7
2 R230 1 2 * 11 35
1
1
2,3,7,8 VCT_SCL HSCL1/RXD/P3.0 NC2

12 34 C209 C210
R224 1 * * NC1 NC3 1uF 100nF
2,3,7,8 VCT_SDA 2 R226 1 2 13 HSDA1/TXD/P3.1 MTV512 NC4 33
R919 1 2 100 14 32
2
2
2,3 IRRCVR P3.2/INT0 VSYNC

1 2 15 P3.3/INT1 P6.7 31 R213 2 1 * DTV_IDENT
R243 1 2 4.7K 16 30 R246 2 1 100
R244 1 4.7K P3.4/T0 P6.6/CLK01 THD_SS
2 17 P3.5/T1 P6.5 29 R215 2 1 100 ACD
R245 4.7K
2
2
C205 C206
+3.3V_MICOM 68P 68P
B B
1
1
X1 5V_D 4.7K R218 +5V_OFF
P7.6/CLK02
P7.7
X2
X1
VSS
NC0
P6.0/AD0
P6.1/AD1
P6.2/AD2
P6.3/AD3
P6.4
15K R228
X2
18
19
20
21
22
23
24
25
26
27
28
1 2 R221 1M
2 DVB_ON R270 1
2 GPIO 2 100
R271 1 2 100 R217 2 1 100
2 IRR_MUTE R272 100 5V_D
R219 1 2 * SCART_AVSW2 2
X2
X1
R220 1 2 * SCART_AVSW1 2
1 2 R924 2 1 * KEY_AD2 2,3
X201 R921 2 1 *
1
1
KEY_AD1 2,3
12MHz
OTHER SDI PDP C203 C204 R222 2 1 100
33pF 33pF TV_MENU 2
R223 2 1 100
2
2
DVB_MENU 2
C208 1nF DELETE C208 1 2

R274 1 2 4.7K
R273 4.7K
A A
+3.3V_MICOM
Date
INS60256487CONFIDENTIAL Thursday, April 20, 2006
Title Sheet 6 of 8
A4 A4 <Doc>
06. MICOM Note
Designer
5 4 3 2 1
5 4 3 2 1
TW_VDDE TW_AVDPLL
2 1 +5V_2TUNER
R331 TW_AVD
470 TW_VDD
Q301 2 1
KSC1623 VCT_CVBS 3
R310 75
R330 2 1 * 100 2 1 R618 +5V_2TUNER
11
53
74
3
60
72
33
44
46
SUB_CVBS U405 2,3,6,7 VCT_SCL
1 R320 2 2,3,6,7 VCT_SDA
100 2 1 R617
1
1
D D
1K
AVD0
AVD1
VDD0
VDD1
VDD2
2 4 5RA405 C621 C622 *
VDDE0
VDDE1
VDDE2
* R464 * VD[0] 20pF 20pF
AVDPLL
2 1 C443 31 1 3 6 *
2
2
* R463 * VIN0 VD[1] R619
2 1 C442 32 VIN1 VD[2] 80 2 7
VD[3] 79 1 8
100 R328 100nF 2 1 C444 42 78 4 5 RA404
1
2,3 SVHS_CIN 100 R459 100nF 2 CIN0 VD[4]
1 C436 43 CIN1 VD[5] 77 3 6 *
5 DVD_C 76 2 7
100 R484 100nF C439 VD[6] U601
RF_CVBS 2 1 35 MUX3 VD[7] 75 1 8
5 DVD_Y 100 R483 100nF 2 1 C440 36 69 4 5 +5V_2TUNER 1 2
100 R461 100nF C438 MUX2 VD[8] L605 COIL-3.3UH
2 1 37 68 3 6RA403
1
1
2,3 SVHS_YIN 100 R460 100nF C437 MUX1 VD[9]
SUB_CVBS 2 1 38 MUX0 VD[10] 67 2 7 * ADC-B[7..0] 5,7 1 NC1
66 1 8 + C618 + C619 C620 2
VD[11] ADC-B0 NC2
VD[12] 64 4 5 3 NC3
63 RA402 3 6 ADC-B1 * 470U/16V 0.01UF 4
2
2
VD[13] ADC-B2 NC4 ADDRESS:C6
VD[14] 62 47 2 7 5 IFOUT
R467 * 2 1 14 61 1 8 ADC-B3 6
R466 * AMCLK VD[15] ADC-B4 NC5
2 1 15 AMXCLK VD[16] 58 4 5 7 NC6
R457 * 2 1 16 57 3 6 ADC-B5 8
R455 * ASCLK VD[17] ADC-B6 AGC
2 1 17 ALRCLK VD[18] 56 2 7 9 SAS
55 1 8 ADC-B7 4.7UF/16V C612 10
VD[19] SCL
+
19 RA401 47 4 RF_MONO 1 2 100 1 2 R613 11
TMODE SDA
12
1
C 5V/B+ C
R454 13 2 1 R468 * 13
1
FIELD SIF
5 XTI VSYNC 10 4 5 14 NC7 CHASSIS3 21
* 9 3 6 RA406 C613 15 20
X401 27Mhz HSYNC 1.5nF AUDIO_OUT CHASSIS2
8 2 7 16 19
2
DVALID * AFT CHASSIS1
2 1 6 7 1 8 17 18
2
XTO MPOUT VIDEO_OUT CHASSIS0
C433 XTAL C434
1 2 73 TCLW3001PC29A(H)
27p R456 1M 27p CLKX1 C614
CLKX2 70 2 1 VCLK-HDMI 5,7
+33V_T2 1 2 HH-2012-121 10UF/50V
R450 47
1
34 2 1 L604
YBOUT C611 +
21 NC0
22 R462 *
NC1 0.01UF
23 54 2 1
2
NC2 INTREQ
24 NC3
25 51 R478 * TW_RESET 6
NC4 RST# 100 R474
26 NC5 SDAT 50 VCT_SDA 2,3,6,7
27 49 100 R476
NC6 SCLK VCT_SCL 2,3,6,7
28 48 R612 68
NC7 SIAD0
29 47 2 1
1
NC8 PDN R475 RF_CVBS
20
1
1
NC9 R477
B * R611 B
* 75
AVS0
AVS1
VSSE2
VSSE1
VSSE0
VSS0
VSS1
VSS2
VSS3
YGND
AVSPLL
CGND
2
TW9906
4
2
2
30
40
71
59
12
18
52
65
39
45
41
TW_VDDE
+2.5V_TW TW_VDD +3.3V_TW
R465 * R452 * +3.3V_VID +3.3V_TW DELETE : THIS PAGE & POWER OPTION
2 1 TW_VDD 2 1 TW_VDDE R479 * 1 TUNER
2 1 CHANGE : U639 TECH2949PG40B(D)
C430 C447 C435 C431 C429 C432
DELETE :
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 2 TUNER
CHANGE : U639 TECH2949PS40A(D), U602 TCPW3001PC29A(H)
+2.5V_VID +2.5V_TW
R480 *
TW_AVDPLL 2 1
A +2.5V_TW L404 TW_AVD +3.3V_TW L403 A
COIL-10UH COIL-10UH
1 2 1 2 TW_AVDPLL
Date
INS60256487CONFIDENTIAL Friday, April 07, 2006
C446 C441 C445 Title Sheet 7 of 8
0.1UF 0.1UF 0.1UF Custom A4 <Doc>
2 TUNER PAGE Note
Designer
5 4 3 2 1
5 4 3 2 1
DELETE THIS WHEN THE SS PDP 9-4

+8V_SW_OFF
+5V_DVD_CD +33V_2TUNER
J701 R266 0 U715
1 +5V_OFF RC1117-3.3 +3.3V_SCALER
1
P1 P_CTRL1 5 C775
P2 2 TAB 4
3 3 2 0.1uF C781 0.1uF C782 0.1uF
P3 IN OUT R770 10K
4 1 2 1 2
2
+5V_OFF_CD
GND
P4
5
1
P5 C792SOT-223 U712 D701 BAV99 D702 BAV99 D703 BAV99 +33V_T
6
1
P6 +5VS
7 0.1uF R772 4.7K
1
P7 C780 P1 P14
8 R1851 2 0 1 2 1 2 1 2
2
P8 12V-AMP_CD P2 P13
9 1nF
1
P9 +12V_CD P3 P12
10 C776 0.1uF 0.1uF ZD707
2
3
3
3
1
P10 +12V_DVD_CD P4 P11
11 U705 1 2 1 2 1 2 C783 R771 C779
P11 INV_DIM 5 +1.8V_VCTi P5 P10 0.1uF UDZ33B 0.1uF
12 RC1117-1.8
2
P12 INV_CTRL 5 +5V_OFF P6 P9 C777 C778 0.1uF 100K
D 4 D
2
COND12P +3.3V_SCALER U716 R777 0 TAB P7 P8
3 2
1
+3.3V_VID IN OUT
RC1117-3.3
1
1
4069
GND
R1871 2 * +5V_OFF 4 C713
TAB 0.1uF SOT-223 C714 + C715
3 2
2
1
R1881 IN OUT R778 100uF/16V
2 *
GND
0.1uF
1
C794SOT-223 *
1
LCD 9-1 0.1uF
2
+3.3V_OFF_SS
U713
+5V_1TUNER RC1117-2.5 +2.5V_SCALER
U714 +5V_OFF 4
+5V_OFF +2.5V_VID TAB
RC1117-2.5 3 2
IN OUT
4
1
GND
TAB
3 2
1
1
IN OUT SOT-223 +
1
1
1
1
GND
C626 C730 C784 C785 C156
1
1
+5VS
SOT-223 + 0.1uF 100uF/16V 0.1uF
1
2
2
2
COND10P_35155-1000
R182 0 C787 C786 C178 220uF/16V 0.1uF
2
2
U706 0.1uF 100uF/16V 0.1uF
2
2
2
P10 10 1 2 +5V_DVD_SS
MOLEX 3 2 +3.3V_MICOM
P9 9 +12V_DVD_SS VCC OUT +3.3V_MICOM
P8 8 +12V_SS +12V_DVD_CD +12V_DVD TAB 4
+3.3V_OFF_SS +3.3V_SCALER
1
+12V_DVD_LG
GND
P7 7 C720
1 2
1
1
1
P6 6 12V-AMP_SS
C716 + 0.1uF C724 C721 C718
1
P5 5 +12V_DVD_SS +5V_DVD_CD
4 R190 0 +5V_DVD_SS +5V_DVD RC1117-3.3 220uF/16V
P4 100uF/16V 0.1uF 0.1uF
2
2
2
2
P3 3 +3.3V_OFF_SS +3.3V_VID +5V_DVD_LG
2 U704
P2 +12V +1.8V_SCALER
1 2 RC1117-1.8
P1 1 +3.3V_SCALER +3.3V_VID +5V_OFF
+5V_OFF_LG TAB 4
J702 R191 0 3 2
1
+5V_OFF_SS +5V_OFF IN OUT
1
1
1
+5V_OFF_CD
GND
R775 0 C710
1
1
COND11P_35155-1000
+ 0.1uF SOT-223 C712 + C711
2
1
1
1
+12V_CD
11 C725 C791 + C177 C793 + C179 R776 100uF/16V
2
P11 +5V_OFF_SS +12V_SS +12V

10 220uF/16V 100uF/16V 0.1uF 100uF/16V 0.1uF 0.1uF
2
2
P10 +12V_LG
C MOLEX 9 * C
2
2
2
2
P9 +3.3V_OFF_SS +5VS P_CTRL1 5
P8 8 12V-AMP_CD
P7 7 12V-AMP_SS 12V-AMP
6 12V-AMP_LG R257 1K R263 * +3.3V_OFF_SS
P6 R256 1K
P5 5
P4 4 P_CTRL_SS 5
3 KSC1623
P3 R255 1k Q203 Q204
P2 2 +5VS 6 SW_REG_EN
1 KSC1623 +5V_OFF
P1 THD_SS 5
1
R264 * P_CTRL 5 R268 *
J921
+ +5V_1TUNER
C723
2
SS PDP 9-2 220uF/16V
2
R267 0 R195
P_CTRL_SS 5
*
U702 78M08 +8V_SW_OFF U95

1
+12V 1 IN OUT 3 1 2 3 VCC OUT 2

4
G
R194 * TAB
1
GND
C722
4
C717 + 0.1uF
1
RC1117-5
100uF/16V
2
J913
COND3P
5V_IDTV
3
2
1
COND7P_SMW250
COND4P_SMW250
R229 0 7
U309 P7 ACD 5
+5V_OFF 1 2 P6 6 P_CTRL1 5 P4 4 +24V_LG
+12V_CD 1 S1 D1 8 LCD_VDD P5 5 +5VS P3 3
2 7 4 2
1
B S2 D2 5 P4 P2 B
3 6 3 1
1
R706 47K R707 47K S3 D3 + C728 P3 SW_PANEL_P 5 P1
4 G D4 5 P2 2 5V_D 5
P1 1 J705
1 2 C726 0.1uF
2
2
IRF7404
C117 1uF J706 NORMAL I_DTV
220uF/16V
KSC1623
10k R120 Q207 SMW250 SMAW250 +5V_OFF
5 SW_PANEL
LCD 9-7 COND12P_SMW250 R179 +33V_2TUNER

12 +5V_DVD_LG 0 +33V_T2
P12
P11 11 +5V_OFF_LG 9
10 R614 4.7K ZD601 C615 +5V_2TUNER
P10 SW_PANEL_P UDZ33B 0.1uF +12V
9
2
P9
8
2
P8 R262 9 R197
7
1
P7 R180 R198
P6 6 +12V_DVD_LG SW_PANEL *
5 +12V_LG * 1K R708 *
R203 0 P5 1K U703 78M08 U96
4
2
1
5V_IDTV P4
1 2 3 1 3 1 2 3 2
1
P3 R161 IN OUT VCC OUT

2 4
G
P2 R196 * TAB
1 470
1
GND
P1 Q206 C737
4
J704 KSC1623 +5V_2TUNER C719 + 0.1uF

1
AP1501_ADJ U701 RC1117-5

Q103 100uF/16V
2
6 KSC1623
P6
P1
P2
P3
P4
P5
1
1
C625 C731
1
2
3
4
5
+24V_LG +12V_DVD_CD R702 LG PDP 9-3
1K 1% 220uF/16V 0.1uF
2
2
2 TUNER 9-5
2
2
R701 IDTV LCD 5V LG PDP LCD 12V
* * 9.1K 1%
L70133UH R192 * ADD DELETE ADD DELETE ADD DELETE
A A
1 2 1 2
R193
1
R202
1
12V-AMP_LG
U701 AP1501 ADJ R193 U701 AP1501 ADJ R202
1
1
R202 0 OHM R192 0 OHM R203
1
1
C705 C706 + C524 + C530 ZD701 R203 0 OHM R229 R193 0 OHM
2
C733
0.1uF 47uF/50V * *
1
0.1uF MBRS340 R701 9.1K 1% R192 R701 9.1K 1% OHM J913
2
2
2
2
1
1
C732 C795 C796 R702 3K 1% R702 1K 1% OHM
1
1
+ +
C524 47uF/50V C524:IDTV_only
470U/16V 0.01uF 0.001uF
2
2
2
2
IDTV LCD 5V PANEL, LG PDP 9-6 Date
INS60256487CONFIDENTIAL Wednesday, April 12, 2006
Title Sheet 8 of 8
A2 A4 <Doc>
<OrgAddr4> Note
Designer
5 4 3 2 1
__________________________________________________________________________________________________________________
41
__________________________________________________________________________________________________________________
42
__________________________________________________________________________________________________________________
43
__________________________________________________________________________________________________________________
44
__________________________________________________________________________________________________________________
__________________________________________________________________________
1 2 3 4 5 6 7 8 9 10 11 12
TP1 R304 R305

150K TP10 150K Q300
BC337 D301
S300
J315 Comment
J319
STDBY 1
TP7 10uF/25V D321 BYV36C
TP18 TP50
R301 C356 33V C322
2
56K C317 R333 47uF/50V
100nF 3
TP14 4.7K TP19 5VMAIN
D322
D318 12V TR30 J330 J331 4
2.4V TP15 R339 R308
C345 6 15 TP37 TP43 J329
Q302 4.7K 100R 5
TP11 TP20 TP26 C305 5VSTBY
D315 R341 12V
33pF BC848B 270R D302 220pF 6
12V L307
IC30 MBR20200CT J324
1 8 5 13 TP30 20uH 2.5A 7
NC VCC C303 TP34
C351 C354
TP38
TP41
TP21 L302 220pF R327
3 C329 C314 1000uF/25V C347 C332 C312 8
2
100nF/50V 2.2K 12V
2 7 R306 BEAD 16 R309 2200uF/25V 100nF 100nF 1000uF/25V 100nF
PCS OUT TP25
TP6 100R L304 100R TP35
9
Power Board
T300
HS33 HS34 D300 C325
D R307 BEAD D
SMPS HEATSINK SMPS HEATSINK 3 6 1 SPP07N60 680pF 2000V 10
RZI GND D308
TP2 TP8 TP9 33R TP13
1N4148 L301 BYW76 13 A_DIM 11
J307
4 5 C306
SRC OFC BEAD
TP3
10pF BL_ON/OFF 12
1
3
ICE1QS01 TP16
14
R300 C341
C300 C301 TP22 POWER
8.2K 33nF 630V TP27
10pF 47nF R329
68K 1W
R302 J313 J303 L303
VB VB2 1 12
TP4 1M TP23 BEAD TP24
R319 C324 TP28 F301 R320 TP31
C302 D325
1.2M
C328 C361 9
330pF 1N4007 8.2nF 400V 8.2nF 400V 5VMAIN
5A 100R
C336
D305 D310 220pF
270uF/400V 1000uF/16V 1000uF 16V L308 24V 24V
11 TP32
4
10uH 7A TP36 S305 S302
MBR1045 MBR1045 1 1
TP5 R310 C948
L311 C318 C330 C315 C334 C316
12K TP53 TP55
PFC 10 100nF 1000uF/16V 100nF 2 2
J300
3
TP12 TP17 TP29
1nF/1KV IC36 3 3
C320
1nF/1KV 4 4
100nF 275VAC 11
S303 L800 100nF 275VAC L310
F300 5 5
1 1 4 2 3
6
C357 J301 TP96
TP56 T3.15AL/250V TP58 TP59 TP61 TP63 4 1 BGND 6 6
2 VR30
C337 SMPS LCD MAIN
TP65 TP97
V320 7 7
POWER 2 3 1 4
TP92
TP57 TP60 TP62 C321 8 8
C308 2X27mH 2X27mH 1nF/1KV
TP98
100nF 275VAC C319 9 9
RS406 5VSTBY 5VMAIN
TP64
10 10
2
1nF/1KV TP74 TP78
D304 D306 TP99
11 CON10_W
BAT85 BAT85
TP93
TP75 TP79 BL_ON/OFF 12
R344 R345 13
47R 47R
5VOC
A_DIM 14
IC37 TP95
CON14
6 1
6 1 TP76
C359 C343
R314 J309
J314 5 2 100nF 10uF HS30 HS32 HS35
5 2 1K
1 2 POWER HEATSINK POWER HEATSINK POWER HEATSINK
4 3 R315
4 3 OPS.
TP72 J308 470R TP83 TP88
TCDT1101G
R322 R331
C C342 C344 C358 C
12V
2
J305 C338 47pF 15nF 5.6K 1% 47nF 4.7K 1%
S301
TP67 TP70
TP85
4
1nF 400VAC
R321
C339
TP80 33K 3
J311
FD1 FD2 FD3
TP68 5VMAIN 2
1nF 400VAC
D303 TP89
1
C340 TL431
R330 R336
TP69 TP71 22K 1% 1K 1% CON4
2.2nF 400VAC
R303 T301 R317 STB

4.7M 1/2W BC848B TP77 1K TP81 R346 STDBY
R326
1K TP84 3.3K TP86
C206 T302 R347
GND BC848B 33K
1nF 400VAC R203

1K 5VSTBY
2.2nF 400VAC TR20 D200
L200
4 6 J320 J322
TP66 TP73 TP82 20uH 2.5A TP87
R204 C202 STPS5L40 C204
45
68K 1W C210 C211 C205

470uF/35V 100nF 470uF/16V 100nF
TP112
D201
BYV36C
1 10
TP110 TP116
SMPS STANDBY LCD
8
TP113
IC21
GND VST
VFB VCC
D
FSD200 C213
33uF
GND
GND
IC20
1
6 1
6 1 TP117
R201
C203 5 2
100nF
5 2 1K
D326
4 3 R202
1N4007 4 3
TP118 470R TP122
TCDT1101G TP125
C207 C208 R200 C200
100uF/400V
47pF 15nF 2.4K 1% 47nF
TP105
C362 TP123
B R343 B
1.2M R205
33K
D202 TP126
TL431
R337
R316 R332 VB3 2.4K 1%
150K TP101150K Q301 TP111
BC337 D401
TP100 10uF/25V TP106 TP114

C360 D323 BYV36C
C335 R334 33V C410
100nF
TP103 4.7K 47uF/50V 5VOC
D319 TP107
2.4V D324
C304 TP104 R340 8.2V TR40 TP127
3 D309
R402 1N4148
56K TP102 Q303 4.7K TP108
22pF D317 R342
BC848B 270R 11 R412 TP128
12V
IC40 TP119 10R TP120
R335 24V
D404 C416 2.7K
1 8 4
NC VCC 1nF 1KV
MBR20200CT
TP109 L400 L402
1
2
J327
2 7 R404 BEAD 7 10uH 7A
PCS OUT L305 TP115 TP121
C417 TP124 TP129
TP132 TP134 100R
D400 T401 BEAD C413 1nF 1KV C414 C405 C420 C406
J304 J302 3 6 R405 1 SPP07N60 D402 680pF 2000V 12 R413 2200uF/35V 100nF 470uF/35V 100nF
RZI GND BYW76
TP130 TP135 TP136 33R TP137 L306 TP144 10R TP146
1N4148
4 5 BEAD
SRC OFC C307
TP131 10pF
3
ICE1QS01 C411 TP138

8
R400
C400 C401 33nF/630V
8.2K
10pF 100nF R410
J317
68K 1W
R403 L401
J316 6
TP133 1M TP139 BEAD TP140
C403 C404 C402 SMPS LCD BL
330pF 8.2nF 400V 8.2nF 400V
5VOC
J306 J310 J318

IC41 TP141
6 1 D320 C408 C421
6 1 R416 100nF 10uF
5.1V 1K
J312 5 2 24V
5 2
4 3 R417 J323
4 3
TP142 470R TP149
TCDT1101G
A C418 C419
R419
C409
A
30K 1%
47pF 15nF 47nF
R418
TP145 33K
D403
TL431 TP148
R338
3.4K 1%
T400 R414 J328 STB J326 J325

BC848B TP143 1K TP147
R415
1K
1 2 3 4 5 6 7 8 9 10 11 12
__________________________________________________________________________________________________________________
__________________________________________________________________________
46
__________________________________________________________________________________________________________________
__________________________________________________________________________
47
__________________________________________________________________________________________________________________
__________________________________________________________________________
48
1 2 3 4 5 6
D D
Side AV
S100
1
L100
2 L
4 22uH
R
5 L101
22uH
8
C100 C101 C102 C103 R100 R101

7
220nF 220nF 100nF 100nF 4.7R 4.7R
3
HEADPHONE 7P AGND AGND AGND AGND C104 C105

C 10nF 10nF C
S102 S103
AGND 12
1 L107 AGND AGND
BEAD 11
2
C111 10
V 10pF
AV_CVBS 9
AGND
49
S104 8
1 L110 R102 AV_L 7

BEAD 15K
2 6
C109 C113 C115
L 1nF 1nF 1nF AV_R AGND 5
AGND AGND AGND 4

AGND
S105
3
1 L111 R103
BEAD 15K 2
AGND
2
C110 C114 C116 1
B B
R 1nF 1nF 1nF
AGND CON5
AGND AGND AGND
2
1
R104 C100
S106
S_VHS 75R 47pF
5
6
AGND AGND
R105 C101
3
4
75R 47pF
AGND AGND AGND
A A
__________________________________________________________________________________________________________________
1 2 3 4 5 6
__________________________________________________________________________
__________________________________________________________________________________________________________________
B
4
4
220R 1/6W
SW07
R007
P(+)
GND
470R 1/6W
3
3
SW06
R006
P(-)
820R 1/6W
SW05
V(+)
R005
MULTI BUTTON
1.5K 1/6W
SW04
R004
V(-)
2.7K 1/6W
SOURCE
SW03
R003
5.6K 1/6W
MENU
SW02
R002
2
2
100nF
C002
100nF
C001
To main pcb
To infra pcb
2
1
S002
S001
1
1
D
A
C
__________________________________________________________________________
50
__________________________________________________________________________________________________________________
Infraled
A
C
B
4
4
3
3
GND
100uF
1
C001
VCC
2
IR01
IR
3
IR
LED1
LED
15K 1/6W
STBY
SW01
R004
33R 1/4W
470R
R003
R001
100nF
C002
2
2
GND
1
1
S001
S002
INFRA RED To mbutton pcb

1
1
D
A
C
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7. TROUBLESHOOTING
FAULT TRACING DIAGRAM FOR POWER SUPPLY
NO
Check 220 V AC Mains Check AC Power Cable is Plugged
YES
NO Check X102 Fuse

Check C 020 Voltage
YES
NO Check T530 and Peripheral

Check 5VSTBY
Components
YES
NO
Check 5V_OFF Check P_CTRL Pin
LOW HIGH
YES
StandBy Normal Mode
NO Mode Check Components
Check 24V,33V,12V
For 5V
8V
YES
Check Related Components for
Defective Outputs
NO
Check 3.3V,2.5V and 1.8V
YES
Check Related Components
POWER IS OK
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52
__________________________________________________________________________________________________________________
8.DATA SHEETS
Tuner Data Sheets
Specification
specification : PAL FST TU SEM Model No. TECH2949PS40A(D)
1. General Characteristics
1-1. Receiving System : CCIR Standard system
1-2. Channel
BAND START CH FREQ END CH FREQ
VHF Low E2 45.75 S6 140.25

VHF High S7 147.25 S36 423.25
UHF S37 431.25 E69 855.25
1-3. Intermediate Frequency

SYSTEM PICTURE COLOR SOUND
B/G 38.9 34.47 33.4
1-4. Input/Output Impedance

Input Impedance 75 Unbalanced
Output Impedance 1 Balanced
For Aymmetrical use of IF output, IF2 must be connected with 56 load to ground.
1-5. Tuning System : Frequency Synthesized Type

1-6. Band Change Over System : PLL System
1-7. Terminals for External Connection
NO TERMINAL NAME DESCRIPTION
1 AGC AGC Voltage input
2 NC No Internal connection
3 SAS Serial Address Selection
4 SCL Serial Clock Line
5 SDA Serial Data Line
6 NC No Internal connection
7 BP B+ for Internal IC
8 ADC Analog/Digital Converter input
9 BT Tuning Voltage supply
10 IF2 IF output 2
11 IF1 IF output 1
12 ANT VHF/UHF signal input
13 SUB P/J VHF/UHF signal output for PIP sub-tuner.
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__________________________________________________________________________
53
__________________________________________________________________________________________________________________
Specification
specification : PAL FST TU SEM Model No. TECH2949PS40A(D)
2. Limiting Values
2-1. Environmental condition

PAR DESCRIPTION MIN TYP MAX UNIT
TS Storage Temperature -20 +80
TO Operation Temperature -15 +65
RH Relative Humidity for operation 90 %
2-2. Electrical conditions

PAR DESCRIPTION MIN TYP MAX UNIT
VB+ B+ Supply Voltage 4.75 5.0 5.5 V
B+ Supply Current (LNA OFF) 90 120
IB+
B+ Supply Current (LNA ON) 120 150
VFM 2nd Input activationg voltage 4.75 5.0 5.5 V
VAGC AGC Input Voltage 4.0 4.5 V
VT Tuning Supply voltage 30 33 35 V
VRIPPLE Permissible ripple (20 to 500 ) 5 P-P
VSCL Serial clock input Voltage (see Note1) 5.5 V

VSDA Serial data input Voltage (see Note1) 5.5 V
Note 1. I2C bus electrical requirements for operation are in 7-2.
3. Internal Semiconductors
3-1. Tuner section

PARTS MAIN SUB EQUIVALENCE
Mixer+Oscillator+PLL IC SN761672A
RF amplifier UHF BF1202 BF909 BF2030
VHF BF904 BF904WR, BF909WR
Tuning diode UHF BB555 BB179 HVU202A, 1SV214
VHF BB659C, BB689 HVU300A, HVU306A
Tuning correction diode BB555 BB179 HVU202A, 1SV214
3-2. LNA section

PARTS MAIN SUB EQUIVALENCE
Pre-amplifier NE34018 NE38018
_______________________________________________________________________
__________________________________________________________________________
54
__________________________________________________________________________________________________________________
CAT24WC01/02/04/08/16
1K/2K/4K/8K/16K-Bit Serial EEPROM
FEATURES ■ Self-Timed Write Cycle with Auto-Clear

■ 400 KHz I2C Bus Compatible* ■ 1,000,000 Program/Erase Cycles
■ 1.8 to 6.0Volt Operation ■ 100 Year Data Retention
■ Low Power CMOS Technology ■ 8-pin DIP, 8-pin SOIC or 8 pin TSSOP
■ Write Protect Feature (Also available in new Lead-Free packages)
— Entire Array Protected When WP at VIH
■ Commercial, Industrial, Automotive and
■ Page Write Buffer Extended Temperature Ranges
DESCRIPTION
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K- 08/16 feature a 16-byte page write buffer. The device
bit Serial CMOS EEPROM internally organized as 128/ operates via the I2C bus serial interface, has a special
256/512/1024/2048 words of 8 bits each. Catalyst’s write protection feature, and is available in 8-pin DIP, 8-
advanced CMOS technology substantially reduces de- pin SOIC or 8-pin TSSOP.
vice power requirements. The the CAT24WC01/02/04/
PIN CONFIGURATION BLOCK DIAGRAM

DIP Package (P, L) SOIC Package (J, W)
EXTERNAL LOAD
A0 1 8 VCC A0 1 8 VCC
DOUT SENSE AMPS
A1 2 7 WP A1 2 7 WP SHIFT REGISTERS
3 6 3 6 ACK
A2 SCL A2 SCL
VSS 4 5 SDA VSS 4 5 SDA VCC
VSS WORD ADDRESS COLUMN
5020 FHD F01 BUFFERS DECODERS
TSSOP Package (U, Y)

MSOP Package (R, Z) (MSOP and TSSOP available for CAT24WC01,
SDA START/STOP
CAT24WC02 and CAT24WC04 only) LOGIC
NC 1 8 VCC A0 1 8 VCC
NC 2 7 WP A1 2 7 WP
3 6 SCL 3 6 XDEC E2PROM
NC A2 SCL
VSS 4 5 SDA VSS 4 5 CONTROL
SDA WP
LOGIC
PIN FUNCTIONS
Pin Name Function DATA IN STORAGE
A0, A1, A2 Device Address Inputs

SDA Serial Data/Address HIGH VOLTAGE/
TIMING CONTROL
SCL Serial Clock
WP Write Protect SCL STATE COUNTERS
VCC +1.8V to +6.0V Power Supply A0 SLAVE

A1 ADDRESS
VSS Ground A2 COMPARATORS
24WCXX F03
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
__________________________________________________________________________
55
__________________________________________________________________________________________________________________
Philips Semiconductors Product specification
Quad bilateral switches 74HC4066; 74HCT4066
FEATURES GENERAL DESCRIPTION

• Very low ON-resistance: The 74HC4066 and 74HCT4066 are high-speed Si-gate
– 50 Ω (typical) at VCC = 4.5 V CMOS devices and are pin compatible with the
HEF4066B. They are specified in compliance with JEDEC
– 45 Ω (typical) at VCC = 6.0 V
standard no. 7A.
– 35 Ω (typical) at VCC = 9.0 V.
The 74HC4066 and 74HCT4066 have four independent
• Complies with JEDEC standard no. 8-1A analog switches. Each switch has two input/output pins
• ESD protection: (pins nY or nZ) and an active HIGH enable input pin
HBM EIA/JESD22-A114-A exceeds 2000 V (pin nE). When pin nE = LOW the belonging analog switch
is turned off.
MM EIA/JESD22-A115-A exceeds 200 V.
The 74HC4066/74HCT4066 is pin compatible with the
• Specified from −40 to +85 °C and −40 to +125 °C.
74HC4016/74HCT4066 but exhibits a much lower
on-resistance. In addition, the on-resistance is relatively
constant over the full input signal range.
QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
74HC4066 74HCT4066
tPZH/tPZL turn-on time nE to Vos CL = 15 pF; RL = 1 kΩ; VCC = 5 V 11 12 ns
tPHZ/tPLZ turn-off time nE to Vos CL = 15 pF; RL = 1 kΩ; VCC = 5 V 13 16 ns
CI input capacitance 3.5 3.5 pF
CPD power dissipation notes 1 and 2 11 12 pF
capacitance per switch
CS maximum switch 8 8 pF
capacitance
Notes
1. CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ[(CL + CS) × VCC2 × fo] where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS = maximum switch capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ[(CL + CS) × VCC2 × fo] = sum of the outputs.
2. For 74HC4066 the condition is VI = GND to VCC.
For 74HCT4066 the condition is VI = GND to VCC − 1.5 V.
__________________________________________________________________________
56
__________________________________________________________________________________________________________________
Philips Semiconductors Product specification
Quad bilateral switches 74HC4066; 74HCT4066
FUNCTION TABLE
See note 1.
INPUT nE SWITCH
L off
H on
Note
1. H = HIGH voltage level.
L = LOW voltage level.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74HC4066N −40 to 125 °C 14 DIP14 plastic SOT27-1
74HCT4066N −40 to 125 °C 14 DIP14 plastic SOT27-1
74HC4066D −40 to 125 °C 14 SO14 plastic SOT108-1
74HCT4066D −40 to 125 °C 14 SO14 plastic SOT108-1
74HC4066DB −40 to 125 °C 14 SSOP14 plastic SOT337-1
74HCT4066DB −40 to 125 °C 14 SSOP14 plastic SOT337-1
74HC4066PW −40 to 125 °C 14 TSSOP14 plastic SOT402-1
74HCT4066PW −40 to 125 °C 14 TSSOP14 plastic SOT402-1
74HC4066BQ −40 to 125 °C 14 DHVQFN14 plastic SOT762-1
74HCT4066BQ −40 to 125 °C 14 DHVQFN14 plastic SOT762-1
PINNING
PIN SYMBOL DESCRIPTION

1 1Y independent input/output
handbook, halfpage
2 1Z independent input/output 1Y 1 14 VCC
3 2Z independent input/output 1Z 2 13 1E
2Z 3 12 4E
5 2E enable input (active HIGH)
2Y 4 4066 11 4Y
2E 5 10 4Z
7 GND ground (0 V)
8 3Y independent input/output 3E 6 9 3Z
9 3Z independent input/output GND 7 8 3Y
10 4Z independent input/output MGR253
Fig.1 Pin configuration DIP14, SO14 and
(T)SSOP14.
14 VCC supply voltage
__________________________________________________________________________
57
__________________________________________________________________________________________________________________
CD4069UBC Inverter Circuits

October 1987
Revised April 2002
CD4069UBC
Inverter Circuits
General Description Features
The CD4069UB consists of six inverter circuits and is man- ■ Wide supply voltage range: 3.0V to 15V
ufactured using complementary MOS (CMOS) to achieve ■ High noise immunity: 0.45 VDD typ.
wide power supply operating range, low power consump-
tion, high noise immunity, and symmetric controlled rise ■ Low power TTL compatibility: Fan out of 2 driving 74L
and fall times. or 1 driving 74LS
This device is intended for all general purpose inverter ■ Equivalent to MM74C04
applications where the special characteristics of the
MM74C901, MM74C907, and CD4049A Hex Inverter/Buff-
ers are not required. In those applications requiring larger
noise immunity the MM74C14 or MM74C914 Hex Schmitt
Trigger is suggested.
All inputs are protected from damage due to static dis-
charge by diode clamps to VDD and VSS.
Ordering Code:
Order Number Package Number Package Description
CD4069UBCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4069UBCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4069UBCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Connection Diagram Schematic Diagram
__________________________________________________________________________
58
__________________________________________________________________________________________________________________
DATA SHEET
128M bits DDR SDRAM

EDD1232AAFA (4M words × 32 bits)
Description Features
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59
__________________________________________________________________________________________________________________
EDD1232AAFA
Pin Configurations
[[[LQGLFDWHVDFWLYHORZVLJQDO
100-pin plastic LQFP
A8 (AP)
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
DQ11
VREF
DQ28
DQ27
DQ26
DQ25
DQ24
DQ15
DQ13
DQ12
DQ10
VSSQ
DQ14
DQ8
DM3
DM1
MCL
VDD
CKE
DQ9
VSS
/CK
CK
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ29 81 50 A7
VSSQ 82 49 A6
DQ30 83 48 A5
DQ31 84 47 A4
VSS 85 46 VSS
VDDQ 86 45 A9
NC 87 44 NC
NC 88 43 NC
NC 89 42 NC
NC 90 20 × 14mm2 41 NC
NC 91 0.65mm pin pitch 40 NC
VSSQ 92 39 NC
NC 93 38 NC
DQS 94 37 A11
VDDQ 95 36 A10
VDD 96 35 VDD
DQ0 97 34 A3
DQ1 98 33 A2
VSSQ 99 32 A1
DQ2 100 31 A0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DM0
DM2
/WE
/CAS
/RAS
/CS
BA0
BA1
(Top view)
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60
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EN29LV040
EN29LV040
da0.
4 Megabit (512K x 8-bit ) Uniform Sector,
CMOS 3.0 Volt-only Flash Memory
FEATURES
x High performance program/erase speed

x Single power supply operation - Byte/Word program time: 8μs typical
- Full voltage range: 2.7-3.6 volt read and write - Sector erase time: 500ms typical
operations for battery-powered applications.
- Regulated voltage range: 3.0-3.6 volt read x JEDEC Standard program and erase
and write operations for high performance commands
3.3 volt microprocessors.
x JEDEC standard DATA polling and toggle
bits feature
x High performance
- Access times as fast as 45 ns x Single Sector and Chip Erase
x Embedded Erase and Program Algorithms
x Low power consumption (typical values at 5
MHz) x Erase Suspend / Resume modes:
- 7 mA typical active read current Read or program another Sector during
- 15 mA typical program/erase current Erase Suspend Mode
- 1 PA typical standby current (standard access
x triple-metal double-poly triple-well CMOS
time to active mode)
Flash Technology
x Flexible Sector Architecture: x Low Vcc write inhibit < 2.5V
- Eight 64 Kbyte sectors
x >100K program/erase endurance cycle
- Supports full chip erase
- Individual sector erase supported x Package options
- Sector protection and unprotection: - 8mm x 20mm 32-pin TSOP (Type 1)
Hardware locking of sectors to prevent - 8mm x 14mm 32-pin TSOP (Type 1)
program or erase operations within individual - 32-pin PLCC
sectors
x Commercial and industrial Temperature
Range
GENERAL DESCRIPTION
The EN29LV040 is a 4-Megabit, electrically erasable, read/write non-volatile flash memory,

organized as 524,288 bytes. Any byte can be programmed typically in 8μs. The EN29LV040
features 3.0V voltage read and write operation, with access times as fast as 45ns to eliminate the
need for WAIT states in high-performance microprocessor systems.
The EN29LV040 has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable (WE)
controls, which eliminate bus contention issues. This device is designed to allow either single
Sector or full chip erase operation, where each Sector can be individually protected against
program/erase operations or temporarily unprotected to erase or program. The device can sustain a
minimum of 100K program/erase cycles on each Sector.
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61
__________________________________________________________________________________________________________________
EN29LV040
CONNECTION DIAGRAMS
TABLE 1. PIN DESCRIPTION FIGURE 1. LOGIC DIAGRAM
Pin Name Function

EN29LV040
A0-A18 Addresses
DQ0-DQ7 8 Data Inputs/Outputs
DQ0 – DQ7
WE# Write Enable A0 - A18
CE# Chip Enable

OE# Output Enable
Vcc Supply Voltage CE#
Vss Ground OE#
WE#
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62
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August 1998
FDC6326L
Integrated Load Switch
General Description Features
This device is particularly suited for compact power VDROP=0.20V @ VIN=12V, IL=1.5A.RDS(ON) = 0.125 Ω
management in portable electronic equipment where 3V to VDROP=0.20V @ VIN=5V, IL=1A.RDS(ON) = 0.20 Ω.
20V input and 1.8A output current capability are needed.
This load switch integrates a small N-Channel power SuperSOTTM-6 package design using copper lead frame for
MOSFET (Q1) which drives a large P-Channel power superior thermal and electrical capabilities.
MOSFET (Q2) in one tiny SuperSOTTM-6 package.
SOT-23 TM
SuperSOT -6 SuperSOT -8
TM
SO-8 SOT-223 SOIC-16
Vin,R1 4 3 Vout,C1
EQUIVALENT CIRCUIT
6
.32 ON/OFF 5
Q2
2 Vout,C1 +
VDROP
-
IN OUT
Q1
pin 1 R1,C1 6 1 R2 ON/OFF
SuperSOT TM-6 See Application Circuit
Absolute Maximum Ratings T A = 25°C unless otherwise noted

Symbol Parameter FDC6326L Units
VIN Input Voltage Range 3 - 20 V
VON/OFF On/Off Voltage Range 2.5 - 8 V
IL Load Current - Continuous (Note 1) 1.8 A
- Pulsed (Note 1 & 3) 5
PD Maximum Power Dissipation (Note 2) 0.7 W
TJ,TSTG Operating and Storage Temperature Range -55 to 150 °C
ESD Electrostatic Discharge Rating MIL-STD-883D Human Body 6 kV
Model (100pf/1500Ohm)
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 2) 180 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 2) 60 °C/W
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63
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TECHNICAL DATA IL1117A-x
1.0A Low Dropout Positive Voltage Regulator
Features ΄΀΅ͣͣͤ͞
ሪ Adjustable and Fixed of 1.25, 1.5, 1.8, 2.5, 2.85, 3.3, 5.0V ͑
ඖ Space saving SMD types of SOT-223 ͑͑͑
IL1117A-x
΄ͨ͢͢͢͞ΉΉ
ඖ 1.2V Drop-out Voltage Ͳ͵ͻ͠
͸Ϳ͵͑͑͑͑΀Ά΅͑͑͑͑ͺͿ
ඖ 1.0A Output Current
͑͢ ͑ͣ ͑ͤ
ሪ Line Regulation Typically at 0.2% max
ሪ Current Limiting and Thermal Protection
General Description
The IL1117A is a series of low dropout voltage regulators which can provide
up to 1A of output current. The IL1117A is available in seven fixed voltage,
1.25, 1.5, 1.8, 2.5, 2.85, 3.3 and 5.0V. Additonally it is also available in
adjustable version. On chip precision trimming adjusts the reference/
output voltage to within ± 2%. Current limit is also trimmed to ensure
specified output current and controlled short-circuit current.
The IL1117A series is available in SOT-223 packages.
A minimum of 10uF tantalum capacitor is required at the output to
improve the transient response and stability.
Applications
ሪ Post Regulator for switching DC/DC Converter
ඖ High Efficiency Linear Regulator
ඖ Battery Chargers
ඖ PC Add on Card
ሪ Motherboard clock supplies
ሪ LCD Monitor
ሪ Set-top Box
Absolute Maximum Ratings

ሪ Maximum Input Voltage ~ 15.0V
ሪ Operating Junction Temperature Range -25ఁ ~ 125ఁ
ሪ Storage Temperature Range -50ఁ ~ 150ఁ
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64
__________________________________________________________________________________________________________________
TECHNICAL DATA IL1117A-x
Electrical Characteristics
(Vin = 5V, Co = 10uF, Ta = 25ఁ, unless otherwise specified)
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65
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MST6181LDA
SXGA/WXGA LCD Multi-Function Monitor Controller with Dual LVDS Transmitter
Preliminary Data Sheet Version 0.2
FEATURES
Input supports up to UXGA & 1080P Auto-Configuration/Auto-Detection
Panel supports up to SXGA/WXGA Auto input signal format (SOG, Composite,
Integrated 8-bit triple-ADC/PLL Separated HSYNC, VSYNC, and DE), and input
Integrated DVI/HDCP/HDMI compliant receiver mode (all VESA & IBM modes w/ resolution
RGB/YUV 444 and YUV422 digital video input and polarity) detection
ports Auto-tuning function including phasing,
Dual high-quality scaling engines positioning, offset, gain, and jitter detection
Built-in 3-D video de-interlacer Sync Detection for H/V Sync
Video-over-graphic PIP Dual High-Performance Scaling Engine
Video-by-graphic split screen Fully Programmable shrink/zoom capabilities
MStarACE-2 picture/color processing engine Nonlinear video scaling supports various
Embedded On-screen display controller (OSD) modes including Panorama
engine Flexible independent control of sharpness for
Digital audio I/O & sync processor TV and graphic windows
Built-in dual-link LVDS transmitter Video Processing & Conversion
5 Volt tolerant inputs 3-D motion adaptive video de-interlacer with
Low EMI and power saving features upgraded edge-oriented adaptive algorithm for
Supports PWM & GPO controls smooth low-angle edges
256-pin LQFP Automatic 3:2 pull-down & 2:2 pull-down
Analog RGB Compliant Input Ports detection and recovery
Dual analog ports support up to 165Mhz PIP with programmable size and location,
Supports PC RGB input up to UXGA@60Hz supports multi-video applications
Supports HDTV RGB/YPbPr/YCbCr up to 1080P Video-over-graphic overlay
On-chip high-performance PLLs Video-by-graphic split screen
Supports Composite Sync and SOG Frame rate conversion for both main window
(Sync-on-Green) separator and sub window
Automatic color calibration MStar 2nd Generation Advanced Color Engine
DVI/HDCP/HDMI Compliant Input Port (MStarACE-2) automatic picture enhancement
Operates up to 165 MHz (up to UXGA @60Hz) gives:
Single link on-chip DVI 1.0 compliant receiver Brilliant and fresh color
High-bandwidth Digital Content Protection Intensified contrast and details
(HDCP) 1.1 compliant receiver Vivid skin tone
High Definition Multimedia Interface (HDMI) Sharp edge
1.0 compliant receiver with I2S and S/PDIF Enhanced depth of field perception
digital audio outputs Accurate and independent color control
Long-cable tolerant robust receiving Independent picture control for main and sub
Video Input Port windows
One RGB/YUV 4:4:4 24-bit and one 4:2:2 sRGB compliance allows end-user to
ITU656 8-bit digital video input ports experience the same colors as viewed on CRTs
24-bit port supports 8/16-bit YUV 4:2:2 or and other displays
24-bit RGB/YUV 4:4:4 interlaced/ progressive Programmable 10-bit RGB gamma CLUT
video input up to 1080i/720P 3-D video noise reduction
__________________________________________________________________________
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__________________________________________________________________________________________________________________
MST6181LDA
On-Screen OSD Controller Supports 2 data output formats: Thine & TI

16/256 color palette data mappings
256/512 1-bit/pixel font Compatible with TIA/EIA
128/256/512 4-bit/pixel font With 6/8 bits options
Supports texture function Reduced swing for LVDS for low EMI
Supports 4K attribute/code Supports flexible spread spectrum frequency
Horizontal and vertical stretch of OSD menus with 360Hz~11.8MHz and up to 25%
Supports button function modulation
Pattern generator for production test External Connection/Component
Supports OSD MUX and alpha blending Support 8051 parallel MCU bus
capability Supports 4-wire double-data-rate direct MCU
Supports blinking and scrolling for closed bus
caption applications 32-bit data bus for external frame buffer (SDR
LVDS Panel Interface or DDR DRAM)
Supports dual link up to 135MHz dot clock for All system clocks synthesized from a single
SXGA external clock
GENERAL DESCRIPTION
The MST6181LDA is a high performance and fully integrated graphics processing IC solution for multi-function
LCD monitor/TV with resolutions up to SXGA/WXGA. It is configured with an integrated triple-ADC/PLL, an
integrated DVI/HDCP/HDMI receiver, a video de-interlacer, two high quality scaling engines, an on-screen
display controller, and a built-in output clock generator. By use of external frame buffer, PIP is provided for
multimedia applications. It supports de-interlaced full-screen video, video-on-graphic overlay, split screen,
frame rate conversion, and aspect ratio conversion for various video sources. To further reduce system costs,
the MST6181LDA also integrates intelligent power management control capability for green-mode requirements
and spread-spectrum support for EMI management.
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__________________________________________________________________________________________________________________
MST6181LDA
PIN DIAGRAM (MST6181LDA)
VI_DATA[31]
VI_DATA[30]
VI_DATA[29]
VI_DATA[28]
VI_DATA[27]
VI_DATA[26]
VI_DATA[25]
VI_DATA[24]
AVDD_MPLL
BUSTYPE
LVACKM
AUMUTE
LVACKP
LVBCKM
LVBCKP
SPDIFO
VI_CKB
LVA1M
LVA2M
AUMCK
LVA1P
LVA2P
LVB0M
LVB1M
LVB2M
LVB3M
LVA0M
LVA3M
AIMCK
AUSCK
LVB0P
LVB1P
LVB2P
LVB3P
LVA0P
LVA3P
PWM1
PWM0
AISCK
AUWS
VDDC
VDDP
VDDC
VDDC
XOUT
VDDP
VDDP
AIWS
AUSD
GND
AISD
GND
GND
GND
GND
GND
GND
XIN
NC
NC
NC
NC
NC
NC
256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
GND 1 192 BYPASS
GND 2 191 NC
DVI_R+ 3 190 PWM5
DVI_R- 4 Pin 1 189 PWM4
GND 5 188 PWM3
DVI_G+ 6 187 NC
DVI_G- 7 186 GPO[6]
AVDD_DVI 8 185 GPO[5]
DVI_B+ 9 184 GPO[4]
DVI_B- 10 183 VDDP
GND 11 182 GND
DVI_CK+ 12 181 GND
DVI_CK- 13 180 VDDC
AVDD_DVI 14 179 GPO[3]
REXT 15 178 GPO[2]
AVDD_PLL 16 177 GPO[1]
GND 17 176 GPO[0]
DDCD_DA 18 175 GND
DDCD_CK 19 174 VDDM
GND 20 173 DQS[0]
AVDD_ADC 21 172 MDATA[0]
HSYNC1 22 171 MDATA[1]
VSYNC1 23 170 MDATA[2]
BIN1P 24 169 MDATA[3]
BIN1M 25 168 MDATA[4]
SOGIN1 26 167 MDATA[5]
GIN1P 27 166 MDATA[6]
GIN1M 28 165 MDATA[7]
RIN1P 29 164 MDATA[8]
RIN1M 30 163 MDATA[9]
XXXXX
XXXXXXXXXXX
MST6181LDA
BIN0M 31 162 MDATA[10]

BIN0P 32 161 MDATA[11]
GIN0M 33 160 GND
GIN0P 34 159 VDDM
SOGIN0 35 158 MDATA[12]
RIN0M 36 157 MDATA[13]
RIN0P 37 156 MDATA[14]
AVDD_ADC 38 155 MDATA[15]
GND 39 154 DQS[1]
HSYNC0 40 153 DQM[0]
VSYNC0 41 152 GND
RMID 42 151 VDDC
REFP 43 150 MADR[11]
REFM 44 149 MADR[10]
GND 45 148 MADR[9]
GND 46 147 MADR[8]
VDDP 47 146 GND
VI_DATA[16] 48 145 VDDM
VI_DATA[17] 49 144 MADR[7]
VI_DATA[18] 50 143 MADR[6]
VI_DATA[19] 51 142 MADR[5]
VI_DATA[20] 52 141 MADR[4]
VI_DATA[21] 53 140 MADR[3]
VI_DATA[22] 54 139 MADR[2]
VI_DATA[23] 55 138 MADR[1]
VI_DATA[8] 56 137 MADR[0]
VI_DATA[9] 57 136 WEZ
VI_DATA[10] 58 135 CASZ
VI_DATA[11] 59 134 GND
VI_DATA[12] 60 133 VDDM
VI_DATA[13] 61 132 RASZ
AVDD_APLL 62 131 BADR[0]
GND 63 130 BADR[1]
VI_DATA[14] 64 129 AVDD_PLL2
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
PWM2
MDATA[23]
MDATA[22]
MDATA[21]
MDATA[19]
MDATA[17]
DDCR_CK
MVREF
MCLK
GND
GND
HWRESET
INT
ALE
FIELD
GND
VDDM
GND
VDDM
GND
MCLKE
GND
RDZ
WRZ
MCLKZ
DVSYNC
VDDC
VI_CKA
VDDC
VDDP
DDCR_DA
VI_DATA[0]
VI_DATA[1]
VI_DATA[0]
VI_DATA[3]
VI_DATA[4]
VI_DATA[5]
VI_DATA[6]
VI_DATA[7]
DBUS[0]
DBUS[1]
DBUS[2]
DBUS[3]
DBUS[4]
DBUS[5]
DBUS[6]
DBUS[7]
DQS[3]
MDATA[31]
MDATA[30]
MDATA[29]
MDATA[28]
MDATA[27]
MDATA[26]
MDATA[25]
MDATA[24]
MDATA[20]
MDATA[18]
MDATA[16]
DQS[2]
DQM[1]
DHSYNC
VI_DATA[15]
DE
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68
__________________________________________________________________________________________________________________
MST6181LDA
PIN DESCRIPTION
MCU Interface
Pin Name Pin Type Function Pin
HWRESET Schmitt Trigger Input Hardware Reset, active high 81

w/ 5V-tolerant
DBUS[7:0] I/O w/ 5V-tolerant MCU Direct bus; 4mA driving strength 93-86
ALE I w/ 5V-tolerant MCU Bus ALE, active high 83
RDZ I w/ 5V-tolerant MCU Bus RDZ, active high 84
WRZ I w/ 5V-tolerant MCU Bus WDZ, active high 85
INT Output MCU Bus Interrupt; 4mA driving strength 82
BUSTYPE Input (not 5V-tolerant) MCU bus type selection 240
Low (0V): 4-bit (DBUS[3:0]) DDR Direct Bus
High (3.3V): 8-bit (DBUS[7:0]) Direct Bus
Analog Interface
RMID Mid-Scale Voltage Bypass 42
REFP Internal ADC Top De-coupling Pin 43
REFM Internal ADC Bottom De-coupling Pin 44
REXT Analog Input External Resister 390 ohm to AVDD_DVI 15
HSYNC0 Schmitt Trigger Input Analog HSYNC Input from Channel 0 40
w/ 5V-tolerant
VSYNC0 Schmitt Trigger Input Analog VSYNC Input from Channel 0 41
w/ 5V-tolerant
BIN0M Analog Input Reference Ground for Analog Blue Input from Channel 0 31
BIN0P Analog Input Analog Blue Input from Channel 0 32
GIN0M Analog Input Reference Ground for Analog Green Input from Channel 0 33
GIN0P Analog Input Analog Green Input from Channel 0 34
SOGIN0 Analog Input Sync On Green Input from Channel 0 35
RIN0M Analog Input Reference Ground for Analog Red Input from Channel 0 36
RIN0P Analog Input Analog Red Input from Channel 0 37
HSYNC1 Schmitt Trigger Input Analog HSYNC Input from Channel 1 22
w/ 5V-tolerant
VSYNC1 Schmitt Trigger Input Analog VSYNC Input from Channel 1 23
w/ 5V-tolerant
BIN1M Analog Input Reference Ground for Analog Blue Input from Channel 1 25
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__________________________________________________________________________________________________________________
MST6181LDA

BIN1P Analog Input Analog Blue Input from Channel 1 24
SOGIN1 Analog Input Sync On Green Input from Channel 1 26
GIN1M Analog Input Reference Ground for Analog Green Input from Channel 1 28
GIN1P Analog Input Analog Green Input from Channel 1 27
RIN1M Analog Input Reference Ground for Analog Red Input from Channel 1 30
RIN1P Analog Input Analog Red Input from Channel 1 29
DVI/HDMI Interface
DVI_R+ Input DVI/HDMI Input Channel Red + 3
DVI_R- Input DVI/HDMI Input Channel Red - 4
DVI_G+ Input DVI/HDMI Input Channel Green + 6
DVI_G- Input DVI/HDMI Input Channel Green - 7
DVI_B+ Input DVI/HDMI Input Channel Blue + 9
DVI_B- Input DVI/HDMI Input Channel Blue - 10
DVI_CK+ Input DVI/HDMI Input Clock + 12
DVI_CK- Input DVI/HDMI Input Clock - 13
Video Interface
VI_CKA Input w/ 5V-tolerant Digital Video Input Clock for VI_DATA[23:0] 68
VI_CKB Input w/ 5V-tolerant Digital Video Input Clock for VI_DATA[31:24] 251
VI_DATA[23:0] Input w/ 5V-tolerant Digital Video Input Data[23:0] 55-48, 65, 64,
61-56, 76-69
VI_DATA[31:24] Input Digital Video Input Data[31:24] 244-241, 237-234
FIELD Input w/ 5V-tolerant FIELD Input 96
DVSYNC Input w/ 5V-tolerant Digital VSYNC Input 95
DHSYNC Input w/ 5V-tolerant Digital HSYNC Input 66
DE Input w/ 5V-tolerant DE Input 67
Digital Audio Interface

AUMCK Output Audio Master Clock Output 228
AUSD Output Audio Serial Data Output; 4mA driving strength 229
AUSCK Output Audio Serial Clock Output; 4mA driving strength 230
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__________________________________________________________________________________________________________________
MST6181LDA

AUWS Output Word Select Output; 4mA driving strength 231
AUMUTE Output Audio Output Mute Control 232
SPDIFO Output S/PDIF Audio Output; 4mA driving strength 233
AIMCK Input w/ 5V-tolerant Audio Master Clock Input 247
AISD Input w/ 5V-tolerant Audio Serial Data Input 248
AISCK Input w/ 5V-tolerant Audio Serial Clock Input 249
AIWS Input w/ 5V-tolerant Word Select Input 250
LVDS Interface
LVA0M Output A-Link Negative LVDS Differential Data Output 211
LVA0P Output A-Link Positive LVDS Differential Data Output 210
LVACKM Output A-Link Negative LVDS Differential Data Output 205
LVACKP Output A-Link Positive LVDS Differential Data Output 204
LVB0M Output B-Link Negative LVDS Differential Data Output 227
LVB0P Output B-Link Positive LVDS Differential Data Output 226
LVBCKM Output B-Link Negative LVDS Differential Data Output 217
LVBCKP Output B-Link Positive LVDS Differential Data Output 216
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71
__________________________________________________________________________________________________________________
MST6181LDA
GPO Interface
PWM0 Output PWM; 4mA driving strength 252
PWM3/GPO[7] Output GPO with PWM Function; 6mA driving strength 188
GPO[6:0] Output GPO; 6mA driving strength 186-184,
179-176
DRAM Interface
MVREF Input Reference Voltage for DDR SDRAM Interface 124
MCLKE Output DRAM Memory Clock Enable 125
MCLKZ Output DRAM Memory Clock Complementary / Input 126
(for differential clocks)
MCLK Output DRAM Memory Clock 127
RASZ Output Row Address Strobe, active low 132
CASZ Output Column Address Strobe, active low 135
WEZ Output Write Enable, active low 136
DQM[1:0] Output Data Mask Byte Enable 121, 153
DQS[3:0] Output Data Strobe 101, 120, 154, 173
BADR[1:0] Output Memory Bank Address 130, 131
MADR[11:0] Output Memory Address 150-147, 144-137
MDATA[31:0] I/O Memory Data 102-105, 108-119,
155-158, 161-172
Misc. Interface
DDCD_DA I/O w/ 5V-tolerant HDCP Serial Bus Data / DDC Data of DVI Port; 4mA driving 18
strength
DDCD_CK Input w/ 5V-tolerant HDCP Serial Bus Data / DDC Clock of DVI Port 19
DDCR_CK Input w/ 5V-tolerant DDC Clock for ROM 94
DDCR_DA I/O w/ 5V-tolerant DDC Data for ROM 97
BYPASS For External Bypass Capacitor 192
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72
__________________________________________________________________________________________________________________
MST6181LDA

XIN Crystal Oscillator Input Xin 255
XOUT Crystal Oscillator Output Xout 254
Power Pins
AVDD_DVI 3.3V Power DVI/HDMI Power 8, 14
AVDD_ADC 3.3V Power ADC Power 21, 38
AVDD_PLL 3.3V Power PLL Power 16
AVDD_PLL2 3.3V Power PLL Power 129
AVDD_APLL 1.8V Power Audio PLL Power 62
AVDD_MPLL 3.3V Power PLL Power 256
VDDM 3.3V Power (SDRAM) / Memory Interface Power 106, 122, 133, 145, 159,
2.5V Power (DDR) 174
VDDP 3.3V Power Digital Output Power 47, 80, 183, 202, 222,
238
VDDC 1.8V Power Digital Core Power 77, 99, 151, 180, 213,
225, 246
GND Ground Ground 1, 2, 5, 11, 17, 20, 39,
45, 46, 63, 78, 79, 100,
107, 123, 128, 134, 146,
152, 160, 175, 181, 182,
193, 203, 212, 223, 224,
239, 245
No Connects
NC No connect. Leave these pins floating. 187, 191, 194-199
__________________________________________________________________________
73
__________________________________________________________________________________________________________________
MST6181LDA
ELECTRICAL SPECIFICATIONS
Analog Interface Characteristics
Parameter Min Typ Max Unit
Resolution 8 Bits
DC ACCURACY
Differential Nonlinearity ±0.5 +1.50/-1.0 LSB
Integral Nonlinearity ±1 LSB
No Missing Codes Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum 0.5 V p-p
Maximum 1.0 V p-p
Input Bias Current 1 uA
Input Full-Scale Matching 1.5 %FS
Brightness Level Adjustment 62 %FS
SWITCHING PERFORMANCE
Maximum Conversion Rate 165 MSPS
Minimum Conversion Rate 12 MSPS
HSYNC Input Frequency 15 200 kHz
PLL Clock Rate 12 165 MHz
PLL Jitter 500 ps p-p
Sampling Phase Tempco TBD ps/°C
DIGITAL INPUTS
Input Voltage, High (VIH) 2.5 V
Input Voltage, Low (VIL) 0.8 V
Input Current, High (IIH) -1.0 uA
Input Current, Low (IIL) 1.0 uA
Input Capacitance 5 pF
DIGITAL OUTPUTS
Output Voltage, High (VOH) VDDP-0.1 V
Output Voltage, Low (VOL) 0.1 V
Duty Cycle
DCK, /DCK 45 50 55 %
Output Coding Binary
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power 250 MHz
Channel to Channel Matching 0.5% Full-Scale
Specifications subject to change without notice.
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__________________________________________________________________________________________________________________
MST6181LDA

Parameter Symbol Min Typ Max Units
3.3V Supply Voltages VVDD_33 -0.3 3.6 V
Input Voltage (5V tolerant inputs) VIN5Vtol -0.3 5.0 V
Input Voltage (non 5V tolerant inputs) VIN -0.3 VVDD_33 V
Ambient Operating Temperature TA 0 70 °C
Storage Temperature TSTG -40 150 °C
Junction Temperature TJ 150 °C
Thermal Resistance (Junction to Air) Natural θJA 18 °C/W
Conversion
Thermal Resistance (Junction to Case) Natural θJC 1.2 °C/W
Conversion
Note: Stress above those listed under Absolute Maximum Rating may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may
affect device reliability.
ORDERING GUIDE DISCLAIMER

MSTAR SEMICONDUCTOR RESERVES THE
Model Temperature Package Package
RIGHT TO MAKE CHANGES WITHOUT
Range Description Option FURTHER NOTICE TO ANY PRODUCTS HEREIN
MST6181LDA 0°C to +70°C LQFP 256 TO IMPROVE RELIABILITY, FUNCTION OR
DESIGN. NO RESPONSIBILITY IS ASSUMED
MST6181LDA-LF 0°C to +70°C LQFP 256 BY MSTAR SEMICONDUCTOR ARISING OUT OF
Note: Product suffix “LF” represents lead-free version. THE APPLICATION OR USER OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER
MARKING INFORMATION
DOES IT CONVEY ANY LICENSE UNDER ITS
MST6181LDA PATENT RIGHTS, NOR THE RIGHTS OF
Part Number
OTHERS.
Lot Number
Operation Code A
Operation Code B
Date Code (YYWW)
Electrostatic charges accumulate on both test equipment and human body and can discharge
without detection. MST6181LDA comes with ESD protection circuitry; however, the device may be
permanently damaged when subjected to high energy discharges. The device should be handled
with proper ESD precautions to prevent malfunction and performance degradation.
REVISION HISTORY
Document Description Date
MST6181LDA_ds_v01 Initial release Jul 2005
MST6181LDA_ds_v02 Updated Features / On-Screen OSD Controller Aug 2005
Updated Register Table
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__________________________________________________________________________________________________________________
MTV512M
8051 Embedded Monitor Controller with 64K Flash ROM

GENERAL DESCRIPTIONS • Watchdog timer with programmable interval
• Support external counters/timers, T0, T1, and ET2
The MTV512M micro-controller is an 8051 CPU core • Single/double frequency clock output
embedded device especially tailored for flat panel • Two clock output ports
display applications. It includes an 8051 CPU core, • Two external interrupts, INT1 is shared with Slave
768-byte SRAM, 4 channels of 6-bit ADC, 3 external IIC interrupt source
counters/timers, 6 channels of PWM DAC, VESA • Maximum 4 channels of 6-bit ADC
DDC interface, and a 64K-byte internal program • Flash-ROM code protection selection
Flash-ROM memory. • Hardware ISP (In System Programming), no Boot
Code required
• Embedded Dual Ports DDCRAM (128-byte x 2)
FEATURES • 40-pin PDIP, 42-pin SDIP, or 44-pin PLCC/QFP
• 8051 core, CPU operating frequency up to 24MHz package
• 3.3V power supply • Green products like Pb-Free Packages or All
• 768-byte RAM; 64K-byte program Flash memory Green Packages available
• Maximum 6 channels of PWM DAC
• Compliant with VESA DDC1/2B/2Bi/2B+/CI
standard
BLOCK DIAGRAM
P0.0-7 P0.0-7
P1.0-7
P3.0-3.4
P2.0-3 P2.0-7 AUXRAM &
RD RD XFR DDCRAM1 &
WR WR DDCRAM2
8051 ALE ALE
INT1 INT1
CORE
RST
X1 ADC
X2
CKO AD0-3
PWM DAC
P7.6-7 DA0-5
P6.0-7 AUX DDC & IIC HSCL1

P5.0-6 I/O INTERFACE HSDA1
HSCL2
HSDA2
**This datasheet is the confidential information of MYSON CENTURY, INC. and is subject to various privileges
against unauthorized disclosure. Recipient shall not disclose this confidential information to any other person,
nor shall one use the confidential information for the purpose of competing with MYSON CENTURY, INC.
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__________________________________________________________________________________________________________________
MTV512M
PIN CONNECTION DIAGRAMS
DA0/P5.0 1 40 VCC
DA1/P5.1 2 39 P1.0/ET2
DA2/P5.2 3 38 P1.1
DA3/P5.3 4 37 P1.2
DA4/P5.4 5 36 P1.3
MTV512MN 40-pin PDIP

DA5/P5.5 6 35 P1.4
P5.6/HSCL2 7 34 P1.5
P5.7/HSDA2 8 33 P1.6
RST 9 32 P1.7
HSCL1/P3.0/RXD 10 31 NC
HSDA1/P3.1/TXD 11 30 NC
P3.2/INT0 12 29 VSYNC
P3.3/INT1 13 28 P6.7
P3.4/T0 14 27 P6.6/CLKO1
P3.5/T1 15 26 P6.5
P7.6/CLKO2 16 25 P6.4
P7.7 17 24 P6.3/AD3
X2 18 23 P6.2/AD2
X1 19 22 P6.1/AD1
VSS 20 21 P6.0/AD0
NC 1 42 VCC
DA0/P5.0 2 41 P1.0/ET2
DA1/P5.1 3 40 P1.1
DA2/P5.2 4 39 P1.2
DA3/P5.3 5 38 P1.3
DA4/P5.4 6 37 P1.4
MTV512MS 42-pin SDIP
DA5/P5.5 7 36 P1.5
P5.6/HSCL2 8 35 P1.6
P5.7/HSDA2 9 34 P1.7
RST 10 33 NC
HSCL1/P3.0/RXD 11 32 NC
HSDA1/P3.1/TXD 12 31 NC
P3.3/INT1 14 29 P6.7
P3.4/T0 15 28 P6.6/CLKO1
P3.5/T1 16 27 P6.5
P7.6/CLKO2 17 26 P6.4
P7.7 18 25 P6.3/AD3
X2 19 24 P6.2/AD2
X1 20 23 P6.1/AD1
VSS 21 22 P6.4/AD0
__________________________________________________________________________
77
__________________________________________________________________________________________________________________
MTV512M
DA4/P5.4
DA3/P5.3
DA2/P5.2
DA1/P5.1
DA0/P5.0
P1.0/ET2
VCC
P1.1
P1.2
P1.3
NC
44
43
42
41
40
3
2
1
6
5
4
DA5/P5.5 7 39 P1.4
P5.6/HSCL2 8 38 P1.5
P5.7/HSDA2 9 37 P1.6
RST 10 36 P1.7
HSCL1/RXD/P3.0 11 35 NC
MTV512MV
NC 12 34 NC
44-pin
HSDA1/TXD/P3.1 13 PLCC 33 NC
P3.3/INT1 15 31 P6.7
P3.4/T0 16 30 P6.6/CLKO1
P3.5/T1 17 29 P6.5
18
19
20
22
23
24
25
26
27
28
21
P7.6/CLKO2
P7.7
X1
VSS
NC
P6.0/AD0
P6.1/AD1
P6.3/AD3
P6.4
X2
P6.2/AD2
DA4/P5.4
DA3/P5.3
DA2/P5.2
DA1/P5.1
DA0/P5.0
P1.0/ET2
P1.1
P1.2
P1.3
VCC 38
NC
44
43
42
41
40
39
37
36
35
34
DA5/ P5.5 1 33 P1.4

P5.6/HSCL2 2 32 P1.5
P5.7/HSDA2 3 31 P1.6
RST 4 30 P1.7
HSCL1/RXD/P3.0 5 29 NC
MTV512MF
NC 6 28 NC
44-pin
HSDA1/TXD/P3.1 7 QFP 27 NC
P3.3/INT1 9 25 P6.7
P3.4/T0 10 24 P6.6/CLKO1
P3.5/T1 11 23 P6.5
12
13
14
16
17
18
19
20
21
22
15
P7.6/CLKO2
X2
X1
VSS
NC
P6.0/AD0
P6.1/AD1
P7.7
P6.2/AD2
P6.3/AD3
P6.4
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78
__________________________________________________________________________________________________________________
www.fairchildsemi.com
RC1117
1A Adjustable/Fixed Low Dropout Linear Regulator
Features Description
• Low dropout voltage The RC1117 and RC1117-2.5, -2.85, -3.3 and -5 are low
• Load regulation: 0.05% typical dropout three-terminal regulators with 1A output current
• Trimmed current limit capability. These devices have been optimized for low voltage
• On-chip thermal limiting where transient response and minimum input voltage are
• Standard SOT-223, TO-263, and TO-252 packages critical. The 2.85V version is designed specifically to be
• Three-terminal adjustable or fixed 2.5V, 2.85V, 3.3V, 5V used in Active Terminators for SCSI bus.
Applications Current limit is trimmed to ensure specified output current

and controlled short-circuit current. On-chip thermal limiting
• Active SCSI terminators provides protection against any combination of overload and
• High efficiency linear regulators ambient temperatures that would create excessive junction
• Post regulators for switching supplies temperatures.
• Battery chargers
• 5V to 3.3V linear regulators Unlike PNP type regulators where up to 10% of the output
• Motherboard clock supplies current is wasted as quiescent current, the quiescent current
of the RC1117 flows into the load, increasing efficiency.
The RC1117 series regulators are available in the industry-

standard SOT-223, TO-263 (D2PAK), and TO-252 (DPAK)
power packages.
Typical Applications
RC1117
VIN = 3.3V + VIN VOUT 1.5V at 1A

+
10μF 22μF
R1
ADJ 124Ω
R2
24.9Ω
VOUT = VREF(1 + R2/R1) + IAdj • R2
RC1117-2.85
VIN = 5V + VIN VOUT +

2.85V at 1A
10μF 22μF
GND
__________________________________________________________________________
79
__________________________________________________________________________________________________________________
PRODUCT SPECIFICATION RC1117
Pin Assignments
Tab is
VOUT
Tab is
Front View VOUT
3 IN
Tab is
VOUT 2 OUT
1 ADJ/GND
1 2 3 1 2 3
4-Lead Plastic SOT-223

ΘJC = 15°C/W*
ADJ/ IN
GND ADJ/ OUT IN
GND
3-Lead Plastic TO-252
ΘJC = 3°C/W* 3-Lead Plastic TO-263
ΘJC = 3°C/W*
*With package soldered to 0.5 square inch copper area over backside ground plane or internal power plane., ΘJA can vary from
30°C/W to more than 50°C/W. Other mounting techniques may provide better thermal resistance than 30°C/W.

Parameter Min. Max. Unit
VIN 7.5 V
Operating Junction Temperature Range 0 125 °C
Storage Temperature Range -65 150 °C
Lead Temperature (Soldering, 10 sec.) 300 °C
__________________________________________________________________________
80
__________________________________________________________________________________________________________________
www.ti.com
SLOS407D − FEBRUARY 2003 − REVISED AUGUST 2004

FEATURES DESCRIPTION
D 12-W/Ch Into an 8-Ω Load From 15-V Supply
The TPA3004D2 is a 12-W (per channel) efficient, Class-D
D Efficient, Class-D Operation Eliminates
audio amplifier for driving bridged-tied stereo speakers.
Heatsinks and Reduces Power Supply
The TPA3004D2 can drive stereo speakers as low as 4 Ω.
Requirements
The high efficiency of the TPA3004D2 eliminates the need
D 32-Step DC Volume Control From −40 dB to for external heatsinks when playing music.
36 dB
D Line Outputs For External Headphone Stereo speaker volume is controlled with a dc voltage
Amplifier With Volume Control applied to the volume control terminal offering a range of
D Regulated 5-V Supply Output for Powering gain from –40 dB to 36 dB. Line outputs, for driving
TPA6110A2 external headphone amplifier inputs, are also dc voltage
D Space-Saving, Thermally-Enhanced controlled with a range of gain from –56 dB to 20 dB.
PowerPAD™ Packaging An integrated 5-V regulated supply is provided for
D Thermal and Short-Circuit Protection powering an external headphone amplifier.
APPLICATIONS
D LCD Monitors and TVs
D Powered Speakers
PVCC 10 μF 10 μF PVCC
10 nF 10 nF
Cs Cs
0.1 μF 0.1 μF
Cbs Cbs
Cs Cs
PGNDR
PGNDR
PVCCR
PVCCR
ROUTN
ROUTN
PVCCR
PVCCR
BSRN
ROUTP
ROUTP
BSRP
Ccpr
SYSTEM CONTROL SD VCLAMPR
Crinn
MODE_OUT 1 μF
RINN RINN MODE_OUT
Crinp 1 μF
RINP RINP MODE SYSTEM CONTROL
C2p5 AVCC
1 μF AVCC
V2P5 Cvcc
Clinp Cs
1 μF 0.1 μF 10 μF
LINP LINP VAROUTR RLINE_OUT
Clinn
1 μF
LINN LINN VAROUTL LLINE_OUT
1 μF TPA3004D2
AVDDREF FADE SYSTEM CONTROL
AVDD Cvdd
VREF AVDD
Cosc 100 nF
VARDIFF VARDIFF COSC
220 pF Rosc
VARMAX VARMAX ROSC
VOL 120 kΩ
VOLUME AGND
Ccpl
REFGND VCLAMPL
PGNDL
PGNDL
LOUTN
LOUTN
PVCCL
PVCCL
LOUTP
LOUTP
PVCCL
PVCCL
1 μF
BSLN
BSLP
10
kΩ 10
kΩ
Cs Cs
Cbs Cbs
0.1 μF 0.1 μF
Cs Cs
10 nF 10 nF
PVCC 10 μF 10 μF PVCC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
81
__________________________________________________________________________________________________________________
TPA3004D2 www.ti.com
AVAILABLE OPTIONS
PACKAGED DEVICE
TA
48-PIN HTQFP (PHP)(1)
−40°C to 85°C TPA3004D2PHP
(1) The PHP package is available taped and reeled. To order a taped and
reeled part, add the suffix R to the part number (e.g., TPA3004D2PHPR).
PIN ASSIGNMENTS
PHP PACKAGE
(TOP VIEW)
PGNDR
PGNDR
ROUTN
ROUTN
PVCCR
PVCCR
ROUTP
ROUTP
PVCCR
PVCCR
BSRN
BSRP
48 47 46 45 44 43 42 41 40 39 38 37
SD 1 36 VCLAMPR
RINN 2 35 MODE_OUT
RINP 3 34 MODE
V2P5 4 33 AVCC
LINP 5 32 VAROUTR
LINN 6 31 VAROUTL
TPA3004D2
AVDDREF 7 30 FADE
VREF 8 29 AVDD
VARDIFF 9 28 COSC
VARMAX 10 27 ROSC
VOLUME 11 26 AGND
REFGND 12 25 VCLAMPL
13 14 15 16 17 18 19 20 21 22 23 24
BSLP
PVCCL
PVCCL
LOUTP
LOUTP
PVCCL
PVCCL
BSLN
LOUTN
LOUTN
PGNDL
PGNDL
__________________________________________________________________________
82
__________________________________________________________________________________________________________________
TPA3004D2 www.ti.com
Terminal Functions
TERMINAL
I/O DESCRIPTION
NO. NAME
AGND 26 − Analog ground for digital/analog cells in core
AVCC 33 − High-voltage analog power supply (8.5 V to 18 V)
AVDD 29 O 5-V Regulated output capable of 100-mA output
AVDDREF 7 O 5-V Reference output—provided for connection to adjacent VREF terminal.
BSLN 13 I/O Bootstrap I/O for left channel, negative high-side FET
BSLP 24 I/O Bootstrap I/O for left channel, positive high-side FET
BSRN 48 I/O Bootstrap I/O for right channel, negative high-side FET
BSRP 37 I/O Bootstrap I/O for right channel, positive high-side FET
COSC 28 I/O I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5
FADE 30 I Input for controlling volume ramp rate. A logic low on this pin places the amplifier in fade mode. A logic high on
this pin allows a quick transition to the desired volume setting when cycling SD or during power-up.
LINN 6 I Negative differential audio input for left channel
LINP 5 I Positive differential audio input for left channel
LOUTN 16, 17 O Class-D 1/2-H-bridge negative output for left channel
LOUTP 20, 21 O Class-D 1/2-H-bridge positive output for left channel
MODE 34 I Input for MODE control. A logic high on this pin places the amplifier in the variable output mode and the Class-D
outputs are disabled. A logic low on this pin places the amplifier in the Class-D mode and Class-D stereo outputs
are enabled. Variable outputs (VAROUTL and VAROUTR) are still enabled in Class-D mode to be used as
line-level outputs for external amplifiers.
MODE_OUT 35 O Output for control of the variable output amplifiers. When the MODE pin (34) is a logic high, the MODE_OUT
pin is driven low. When the MODE pin (34) is a logic low, the MODE_OUT pin is driven high. This pin is intended
for MUTE control of an external headphone amplifier. Leave unconnected when not used for headphone
amplifier control.
PGNDL 18, 19 − Power ground for left channel H-bridge
PGNDR 42, 43 − Power ground for right channel H-bridge
PVCCL 14, 15 − Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or AVCC.
PVCCL 22, 23 − Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or AVCC.
PVCCR 38,39 − Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or AVCC.
PVCCR 46, 47 − Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or AVCC.
REFGND 12 − Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC
ground to this terminal.
RINP 3 I Positive differential audio input for right channel
RINN 2 I Negative differential audio input for right channel
ROSC 27 I/O Current setting resistor for ramp generator. Nominally equal to 1/8*VCC
ROUTN 44, 45 O Class-D 1/2-H-bridge negative output for right channel
ROUTP 40, 41 O Class-D 1/2-H-bridge positive output for right channel
SD 1 I Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC.
VARDIFF 9 I DC voltage to set the difference in gain between the Class-D and VAROUT outputs. Connect to GND or
AVDDREF if VAROUT outputs are unconnected.
VARMAX 10 I DC voltage that sets the maximum gain for the VAROUT outputs. Connect to GND or AVDDREF if VAROUT
outputs are unconnected.
VAROUTL 31 O Variable output for left channel audio. Line level output for driving external HP amplifier.
__________________________________________________________________________
83
__________________________________________________________________________________________________________________
www.ti.com TPA3004D2
Terminal Functions (Continued)

TERMINAL
I/O DESCRIPTION
NO. NAME
VAROUTR 32 O Variable output for right channel audio. Line level output for driving external HP amplifier.
VCLAMPL 25 − Internally generated voltage supply for left channel bootstrap capacitors.
VCLAMPR 36 − Internally generated voltage supply for right channel bootstrap capacitors.
VOLUME 11 I DC voltage that sets the gain of the Class-D and VAROUT outputs.
VREF 8 I Analog reference for gain control section.
V2P5 4 O 2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended inputs.
— Thermal − Connect to AGND and PGND—should be center point for both grounds.
Pad
ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage range: AVCC, PVCC −0.3 V to 20 V
Load impedance, RL ≥ 3.6 Ω
MODE, VREF, VARDIFF, VARMAX, VOLUME, FADE 0 V to 5.5 V
Input voltage range, VI SD −0.3 V to VCC + 0.3 V
RINN, RINP, LINN, LINP −0.3 V to 7 V
AVDD 120 mA
Supply current
AVDDREF 10 mA
Output current VAROUTL, VAROUTR 20 mA
Continuous total power dissipation See Dissipation Rating Table
Operating free-air temperature range, TA −40°C to 85°C
Operating junction temperature range, TJ(2) −40°C to 150°C
Storage temperature range, Tstg −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The TPA3004D2 incorporates an exposed PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally
dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature that could permanently
damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package.
PACKAGE DISSIPATION RATINGS

PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C
PHP 4.3 W 34.7 mW/°C(1) 2.7 W 2.2 W
(1) The PowerPAD must be soldered to a thermal land on the printed circuit board. Please refer to the PowerPAD
Thermally Enhanced Package application note (SLMA002
__________________________________________________________________________
84
__________________________________________________________________________________________________________________
TPA6110A2
150-mW STEREO AUDIO POWER AMPLIFIER
SLOS314 – DECEMBER 2000
150 mW Stereo Output DGN PACKAGE

(TOP VIEW)
PC Power Supply Compatible
– Fully Specified for 3.3 V and 5 V BYPASS 1 8 IN1–
Operation GND 2 7 VO 1
– Operation to 2.5 V SHUTDOWN 3 6 VDD
Pop Reduction Circuitry IN2– 4 5 VO 2
Internal Mid-Rail Generation
Thermal and Short-Circuit Protection
Surface-Mount Packaging
– PowerPAD™ MSOP
Pin Compatible With LM4881
description
The TPA6110A2 is a stereo audio power amplifier packaged in an 8-pin PowerPAD™ MSOP package capable
of delivering 150 mW of continuous RMS power per channel into 16-Ω loads. Amplifier gain is externally
configured by means of two resistors per input channel and does not require external compensation for settings
of 1 to 10.
THD+N when driving a 16-Ω load from 5 V is 0.03% at 1 kHz, and less than 1% across the audio band of 20
Hz to 20 kHz. For 32-Ω loads, the THD+N is reduced to less than 0.02% at 1 kHz, and is less than 1% across
the audio band of 20 Hz to 20 kHz. For 10-kΩ loads, the THD+N performance is 0.005% at 1 kHz, and less than
0.5% across the audio band of 20 Hz to 20 kHz.
typical application circuit
325 kΩ 325 kΩ VDD 6

VDD
Rf C(S)
VDD/2
Audio
Input
Ri IN 1–
8 VO1 7
–
Ci +
C(C)
1 BYPASS
C(B)
Audio
Input
Ri IN 2–
4 VO2 5
–
Ci +
C(C)
From Shutdown 3 SHUTDOWN Bias 2

Control Circuit Control
Rf
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Copyright © 2000, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
__________________________________________________________________________
85
__________________________________________________________________________________________________________________
TPA6110A2
150-mW STEREO AUDIO POWER AMPLIFIER
SLOS314 – DECEMBER 2000
AVAILABLE OPTIONS
PACKAGED DEVICE MSOP
TA
MSOP† Symbolization
– 40°C to 85°C TPA6110A2DGN TI AIZ
† The DGN package is available in left-ended tape and reel only (e.g.,
TPA6110A2DGNR).
Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
BYPASS 1 I Tap to voltage divider for internal mid-supply bias supply. Connect to a 0.1 μF to 1 μF low ESR capacitor for
best performance.
GND 2 I GND is the ground connection.
IN1– 8 I IN1– is the inverting input for channel 1.
IN2– 4 I IN2– is the inverting input for channel 2.
SHUTDOWN 3 I Puts the device in a low quiescent current mode when held high.
VDD 6 I VDD is the supply voltage terminal.
VO1 7 O VO1 is the audio output for channel 1.
VO2 5 O VO2 is the audio output for channel 2.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)‡
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE

TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING
DGN 2.14 W§ 17.1 mW/°C 1.37 W 1.11 W
§ Please see the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report
(literature number SLMA002), for more information on the PowerPAD™ package. The thermal data was
measured on a PCB layout based on the information in the section entitled Texas Instruments Recommended
Board for PowerPAD on page 33 of the before mentioned document.
recommended operating conditions

MIN MAX UNIT
Supply voltage, VDD 2.5 5.5 V
Operating free-air temperature, TA –40 85 °C
High-level input voltage, VIH, (SHUTDOWN) 60% x VDD V
Low-level input voltage, VIL, (SHUTDOWN) 25% x VDD V
2 __________________________________________________________________________
86
__________________________________________________________________________________________________________________
Techwell Mixed Signal Semiconductor Solutions
TECHWELL
VIDEO
DECODERS
NTSC/PAL/SECAM Video Decoder for Multimedia Applications
Features
TW9906
3x10-bit Multi-Standard Comb Filter Video Decoder
with YCbCr Component Input
* Pin to Pin with TW9909
Target Applications
Techwell's TW9906 is a high quality NTSC/PAL/SECAM video decoder
CRT, LCD, PDP and Projection TV
Multifunction LCD Monitor (Monitor TV)
that is designed for multimedia applications. It uses the mixed-signal
DVD-Recorder 2.5V/3.3V CMOS technology to provide a low-power integrated solution.
PC TV Capture Card
CCTV Digital Video Recorder The TW9906 analog front-end is equipped with three separate analog
channels that enable it to accept all three possible analog video signal
standards: composite, S-video or YCbCr component video. All channels
include an analog multiplexer (MUX) for maximum flexibility in software
Analog Video Decoder controlled input selection. It is possible to connect up to five composite
inputs at one time and allow the software to switch between them.
NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N Alternatively several combinations of composite inputs and S-Video
combination), PAL (60), SECAM support with
component inputs may be switched under software control. (Four input
automatic format detection
channels of any format can be accommodated with but there is a
Advanced synchronization processing for VCR
maximum of 2 S-Video inputs or 2 component inputs.)
fast forward, backward, and pause mode
Software selectable analog inputs
The front-end contains all the necessary circuits to simplify the system
Up to five composite video inputs
design. The built-in three high quality 10-bit analog-to-digital converters
Four composite, one S-video or one YCbCr
(ADCs) convert inputs into digital signals for processing.
input
Two composite, two S-Video or two YCbCr
inputs The TW9906 uses proprietary adaptive 4H comb filter for chroma and luma
Three composite, one S-Video and one YCbCr separation to achieve high video quality. The image enhancement
inputs includes horizontal and vertical peaking, CTI and BCS control.
Three 10-bit ADCs with analog clamping circuit
and anti-aliasing filter built in The advanced synchronization processing can produce stable pictures for
Fully programmable static gain or automatic non-standard signal such as those produced by VCR trick mode.
gain control for the Y channel
Programmable white peak control for the Y The high quality scaler uses multi-tap poly-phase decimation filter to
channel accurately scale down the image with minimum phase error. It can be
programmed to scale-down the output picture to an arbitrary ratio with
cropping.
The TW9906 supports flexible pixel interface. It outputs YCbCr (4:2:2) data
stream over 10-bit or 20-bit data path. It also supports both free-running
clock and line-locked clock output.
A 2-wire serial MPU interface is used to simplify system integration. All the
functions can be controlled through this interface.
www.techwellinc.com
__________________________________________________________________________
87
__________________________________________________________________________________________________________________
NTSC/PAL/SECAM Video Decoder for Multimedia Applications
TW9906
3x10-bit Multi-Standard Comb Filter Video Decoder
with YCbCr Component Input
* Pin to Pin with TW9909
TW9906 Block Diagram
Scaler/Cropping
Anti-alias
VIN (0)
MUX
Clamp
10-bit
Filter
ADC
Luma/Chroma
Filter
V
Video Processing
H/V Down
Demodulation
VIN (1)/MUX4
processor
Chroma
CIN (0) Adaptive 4H comb filter for the best image

MUX
Clamp
10-bit
ADC
Anti-alias
Filter
Analog Video In
CIN (1) U quality

Filter
PAL delay line for color phase error correction

Y
VD(19:0)
Digital sub-carrier PLL for accurate color
Filter
AGC/Cla
Y/C separation
YBOUT
10-bit
ADC
4-H adaptive
decoding
comb filter
Anti-alias
MUX0 MPOUT
Filter
Digital Horizontal PLL and advanced

MUX
MUX3
synchronization processing for non-standard
Video output Interface
VSYNC video signals

Sync
HSYNC Programmable hue, brightness, saturation,

FIELD
contrast, and sharpness
DVALID
Blue stretch
VBI Pass
through
Image enhancement with 2D peaking and CTI.

Generator
Line-lock
CLKX2
clock
CLKX1 Automatic color control and color killer

Clock
27 Mhz PDN IF compensation filter

INTREQ
VBI Slicer Detection of level of copy protection
VBI FIFO according to Macrovision standard
2 Wire
Serial
SIAD0
YCbCr input supports 480i/576i and sub-
Bus
SCLK
SDAT AMXCLK sampled 480p/576p with auto-detection.
Audio Clock
AMCLK
ASCLK
ALRCLK
Video Output Miscellaneous

Supports both free-running and line-locked clock outputs
Programmable output cropping Two wire MPU serial bus interface
High quality horizontal filtered scaling with arbitrary scale down Power-down mode
ratio Typical power consumption 0.25W
VMI 1.4 compatible 10-bit or 20-bit pixel interface Single 27MHz crystal for all standards
ITU-R 601 or ITU-R 656 compatible output YCbCr(4:2:2) output Supports 24.54MHz and 29.5MHz crystal
format for high quality square pixel format
VBI slicer supporting industrial standard data services with data 3.3V / 5V tolerant I/O
packet filter capability 2.5V / 3.3V Power Supply
Built-in VBI FIFO for convenient access through host interface 80 pin TQPF package
VBI data pass through, raw ADC data for Intercast™
Field locked audio clock generator
About Techwell
Techwell designs and sells mixed signal semiconductor solutions for digital video applications.The company's products enable the
conversion of analog video sources to digital form and facilitate the display, storage and transport of digital video, HDTV, and personal
computer display information. Headquartered in San Jose, CA, Techwell currently has over 50 employees in the U.S., Korea, and Taiwan.

For more information on Techwell, please contact us at 1-408-435-3888
© 2005 Techwell Inc. All rights reserved.
All other trademarks are property of their respective owners
TECHWELL INC. TEL 1-408-435-3888 www.techwellinc.com
__________________________________________________________________________
88
1 __________________________________________________________________________________________________________________
VCT 49xyI, VCT 48xyI ADVANCE INFORMATION
Volume 1: General Description
General Description 1.1. Features
Release Note: This data sheet describes functions The VCT 49xyI, VCT 48xyI family offers a rich feature
and characteristics of the VCT 49xyI, VCT 48xyI- set, covering the whole range of state-of-the-art 50/60-
C4. Hz TV applications.
– PSSDIP88-1/-2 package
1. Introduction – PMQFP144-2 package
– Submicron CMOS technology
The VCT 49xyI, VCT 48xyI is an IC family of high-qual-
ity single-chip TV processors. Modular design and – Low-power standby mode
deep-submicron technology allow the economic inte-
gration of features in all classes of single-scan TV – Single 20.25 MHz reference crystal
sets. The VCT 49xyI, VCT 48xyI family is based on – 8-bit 8051 instruction set compatible CPU
functional blocks contained and approved in existing
products like DRX 396xA, MSP 34x5G, VSP 94x7B, – Up to 256 kB on-chip program ROM
DDP 3315C, and SDA 55xx. – WST, PDC, VPS, and WSS acquisition
Each member of the family contains the entire IF, – Closed Caption and V-chip acquisition
audio, video, display, and deflection processing for 4:3 – Up to 10 pages on-chip teletext memory
and 16:9 50/60-Hz mono and stereo TV sets. The inte-
grated microcontroller is supported by a powerful OSD – Multi-standard QSS IF processing with single SAW
generator with integrated Teletext & CC acquisition – FM Radio and RDS with standard TV tuner
including on-chip page memory.
– TV-sound demodulation:
• all A2 standards
• all NICAM standards
Video & Sound IF
DRX 396xA • BTSC/SAP with MNR (DBX optional)
• EIA-J
– Baseband sound processing for loudspeaker chan-
nel:
Audio Processing
MSP 34x5G • volume and balance
• bass/treble or equalizer
• loudness and spatial effect (e.g. pseudo stereo)
• Micronas AROUND (virtual Dolby optional)
Video Processing
VSP 94x7B
VCT 49xyI • Micronas BASS
• further optional and licence requiring sound
enhancements as BBE, SRS Wow and Micronas
VOICE
Display & Deflection
– CVBS, S-VHS, YCrCb and RGB inputs
DDP 3315C
– 4H adaptive comb filter (PAL/NTSC)
– multi-standard color decoder (PAL/NTSC/SECAM)
Control, OSD, Text – Nonlinear horizontal scaling “panorama vision”
SDA 55xx
– Luma and chroma transient improvement (LTI, CTI)
– Non-linear color space enhancement (NCE)
Fig. 1–1: Single-chip VCT 49xyI, VCT 48xyI
– Dynamic black level expander (BLE)
– Scan velocity modulation output
– Soft start/stop of H-drive
– Vertical angle and bow correction
– Average and peak beam current limiter
– Nonlinear and dynamic EHT compensation
– Black switch off procedure (BSO)
89
__________________________________________________________________________________________________________________
1.2. Chip Architecture
SPEAKER
TAGC
AOUT
AIN
SIF
IFIN+ IF IF Sound Audio

IFIN- Frontend Processor Demodulator Processor
PROT
HOUT
HFLB
VERT
CVBS in Comb Color
Filter Decoder Display & EW
YCrCb in Video Panorama Video
Deflection SVM
RGB in Frontend Scaler Backend
Component Processor RGB out
CVBS out Interface RGB in
SENSE
RSW
I2C Master/
Bus Display I2C
Slicer Slave
Arbiter Generator
Timer
CRT
PWM RESETQ
24kB CPU Reset & Test
ADC
Char ROM 8051 Logic TEST
UART
Watchdog
RTC
256kB Memory Clock XTAL1
20kB XRAM
Prog ROM Interface I/O-Ports Generator XTAL2
ADB, DB, PSENQ, Pxy

PSWEQ, WRQ, RDQ
Fig. 1–2: Block diagram of the VCT 49xyI, VCT 48xyI
__________________________________________________________________________
90
__________________________________________________________________________________________________________________
4.2. Pin Connections and Short Descriptions
NC = not connected
LV = if not used, leave vacant
OBL = obligatory; connect as described in circuit diagram
IN = Input Pin
OUT = Output Pin
SUPPLY = Supply Pin
Pin No. Pin Name Type Connection Short Description

PMQFP144-2
PSSDIP88-1
PSSDIP88-2
(If not used)
1 88 128 GND SUPPLY OBL Ground Platform

2 87 129 VSUP5.0BE SUPPLY OBL Supply Voltage Analog Video Back-end, 5.0 V
3 86 130 TEST IN GND Test Input, reserved for Test
4 85 131 VERT+ OUT GND Differential Vertical Sawtooth Output
5 84 132 VERT- OUT GND Differential Vertical Sawtooth Output
6 83 133 EW OUT GND Vertical Parabola Output
7 82 134 RSW2 OUT LV Range Switch 2 Output
8 81 135 RSW1 OUT LV Range Switch 1 Output
9 80 136 SENSE IN GND Sense ADC Input
10 79 137 GNDM IN GND Reference Ground for Sense ADC
11 78 138 FBIN IN GND Fast Blank Input, Back-end
12 77 139 RIN IN GND Analog Red Input, Back-end
13 76 140 GIN IN GND Analog Green Input, Back-end
14 75 141 BIN IN GND Analog Blue Input, Back-end
15 74 142 SVMOUT OUT VSUP5.0BE Scan Velocity Modulation Output
16 73 143 ROUT OUT VSUP5.0BE Analog Red Output
17 72 144 GOUT OUT VSUP5.0BE Analog Green Output
18 71 1 BOUT OUT VSUP5.0BE Analog Blue Output
19 70 2 VRD OBL Reference Voltage for RGB DACs
20 69 3 XREF OBL Reference Current for RGB DACs
21 68 4 VSUP3.3BE SUPPLY OBL Supply Voltage Analog Video Back-end, 3.3 V
24 65 7 VSUP3.3IO SUPPLY OBL Supply Voltage I/O Ports, 3.3 V
(main and standby supply)
25 64 8 VSUP3.3DAC SUPPLY OBL Supply Voltage Video DACs, 3.3 V
26 63 9 GNDDAC SUPPLY OBL Ground Video DACs
__________________________________________________________________________
91
__________________________________________________________________________________________________________________
ADVANCE INFORMATION VCT 49xyI, VCT 48xyI

Pin No. PMQFP144-2 Pin Name Type Connection Short Description

PSSDIP88-1
PSSDIP88-2
(If not used)
27 62 10 SAFETY IN GND Safety Input

28 61 11 HFLB IN HOUT Horizontal Flyback Input
29 60 12 HOUT OUT LV Horizontal Drive Output
30 59 13 VPROT IN GND Vertical Protection Input
37 PWMV OUT LV PWM Vertical Output
38 DFVBL OUT LV Dynamic Focus Vertical Blanking Output
31 58 39 SDA IN/OUT OBL I2C Bus Data Input/Output

32 57 40 SCL IN/OUT OBL I2C Bus Clock Input/Output
33 56 41 P21 IN/OUT LV Port 2, Bit 1 Input/Output
43 46 53 VSUP3.3FE SUPPLY OBL Supply Voltage Analog Video Front-end, 3.3 V
46 43 56 VSUP1.8FE SUPPLY OBL Supply Voltage Analog Video Front-end, 1.8 V
47 42 57 VOUT3 OUT LV Analog Video 3 Output
50 39 60 VIN1 IN GND Analog Video 1 Input
92
__________________________________________________________________________________________________________________

PSSDIP88-1
PSSDIP88-2
(If not used)

63 26 100 XTAL2 OUT OBL Analog Crystal Output
64 25 101 XTAL1 IN OBL Analog Crystal Input
65 24 102 VSUP1.8DIG SUPPLY OBL Supply Voltage Digital Core, 1.8 V
68 21 105 VSUP3.3DIG SUPPLY OBL Supply Voltage Digital Core, 3.3 V
69 20 106 VSUP5.0IF SUPPLY OBL Supply Voltage IF ADC, 5.0 V
70 19 107 VSUP5.0FE SUPPLY OBL Supply Voltage Analog IF Front-end, 5.0 V
71 18 108 RESETQ IN/OUT OBL Reset Input/Output
72 17 109 IFIN+ IN VREFIF Differential IF Input
73 16 110 IFIN- IN VREFIF Differential IF Input
74 15 111 VREFIF OBL Reference Voltage, IF ADC
75 14 112 TAGC OUT LV Tuner AGC Output
76 13 113 AIN1R / IN/OUT GND Analog Audio 1 Input, Right
SIF Analog 2nd Sound IF Output
77 12 114 AIN1L IN GND Analog Audio 1 Input, Left
78 11 115 AIN2R IN GND Analog Audio 2 Input, Right
79 10 116 AIN2L IN GND Analog Audio 2 Input, Left
117 AIN3R IN GND Analog Audio 3 Input, Right
118 AIN3L IN GND Analog Audio 3 Input, Left
119 AOUT2R OUT LV Analog Audio 2 Output, Right
120 AOUT2L OUT LV Analog Audio 2 Output, Left
80 9 AIN3R / IN / LV Analog Audio 3 Input, Right
AOUT2R OUT Analog Audio 2 Output, Right
81 8 AIN3L / IN / LV Analog Audio 3 Input, Left
AOUT2L OUT Analog Audio 2 Output, Left
82 7 121 AOUT1R OUT LV Analog Audio 1 Output, Right
83 6 122 AOUT1L OUT LV Analog Audio 1 Output, Left
93
__________________________________________________________________________________________________________________


PSSDIP88-1
PSSDIP88-2
(If not used)
84 5 123 SPEAKERR OUT LV Analog Loudspeaker Output, Right

85 4 124 SPEAKERL OUT LV Analog Loudspeaker Output, Left
86 3 125 VREFAU OBL Reference Voltage, Audio
87 2 126 VSUP8.0AU SUPPLY OBL Supply Voltage Analog Audio, 8.0 V
71 P37 / IN/OUT LV Port 3, Bit 7 Input/Output
656IO7 Digital 656 Bus 7 Input/Output
76 GNDEIO SUPPLY OBL Ground Extended I/O Ports
77 VSUP3.3EIO SUPPLY OBL Supply Voltage Extended I/O Ports, 3.3 V

656VIO Digital 656 Vsync Input/Output
656HIO Digital 656 Hsync Input/Output
656CLKIO Digital 656 Clock Input/Output
31 ADB19 OUT LV Address Bus 19 Output
94
__________________________________________________________________________________________________________________

PSSDIP88-1
PSSDIP88-2
(If not used)

88 DB0 IN/OUT LV Data Bus 0 Input/Output
32 RDQ OUT LV Data Read Enable Output
33 WRQ OUT LV Data Write Enable Output
34 OCF OUT LV Opcode Fetch Output
35 ALE OUT LV Address Latch Enable Output
36 RSTQ OUT LV Internal CPU Reset Output
97 PSENQ OUT LV Program Store Enable Output
20 PSWEQ OUT LV Program Store Write Enable Output
51 XROMQ IN OBL External ROM Enable Input
52 EXTIFQ IN LV Enable External Interface Input
24 STOPQ IN LV Stop CPU Input
25 ENEQ IN LV Enable Emulation Input
95
__________________________________________________________________________________________________________________

4.3. Pin Descriptions lines to the power supply. Decoupling capacitors from
VSUPxx to GND have to be placed as closely as pos-
4.3.1. Supply Pins sible to these pins. It is recommended to use more
than one capacitor. By choosing different values, the
VSUP1.8DIG − Supply Voltage 1.8 V frequency range of active decoupling can be extended.
This pin is main and standby supply for the digital core
logic of controller, video, display and deflection pro-
cessing. 4.3.2. IF Pins
VSUP1.8FE − Supply Voltage 1.8 V VREFIF − Reference Voltage for analog IF (Fig. 4–6)
This pin is main and standby supply for the analog This pin must be connected to GND via a circuitry
video front-end. according to the application circuit. Low inductance
caps are necessary.
VSUP3.3FE − Supply Voltage 3.3 V
This pin is main and standby supply for the analog IFIN+, IFIN- − Balanced IF Input (Fig. 4–4)
video front-end. These pins must be connected to the SAW filter out-
put. The SAW filter has to be placed as close as possi-
VSUP3.3IO − Supply Voltage 3.3 V ble. The layout of the IF input should be symmetrical
This pin is main and standby supply for the digital I/O- with respect to GND.
ports.
SIF − 2nd Sound IF Output (Fig. 4–7)
VSUP3.3DIG − Supply Voltage 3.3 V Output level is set via I2C-Bus. An appropriate sound
This pin is main supply for the digital core logic of IF processor (e.g. MSP) can be connected to this pin.
and audio processing and digital video back-end. This pin is also configurable as audio input (see
Fig. 4–8).
VSUP3.3BE − Supply Voltage 3.3 V
This pin is main supply for the analog video back-end. TAGC − Tuner AGC Output (Fig. 4–5)
This pin controls the delayed tuner AGC. As it is a
VSUP5.0FE − Supply Voltage 5.0 V noise-shaped-I-DAC output, it has to be connected
This pin is main supply for the analog IF front-end. according to the application circuit.
VSUP5.0IF − Supply Voltage 5.0 V

This pin is main supply for the IF ADC. 4.3.3. Audio Pins
VSUP5.0BE − Supply Voltage 5.0 V VREFAU – Reference Voltage for Analog Audio (Fig.
This pin is main supply for the analog video back-end. 4–12)
This pin serves as the internal ground connection for
VSUP8.0AU − Supply Voltage 8.0 V the analog audio circuitry. It must be connected to the
This pin is main supply for the analog audio process- GND pin with a 3.3 μF and a 100 nF capacitor in paral-
ing. lel. This pins shows a DC level of typically 3.77 V.
GND − Ground Platform AIN1 L – Audio 1 Inputs (Fig. 4–8)

This pin is main ground for all above supplies. The analog input signal for audio 1 is fed to this pin.
Analog input connection must be AC coupled.
VSUP3.3DAC − Supply Voltage 3.3 V
This pin is main supply for the video DACs. AIN1 R – Audio 1 Inputs (Fig. 4–8)
The analog input signal for audio 1 is fed to this pin.
GNDDAC − Ground for 3.3 V Video DAC Supply Analog input connection must be AC coupled. This pin
is also configurable as sound IF output (see Fig. 4–7).
VSUP3.3EIO − Supply Voltage 3.3 V
This pin is main and standby supply for the extended AIN2 R/L – Audio 2 Inputs (Fig. 4–8)
digital I/O-ports available in QFP package only. It is The analog input signal for audio 2 is fed to this pin.
internally connected to VSUP3.3IO. Analog input connection must be AC coupled.
GNDEIO − Ground for 3.3 V Extended I/O Supply AIN3 R/L – Audio 3 Inputs (Fig. 4–8)
It is internally connected to GND. The analog input signal for audio 3 is fed to this pin.
Analog input connection must be AC coupled.
Application Note:
All GND pins must be connected to a low-resistive
ground plane underneath the IC. All supply pins must
be connected separately with short and low-resistive
96
__________________________________________________________________________________________________________________
AOUT1 R/L – Audio 1 Outputs (Fig. 4–9) XREF − DAC Current Reference (Fig. 4–18)
Output of the analog audio 1 signal. Connections to External reference resistor for DAC output currents,
these pins are intended to be AC coupled. typical 10 kΩ to adjust the output current of the D/A
converters. (see recommended operating conditions).
AOUT2 R/L – Audio 2 Outputs (Fig. 4–9) This resistor has to be connected to ground as closely
Output of the analog audio 2 signal. Connections to as possible to the pin.
these pins are intended to be AC coupled.
SPEAKER R/L – Loudspeaker Outputs (Fig. 4–11) 4.3.5. CRT Pins

Output of the loudspeaker signal. A 1 nF capacitor to
GND must be connected to these pins. Connections to HOUT − Horizontal Drive Output (Fig. 4–19)
these pins are intended to be AC-coupled. This open source output supplies the drive pulse for
the horizontal output stage. An external pulldown
resistor has to be used. The polarity and gating with
4.3.4. Video Pins the flyback pulse are selectable by software.
VIN 1–11 − Analog Video Input (Fig. 4–13) HFLB − Horizontal Flyback Input (Fig. 4–20)
These are the analog video inputs. A CVBS, S-VHS, Via this pin the horizontal flyback pulse is supplied to
YCrCb or RGB/FB signal is converted using the luma, the VCT 49xyI, VCT 48xyI.
chroma and component AD converters. The input sig-
nals must be AC-coupled by 100nF. In case of an ana- VPROT − Vertical Protection Input (Fig. 4–20)
log fast blank signal carrying alpha blending information The vertical protection circuitry prevents the picture
the input signal must be DC-coupled. tube from burn-in in the event of a malfunction of the
vertical deflection stage. If the peak-to-peak value of
VOUT 1-3 − Analog Video Output (Fig. 4–14) the sawtooth signal from the vertical deflection stage is
The analog video inputs that are selected by the video too small, the RGB output signals are blanked.
source select matrix are output at these pins.
SAFETY − Safety Input (Fig. 4–20)
RIN, GIN, BIN − Analog RGB Input (Fig. 4–15) This input has two thresholds. A signal between the
These pins are used to insert an external analog RGB lower and upper threshold means normal function. A
signal, e.g. from a SCART connector which can be signal below the lower threshold or above the upper
switched to the analog RGB outputs with the fast blank threshold is detected as malfunction and the RGB sig-
signal. Separate brightness and contrast settings for nals will be blanked.
the external analog signals are provided.
VERT+, VERT− − Vertical Sawtooth Output (Fig. 4–21)
FBIN − Fast Blank Input (Fig. 4–16) These pins supply the symmetrical drive signal for the
This pin is used to switch the RGB outputs to the exter- vertical output stage. The drive signal is generated
nal analog RGB inputs. The active level (low or high) with 15-bit precision. The analog voltage is generated
can be selected by software. by a 4 bit current-DAC with an external resistor of
6.8 kΩ and uses digital noise shaping.
ROUT, GOUT, BOUT − Analog RGB Output (Fig. 4–
17) EW − East-West Parabola Output (Fig. 4–22)
These pins are the analog Red/Green/Blue outputs of This pin supplies the parabola signal for the East-West
the back-end. The outputs are current sinks. correction. The drive signal is generated with 15 bit
precision. The analog voltage is generated by a 4 bit
SVMOUT − Scan Velocity Modulation Output (Fig. 4– current-DAC with an external resistor of 6.8 kΩ and
17) uses digital noise shaping.
This output delivers the analog SVM signal. The D/A
converter is a current sink like the RGB D/A convert- PWMV − PWM Vertical Output (Fig. 4–19)
ers. At zero signal the output current is 50% of the This pin provides an adjustable vertical parabola with 7
maximum output current. bit resolution and approx. 79.4 kHz PWM frequency.
VRD − DAC Reference Decoupling (Fig. 4–18) DFVBL − Dynamic Focus Vertical Blanking (Fig. 4–19)
Via this pin the RGB-DAC reference voltage is decou- This pin supplies the blank pulse for dynamic focus
pled by an external capacitor. The DAC output currents during vertical blanking period or a free programmable
depend on this voltage, therefore a pulldown transistor horizontal pulse for horizontal dynamic focus genera-
can be used to shut off all beam currents. A decoupling tion. Alternatively it can be programmed as FIELD out-
capacitor of 4.7 μF in parallel to 100 nF (low induc- put, delivering even/odd field information.
tance) is required.
97
__________________________________________________________________________________________________________________

SENSE − Measurement ADC Input (Fig. 4–25) ADB0−ADB19 − Address Bus Output (Fig. 4–33)
This is the input of the analog to digital converter for These 20 lines provide the CPU address bus output to
the picture and tube measurement. Three measure- access external memory.
ment ranges are selectable with RSW1 and RSW2.
DB0−DB7 − Data Bus Input/Output (Fig. 4–34)
GNDM − Measurement ADC Reference Input These 8 lines provide the bidirectional CPU data bus
This is the reference ground for the measurement A/D to access external memory.
converter. Connect this pin to GND.
WRQ − Data Write Enable Output (Fig. 4–33)
RSW1 − Range Switch1 for Measuring ADC (Fig. 4– This pin controls the direction of data exchange
23) between the CPU and the external data memory
These pin is an open drain pull-down output. During device (SRAM).
cutoff and white drive measurement the switch is off.
During the rest of time it is on. The RSW1 pin can be RDQ − Data Read Enable Output (Fig. 4–33)
used as second measurement ADC input for picture This pin is used to enable the output driver of the
beam current measurement. external data memory device (SRAM) for read access.
RSW2 − Range Switch2 for Measuring ADC (Fig. 4– PSENQ − Program Store Enable Output (Fig. 4–33)
24) This pin is used to enable the output driver of the
These pin is an open drain pull-down output. During external program memory device (ROM/FLASH) for
cutoff measurement the switch is off. During white read access.
drive measurement the switch is on. Also during the
rest of time it is on. It is used to set the range for white PSWEQ − Program Store Write Enable Output (Fig. 4–
drive current measurement. 33)
This pin is used to write into the external program flash
memory device.
4.3.6. Controller Pins
XROMQ − External ROM Enable Input (Fig. 4–35)
XTAL1 − Crystal Input and XTAL2 Crystal Output (Fig. This pin must be pulled low to access the external pro-
4–26) gram memory. XROMQ has an internal pull-up resis-
These pins connect a 20.25 MHz crystal to the internal tor.
oscillator. An external clock can be fed into XTAL2.
EXTIFQ − Enable External Memory Interface Input
RESETQ − Reset Input/Output (Fig. 4–27) (Fig. 4–35)
A low level on this pin resets the VCT 49xyI, VCT This pin must be pulled low to enable the external
48xyI. The internal CPU can pull down this pin to reset memory interface. EXTIFQ has an internal pull-up
external devices connected to this pin. resistor.
TEST − Test Input (Fig. 4–28) STOPQ − Stop CPU Input (Fig. 4–35)
This pin enables factory test modes. For normal opera- Applying a low level during the input phase freezes the
tion, it must be connected to ground. real-time relevant internal peripherals such as timers
and interrupt controller. STOPQ has an internal pull-up
SCL − I2C Bus Clock (Fig. 4–29) resistor.
This pin delivers the I2C bus clock line. The signal can
be pulled down by external slave ICs to slow down ENEQ − Enable Emulation Input (Fig. 4–35)
data transfer. Only if this pin is set to low level, STOPQ and OCF are
operational. ENEQ has an internal pull-up resistor.
SDA − I2C Bus Data (Fig. 4–29)
This pin delivers the I2C bus data line. ALE − Address Latch Enable Output (Fig. 4–33)
This signal indicates changes on the address bus.
P10−P13, P20−P23 − I/O Port (Fig. 4–30)
These pins provide CPU controlled I/O ports. OCF − Opcode Fetch Output (Fig. 4–33)
A high level driven by the CPU during output phase
P14−P17 − I/O Port (Fig. 4–31) indicates the beginning of a new instruction.
These pins provide CPU controlled I/O ports. Addition-
ally they can be used as analog inputs for the control- RSTQ − Internal CPU Reset Input/Output (Fig. 4–36)
ler ADC. This pin is used for emulation purpose only. A low level
on this pin resets the CPU. It also indicates an internal
P24−P26, P30−P37 − I/O Port (Fig. 4–32) reset of the CPU. RSTQ has an internal pull-up resis-
These pins provide CPU controlled I/O ports. tor.
98
__________________________________________________________________________________________________________________
4.4. Pin Configuration
GND 45 44 GND GND 45 44 GND

VSUP1.8FE 46 43 VSUP3.3FE VSUP3.3FE 46 43 VSUP1.8FE
VOUT3 47 42 P10 P10 47 42 VOUT3
VOUT2 48 41 P11 P11 48 41 VOUT2
VOUT1 49 40 P12 P12 49 40 VOUT1
VIN1 50 39 P13 P13 50 39 VIN1
VIN2 51 38 P14 P14 51 38 VIN2
VIN3 52 37 P15 P15 52 37 VIN3
VIN4 53 36 P16 P16 53 36 VIN4
VIN5 54 35 P17 P17 54 35 VIN5
VIN6 55 34 P20 P20 55 34 VIN6
VIN7 56 33 P21 P21 56 33 VIN7
VCT 49xyI PY
VCT 49xyI PZ
VIN8 57 32 SCL SCL 57 32 VIN8
VIN9 58 31 SDA SDA 58 31 VIN9
VIN10 59 30 VPROT VPROT 59 30 VIN10
VIN11 60 29 HOUT HOUT 60 29 VIN11
P23 61 28 HFLB HFLB 61 28 P23
P22 62 27 SAFETY SAFETY 62 27 P22
XTAL2 63 26 GNDDAC GNDDAC 63 26 XTAL2
XTAL1 64 25 VSUP3.3DAC VSUP3.3DAC 64 25 XTAL1
VSUP1.8DIG 65 24 VSUP3.3IO VSUP3.3IO 65 24 VSUP1.8DIG
VSUP3.3DIG 68 21 VSUP3.3BE VSUP3.3BE 68 21 VSUP3.3DIG
VSUP5.0IF 69 20 XREF XREF 69 20 VSUP5.0IF
VSUP5.0FE 70 19 VRD VRD 70 19 VSUP5.0FE
RESETQ 71 18 BOUT BOUT 71 18 RESETQ
IFIN+ 72 17 GOUT GOUT 72 17 IFIN+
IFIN- 73 16 ROUT ROUT 73 16 IFIN-
VREFIF 74 15 SVMOUT SVMOUT 74 15 VREFIF
TAGC 75 14 BIN BIN 75 14 TAGC
SIF / AIN1R 76 13 GIN GIN 76 13 SIF / AIN1R
AIN1L 77 12 RIN RIN 77 12 AIN1L
AIN2R 78 11 FBIN FBIN 78 11 AIN2R
AIN2L 79 10 GNDM GNDM 79 10 AIN2L
AIN3R / AOUT2R 80 9 SENSE SENSE 80 9 AIN3R / AOUT2R
AIN3L / AOUT2L 81 8 RSW1 RSW1 81 8 AIN3L / AOUT2L
AOUT1R 82 7 RSW2 RSW2 82 7 AOUT1R
AOUT1L 83 6 EW EW 83 6 AOUT1L
SPEAKERR 84 5 VERT- VERT- 84 5 SPEAKERR
SPEAKERL 85 4 VERT+ VERT+ 85 4 SPEAKERL
VREFAU 86 3 TEST TEST 86 3 VREFAU
VSUP8.0AU 87 2 VSUP5.0BE VSUP5.0BE 87 2 VSUP8.0AU
Fig. 4–1: PSSDIP88-1 package Fig. 4–2: PSSDIP88-2 package (pinning mirrored)
99
__________________________________________________________________________________________________________________

P24 / 656CLKIO
P25 / 656HIO
P26 / 656VIO
P30 / 656IO0
P31 / 656IO1
P32 / 656IO2
P33 / 656IO3
P34 / 656IO4
P35 / 656IO5
VSUP3.3DIG
VSUP1.8DIG
VSUP3.3EIO
VSUP5.0FE
VSUP5.0IF
RESETQ
GNDEIO
PSENQ
ADB10
XTAL1
XTAL2
ADB0
ADB1
ADB2
ADB3
GND
GND
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
P22
P23
101
98
102
100
97
96
92
91
90
88
86
84
81
80
105
104
103
99
95
94
93
89
87
85
83
82
79
78
108
107
106
77
76
75
74
73
IFIN+ 109 72 P36 / 656IO6
IFIN- 110 71 P37 / 656IO7
VREFIF 111 70 VIN11
TAGC 112 69 VIN10
AIN1R / SIF 113 68 VIN9
AIN1L 114 67 VIN8
AIN2R 115 66 VIN7
AIN2L 116 65 VIN6
AIN3R 117 64 VIN5
AIN3L 118 63 VIN4
AOUT2R 119 62 VIN3
AOUT2L 120 61 VIN2
AOUT1R 121 60 VIN1
AOUT1L 122 59 VOUT1
SPEAKERR 123 58 VOUT2
SPEAKERL 124 57 VOUT3
VREFAU 125 56 VSUP1.8FE
GND
VCT 49xyI
VSUP8.0AU 126 55
GND 127 54 GND

GND 128 53 VSUP3.3FE
VSUP5.0BE 129 52 EXTIFQ
TEST 130 51 XROMQ
VERT+ 131 50 P10
VERT- 132 49 P11
EW 133 48 P12
RSW2 134 47 P13
RSW1 135 46 P14
SENSE 136 45 P15
GNDM 137 44 P16
FBIN 138 43 P17
RIN 139 42 P20
GIN 140 41 P21
BIN 141 40 SCL
SVMOUT 142 39 SDA
ROUT 143 38 DFVBL / FIELD
GOUT 144 37 PWMV
10
11
12
13
14
15
16
17
19
20
21
18
24
25
26
27
30
31
33
34
35
36
22
23
28
29
32
8
1
2
3
4
5
9
6
ADB11
ADB13
ADB14
ADB17
ADB18
ADB16
ADB15
ADB12
ADB19
VSUP3.3DAC
GNDDAC
SAFETY
ALE
VSUP3.3BE
ADB9
ADB7
XREF
ADB8
ADB6
ADB5
ADB4
OCF
VRD
GND
GND
VSUP3.3IO
HFLB
ENEQ
RDQ
STOPQ
PSWEQ
BOUT
WRQ
RSTQ
HOUT
VPROT
Fig. 4–3: PMQFP144-2 package
100
__________________________________________________________________________________________________________________
WM8725
99dB Stereo DAC
DESCRIPTION FEATURES
WM8725 is a high-performance stereo DAC designed for • 99dB SNR performance
use in portable audio equipment, video CD players and • Stereo DAC with input sampling from 8kHz to 96kHz
2
similar applications. It comprises selectable normal or I S • Additional mute feature
compatible serial data interfaces for 16 to 24-bit digital • Normal or I2S compatible data format
inputs, high performance digital filters, and sigma-delta • Sigma-delta design with 64x oversampling
output DACs, achieving an excellent 99dB signal-to-noise • System clock 256fs or 384fs
performance. • Supply range 3V to 5V
• 14-pin SOIC package
The device is available in a 14-pin SOIC package that
offers selectable mute and de-emphasis functions using a APPLICATIONS
minimum of external components.
• Portable audio equipment
• Video CD players
BLOCK DIAGRAM
__________________________________________________________________________
101
__________________________________________________________________________________________________________________
WM8725 Production Data
PIN CONFIGURATION
LRCIN 1 14 SCKI
DIN 2 13 FORMAT
BCKIN 3 12 DEEMPH
WM8725
NC 4 11 NC
CAP 5 10 MUTE
VOUTR 6 9 VOUTL
GND 7 8 VDD
ORDERING INFORMATION
DEVICE TEMPERATURE PACKAGE MOISTURE SENSITIVITY PEAK BODY
RANGE LEVEL TEMPERATURE
o o o
WM8725ED -25 C to +85 C 14-pin SOIC MSL1 240 C
-25oC to +85oC 14-pin SOIC

WM8725ED/R MSL1 240oC
(tape and reel)
WM8725GED/V MSL2 260oC
(lead free)
WM8725GED/RV MSL2 260oC
(lead free tape and reel)
Note:
Reel quantity: 3,000
PD Rev 4.1 August 2004
102
__________________________________________________________________________________________________________________
WM8725 Production Data
PIN DESCRIPTION
PIN NAME TYPE DESCRIPTION
1 LRCIN Digital input Sample rate clock input
2 DIN Digital input Serial data input
3 BCKIN Digital input Bit clock input
4 NC No connect No internal connection
5 CAP Analogue output Analogue internal reference
6 VOUTR Analogue output Right channel DAC output
7 GND Supply 0V supply
8 VDD Supply Positive supply
9 VOUTL Analogue output Left channel DAC output
10 MUTE Digital input Mute control, high = muted. Internal pull-down
11 NC No connect No internal connection
12 DEEMPH Digital input De-emphasis select, high = de-emphasis ON. Internal pull-up
13 FORMAT Digital input Data input format select, low = normal, high = I2S. Internal pull-up
14 SCKI Digital input System clock input (256fs or 384fs)
PD Rev 4.1 August 2004
103

Lcd+Profilo Telra+PT1000

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26”-32” LCD-TV

EDD1232AAFA (4M wordsx32 bits)

VCT 49xyl, VCT 48xyl .................... 89

1. Assembling/ Disassembling Procedure

Please follow the assembly instructions explained below;

1-) Remove Back Cover

6. EJECT BUTTON HOLDER

2. SAFETY INSTRUCTIONS AND PRECAUTIONS

HANDLING THE MOS CHIP COMPONENTS

2.1.1. Mounting Precautions

2.1.2 Operating Precautions

causes metallic foreign material and deal LCM a fatal blow)

2.1.3. Electrostatic Discharge Control

2.1.4. Precautions for Strong Light Exposure

2.1.6. Handling Precautions for Protection Film

Video Level 0.7±0.15 V p-p 75

Audio Level 0.5±0.05 V rms NTSC

3.3 Supported Resolutions

MAIN TUNER PLL TUNER IF1

PIP TUNER PLL TUNER PIP CVBS

SCART AUDIO INPUT DDR RAM

AV AUDIO OUT AUDIO

PC INPUT PC AUDIO INPUT SIDE AV CVBS INPUT

TUNER +3.3V_VID +1.8V_VCTi +5V_TUNER

+12V +8V DDC IC

I2C BLOCK DIAGRAM

1) J916: For IR, LED - Wafer

Pin No. Symbol Description I/O Remarks

2) J917: For Local Key - Wafer

Pin No. Symbol Description I/O Remarks

3) J909: For Debugging - Wafer

Pin No. Symbol Description I/O Remarks

4) J912: For Debugging - Wafer

Pin No. Symbol Description I/O Remarks

5) J915: For HDCP Writing - Wafer

Pin No. Symbol Description I/O Remarks

6) J924: For DVD interface, Wafer

Pin No. Symbol Description I/O Remarks

7) J925: For DVD/DVB Power Supply, Wafer

Pin No. Symbol Description I/O Remarks

8) J926: For DVB Upgrade Interface, Wafer

Pin No. Symbol Description I/O Remarks

9) J927: For IR, Interface (DVB), Wafer

Pin No. Symbol Description I/O Remarks

10) J919: For Headphone Drive, Wafer

Pin No. Symbol Description I/O Remarks

11) J920: For LCD Speaker Output, Wafer

Pin No. Symbol Description I/O Remarks

12) J922: For PDP Speaker Output, Wafer

Pin No. Symbol Description I/O Remarks

13) J502: For LCD Side AV, Wafer

Pin No. Symbol Description I/O Remarks

14) J923: For PDP Side AV, Wafer

Pin No. Symbol Description I/O Remarks

15) J701: For Logic Power Supply – LCD, Wafer

Pin No. Symbol Description I/O Remarks

16) J702: For Logic Power Supply – SDI PDP, Wafer

Pin No. Symbol Description I/O Remarks

17) J921: For Logic Power Supply – SDI PDP, Wafer

Pin No. Symbol Description I/O Remarks

Video Level 0.7±0.15 V p-p 75

PICTURE Menu COLOR TEMP NORMAL, COOL, WARM

SOUND Menu Volume 100 Steps

TRANSPARENCY 100 Steps