dsPIC® DSC

DSP Library
Summary Features
The dsPIC Digital Signal Controller (DSC) DSP Library Key features of the dsPIC DSC DSP Library include:
provides a set of speed optimized functions for the most • 49 total functions
common digital signal processing applications. The dsPIC • Full compliance with the Microchip MPLAB®C30 C
DSC DSP Library provides significant performance savings compiler, assembler and linker
over equivalent functions coded in C and allows developers
• Simple user interface – only one library file and one
to dramatically shorten their development time. The dsPIC
header file
DSC DSP library may be used with any dsPIC DSC variant.
• Functions are both C and assembly callable
The dsPIC DSC DSP Library is written predominantly in • FIR filtering functions include support for lattice,
Assembly language and makes extensive use of the dsPIC decimating, interpolating and LMS filters
DSC DSP instruction set and hardware resources, including
• IIR filtering functions include support for canonic,
X and Y memory addressing, modulo addressing, bit-
transposed canonic and lattice filters
reversed addressing, 9.31 saturation and REPEAT and DO
loops. • FIR and IIR functions may be used with the filter files
generated by the dsPIC® DSC Digital Filter Design Tool
The dsPIC DSC DSP Library provides functions for the • Transform functions include support for in-place and
following: out-of-place DCT, FFT and IFFT transforms
• Vector operations • Window functions include support for Bartlett,
• Matrix operations Blackman, Hamming, Hanning and Kaiser windows
• Filtering operations • Support for program space visibility
• Transform operations • Complete function profile information including
• Window® operations register usage, cycle count and function size
information
Function Execution Times
Cycle Count Number Execution Time
Function
Equation
Conditions*
of Cycles @40 MIPS
Devices Supported
Complex FFT** — N=64 3739 93.5 μs • All processors in the dsPIC DSC families
Complex FFT** — N=128 8485 212.1 μs
Complex FFT** — N=256 19055 476.4 μs
Single Tap FIR — — 1 25 ns
Block FIR 53+N(4+M) N=32, M=32 1205 30.2 μs
Block FIR Lattice 41+N(4+7M) N=32, M=32 7337 183.5 μs
Block IIR Canonic 36+N(8+7S) N=32, S=4 1188 29.7 μs
Block IIR Lattice 46+N(16+7M) N=32, M=8 2350 58.7 μs
Matrix Add 20+3(C*R) C=8, R=8 212 5.3 μs
Matrix Transpose 16+C(6+3(R-1)) C=8, R=8 232 5.8 μs
Vector Dot
17+3N N=32 113 2.9 μs
Product
Vector Max 19+7(N-2) N=32 229 5.7 μs
Vector Multiply 17+4N N=32 145 3.6 μs
Vector Power 16+2N N=32 80 2.0 μs
*C= #columns, N=# samples, M=#taps, S=#sections, R=#rows
**Complex FFT routine inherently prevents overflow.
1 cycle = 25 nanoseconds @ 40 MIPS

DS01033B-28 www.microchip.com