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L29 MicroOperations

The document discusses how a computer executes programs through a series of micro-operations. It describes the fetch cycle which involves 4 main registers - the memory address register, memory buffer register, program counter, and instruction register. The fetch sequence loads the instruction address from the program counter to the memory address register, then loads instruction data from memory to the memory buffer register. It also increments the program counter. The instruction is then loaded from the memory buffer register to the instruction register. The document outlines the roles of the control unit in sequencing micro-operations and executing the steps to complete instructions.

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69 views19 pages

L29 MicroOperations

The document discusses how a computer executes programs through a series of micro-operations. It describes the fetch cycle which involves 4 main registers - the memory address register, memory buffer register, program counter, and instruction register. The fetch sequence loads the instruction address from the program counter to the memory address register, then loads instruction data from memory to the memory buffer register. It also increments the program counter. The instruction is then loaded from the memory buffer register to the instruction register. The document outlines the roles of the control unit in sequencing micro-operations and executing the steps to complete instructions.

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domainname9
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Micro-Operations

• A computer executes a program


• Fetch/execute cycle
• Each cycle has a number of steps
• Called micro-operations
• Each step does very little & simple
• Atomic operation of CPU
Constituent Elements of Program
Execution
1) The Fetch Cycle
Mainly 4 registers are involved in fetch cycle

• Memory Address Register (MAR)


--Connected to address bus
--Specifies address for read or write operation
• Memory Buffer Register (MBR)
--Connected to data bus
--Holds data to write to memory or last data read from memory
• Program Counter (PC)
--Holds address of next instruction to be fetched
• Instruction Register (IR)
--Holds last instruction fetched
Fetch Sequence
• Address of next instruction is in PC
• Address moved to MAR
• Address of MAR is placed on address bus
• Control unit issues READ command
• Result (data from memory) appears on data bus
• Data from data bus copied into MBR
• PC incremented by 1 (in parallel with data fetch from
memory)
• Data (instruction) moved from MBR to IR
• MBR is now free for further data fetches
Fetch Sequence (symbolic)
• t1: MAR <- (PC)
• t2: MBR <- (memory)
PC <- (PC) +1
• t3: IR <- (MBR)
(tx = time unit/clock cycle)
or
• t1: MAR <- (PC)
• t2: MBR <- (memory)
• t3: PC <- (PC) +1
IR <- (MBR)
Rules for Clock Cycle Grouping
• Proper sequence must be followed
--MAR <- (PC) must precede MBR <- (memory)
• Conflicts must be avoided
--Must not read & write same register at same time
--MBR <- (memory) & IR <- (MBR) must not be in
same cycle
2) Indirect Cycle
In case of a one address instruction using indirect
mode of addressing following are the micro-
operations:

• MAR <- (IRaddress) - address field of IR


• MBR <- (memory)
• IRaddress <- (MBRaddress)

• IR is now in same state as if direct addressing had


been used
3) Interrupt Cycle
At completion of execution cycle, CPU checks of presence of
interrupt, if interrupt occurs then sequence of events to handle
the interrupt are:
• t1: MBR <-(PC)
• t2: MAR <- save-address ( address to which contents of PC
are to be saved)
PC <- routine-address
• t3: memory <- (MBR)

• If CPU provide multiple levels of interrupts


– May be additional micro-operations
– Saving context is done by interrupt handler routine, not micro-ops
4) Execute Cycle (ADD)
• Different for each instruction
• e.g. ADD R1,X - add the contents of location X to R1
, store the result in R1
• t1: MAR <- (IR(address))
• t2: MBR <- (memory)
• t3: R1 <- (R1) + (MBR)
• Note no overlap of micro-operations
Execute Cycle (ISZ)
• ISZ X - increment and skip if zero
– t1: MAR <- (IR(address))
– t2: MBR <- (memory)
– t3: MBR <- (MBR) + 1
– t4: memory <- (MBR)
– if (MBR == 0) then (PC <- (PC) + 1)
• Notes:
– Two Micro-operations done during t4 as conflict are not
there
Control of Processor

We have already seen that


• Programs are executed as a sequence of
instructions
• Each instruction consists of a series of steps that
make up the instruction cycle -- fetch, decode,
etc.
• Each of these steps are, in turn, made up of a
smaller series of steps called microoperations
Control of Processor
Functional Requirements

Thus, the control unit operation can be defined by


a) Defining the basic elements of the CPU
b) Defining the micro-operations the CPU performs
c) Determining the functions the control unit must
perform to cause the execution of the micro-
operations in the desired time sequence
– Sequencing
– Execution
a) Basic Elements of Processor
• ALU
• Registers
• Internal data paths
• External data paths
• Control Unit
b) Types of Micro-operation

• Transfer data between registers


• Transfer data from register to external interface (e.g.
system bus)
• Transfer data from external interface to register
• Perform arithmetic or logical ops, using registers
c) Functions of Control Unit
• Sequencing
– Causing the CPU to step through a series of
micro-operations in proper sequence
• Execution
– Causes each micro-op to be performed
• This is done using Control Signals
Control Signals (I/P)
• Clock
– One micro-instruction (or set of parallel micro-instructions)
per clock cycle
• Instruction register
– Op-code for current instruction determines which micro-
instructions are performed
• Flags
– Needed to determine the status of CPU
– Results of previous operations
• From control bus
– Interrupts
– Acknowledgements
The outputs are
• Within CPU
– Cause data movement
– Activate specific ALU functions
• Via control bus
– To memory
– To I/O modules
Hardwired Implementation

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