Mtech Vlsi

SATHYABAMA UNIVERSITY
(Established under section 3 of UGC Act, 1956)

Jeppiaar Nagar, Rajiv Gandhi Salai, Chennai - 119.
SYLLABUS
MASTER OF TECHNOLOGY PROGRAMME
IN
VLSI DESIGN
(4 SEMESTERS)
REGULATIONS 2010
SATHYABAMA UNIVERSITY FACULTY OF ELECTRONICS ENGINEERING
SATHYABAMA UNIVERSITY
REGULATIONS – 2010
Effective from the academic year 2010-2011 and applicable to the students admitted to the Master of Engineering
/ Technology / Architecture /Science (Four Semesters)
1. Structure of Programme
1.1 Every Programme will have a curriculum with syllabi consisting of theory and practical such as:
(i) General core courses like Mathematics
(ii) Core course of Engineering / Technology/Architecture / Science
(iii) Elective course for specialization in related fields
(iv) Workshop practice, Computer Practice, laboratory Work, Industrial Training, Seminar
Presentation, Project Work, Educational Tours, Camps etc.
1.2 Each semester curriculum shall normally have a blend of lecture course not exceeding 7 and practical
course not exceeding 4.
1.3 The medium of instruction, examinations and project report will be English.
2. Duration of the Programme
A student is normally expected to complete the M.E/M.Tech./M.Arch/M.Sc Programme in 4 semesters but in
any case not more than 8 consecutive semesters from the time of commencement of the course. The
Head of the Department shall ensure that every teacher imparts instruction as per the number of hours specified
in the syllabus and that the teacher teaches the full content of the specified syllabus for the course being
taught.
3. Requirements for Completion of a Semester
A candidate who has fulfilled the following conditions shall be deemed to have satisfied the requirement for
completion of a semester.
3.1 He/She secures not less than 90% of overall attendance in that semester.
3.2 Candidates who do not have the requisite attendance for the semester will not be permitted to
write the University Exams.
4. Examinations
The examinations shall normally be conducted between October and December during the odd semesters and
between March and May in the even semesters. The maximum marks for each theory and practical course
(including the project work and Viva Voce examination in the Fourth Semester) shall be 100 with the following
breakup.
(i) Theory Courses
Internal Assessment : 20 Marks
University Exams : 80 Marks
(ii) Practical courses

Internal Assessment : - -
University Exams : 100 Marks
M.Tech (VLSI DESIGN) i REGULATIONS 2010

5. Passing requirements
(i) A candidate who secures not less than 50% of total marks prescribed for the course (For all courses
including Theory, Practicals and Project work) with a minimum of 40 marks out of 80 in the University
Theory Examinations, shall be declared to have passed in the Examination.
(ii) If a candidate fails to secure a Pass in a particular course, it is mandatory that he/she shall reappear
for the examination in that course during the next semester when examination is conducted in that
course. However the Internal Assessment marks obtained by the candidate in the first attempt shall
be retained and considered valid for all subsequent attempts.
6. Eligibility for the Award of Degree
A student shall be declared to be eligible for the award of the M.E/M.Tech./M.Arch./M.Sc degree provided the
student has successfully completed the course requirements and has passed all the prescribed examinations in
all the 4 semesters within the maximum period specified in clause 2.
7. Award of Credits and Grades
All assessments of a course will be done on absolute marks basis. However, for the purpose of reporting the
performance of a candidate, Letter Grades will be awarded as per the range of total marks (out of 100) obtained
by the candidate as given below:
RANGE OF MARKS FOR GRADES
Range of Marks Grade Grade Points (GP)

90-100 A++ 10
80-89 A+ 9
70-79 B++ 8
60-69 B+ 7
50-59 C 6
00-49 F 0
ABSENT W 0
CUMULATIVE GRADE POINT AVERAGE CALCULATION

The CGPA calculation on a 10 scale basis is used to describe the overall performance of a student in
all courses from first semester to the last semester. F and W grades will be excluded for calculating GPA
and CGPA.
Σi C i GP i
CGPA =
Σ i Ci
where Ci - Credits for the subject
GP i - Grade Point for the subject
Σi - Sum of all subjects successfully cleared during all the semesters
M.Tech (VLSI DESIGN) ii REGULATIONS 2010

8. Classification of the Degree Awarded
1 A candidate who qualifies for the award of the Degree having passed the examination in all the
courses of all the semesters in his/her first appearance within a maximum period of 4 consecutive
semesters after commencement of study securing a CGPA not less than 9.0 shall be declared to
have passed the examination in First Class – Exemplary.
2. A candidate who qualifies for the award of the Degree having passed the examination in all the
courses of all the semesters in his/her first appearance within a maximum period of 4 consecutive
semesters after commencement of study, securing a CGPA not less than 7.5 shall be declared to
have passed the examination in First Class with Distinction.
3. A candidate who qualifies for the award of the Degree having passed the examination in all the
courses of all the semesters within a maximum period of 4 consecutive semesters after
commencement of study securing a CGPA not less than 6.0 shall be declared to have passed
the examination in First Class.
4 All other candidates who qualify for the award of the Degree having passed the examination in all
the courses of all the 4 semesters within a maximum period of 8 consecutive semesters after his/her
commencement of study securing a CGPA not less than 5.0 shall be declared to have passed
the examination in Second Class.
5 A candidate who is absent in semester examination in a course/project work after having registered
for the same, shall be considered to have appeared in that examination for the purpose of
classification of degree. For all the above mentioned classification of Degree, the break of study
during the programme, will be counted for the purpose of classification of degree.
6 A candidate can apply for revaluation of his/her semester examination answer paper in a theory
course, within 1 week from the declaration of results, on payment of a prescribed fee along with
prescribed application to the Controller of Examinations through the Head of Department. The
Controller of Examination will arrange for the revaluation and the result will be intimated to the
candidate concerned through the Head of the Department. Revaluation is not permitted for practical
courses and for project work.
Final Degree is awarded based on the following :
CGPA ≥ 9.0 - First Class - Exemplary
CGPA ≥ 7.50 < 9.0 - First Class with Distinction
CGPA ≥ 6.00 < 7.50 - First Class
CGPA ≥ 5.00 < 6.00 - Second Class
Minimum CGPA requirements for award of Degree is 5.0 CGPA.
9. Discipline
Every student is required to observe disciplined and decorous behaviour both inside and outside the University
and not to indulge in any activity which will tend to bring down the prestige of the University. If a student
indulges in malpractice in any of the University theory / practical examination, he/she shall be liable for punitive
action as prescribed by the University from time to time.
10. Revision of Regulations and Curriculum
The University may revise, amend or change the regulations, scheme of examinations and syllabi from time to
time, if found necessary.
M.Tech (VLSI DESIGN) iii REGULATIONS 2010

M.Tech – VLSI DESIGN

REGULATIONS 2010 – CURRICULUM
SEMESTER I
Sl.No. SUBJECT CODE SUBJECT TITLE L T P C Page No.
THEORY
1. SECX5016 Transforms & Probability for Electronics Engineering 3 1 0 4 1
2. SECX5017 Advanced Digital System Design 3 0 0 3 2
3. SECX5018 VLSI Design 3 0 0 3 3
4. SECX5019 MOS Device Modeling 3 0 0 3 4
5. SECX5020 VLSI Technology 3 0 0 3 5
PRACTICAL
6. SECX6503 EDA Tools Laboratory 0 0 4 2 12
Total Credits: 18
SEMESTER II
THEORY
1. SECX5021 Advanced Digital Signal And Image Processing 3 0 0 3 6
2. SECX5022 Analog and Mixed Signal Integrated Circuits 3 1 0 4 7
3. SECX5023 CAD for VLSI Circuits 3 0 0 3 8
4. Elective - I 3 0 0 3
5. Elective - II 3 0 0 3
PRACTICAL
6. SECX6504 VLSI Design Laboratory 0 0 4 2 13
Total Credits: 18
SEMESTER III
THEORY
1. SECX5024 VLSI Signal Processing 3 0 0 3 9
2. SECX5025 Low Power VLSI Design 3 1 0 4 10
3. SECX5026 Testing of VLSI Circuits 3 1 0 4 11
4. Elective - III 3 0 0 3
5. Elective - IV 3 0 0 3
PRACTICAL
6. SECX6505 Design Project Laboratory 0 0 4 2 13
Total Credits: 19
M.Tech (VLSI DESIGN) iv REGULATIONS 2010

SEMESTER IV
Sl.No. SUBJECT CODE SUBJECT TITLE L T P C

1. S82XPROJ Project Vivavoce 0 0 30 15
Total Credits: 15
Total Credits For the Course: 70
LIST OF ELECTIVE SUBJECTS

1. SECX5027 Advanced Programming in HDL 3 0 0 3 14
2. SECX5005 Embedded System Design 3 0 0 3 15
3. SECX5028 Semiconductor Devices and Simulation tools 3 0 0 3 16
4. SECX5084 Fuzzy logic & Neural Networks 3 0 0 3 17
5. SECX5029 ASIC Design 3 0 0 3 18
6. SECX5030 AMS Hardware Description And Verification Languages 3 0 0 3 19
7. SECX5031 Electromagnetic Interference & Compatibility 3 0 0 3 20
8. SECX5032 Digital Signal Processors Architectures and Applications 3 0 0 3 21
9. SECX5085 Bluetooth Technology 3 0 0 3 22
10. SECX5033 Design of Semiconductor Memories 3 0 0 3 23
11. SCSX5031 Cryptography & Network Security 3 0 0 3 24
12. SECX5034 VLSI For Wireless Communication 3 0 0 3 25
13. SECX5035 RF IC Design 3 0 0 3 26
14. SECX5036 Computer architecture and parallel processing 3 0 0 3 27
15. SECX5037 Mixed signal processing 3 0 0 3 28
16. SECX5038 High speed VLSI design 3 0 0 3 29
17. SECX5039 Basics of Nanotechnology 3 0 0 3 30
18. SECX5040 Nano Sensors and Applications 3 0 0 3 31
19. SECX5041 Digital Design With CPLD Application 3 0 0 3 32
20. SECX5042 Algorithms For VLSI Design Automation 3 0 0 3 33
21. SECX5043 High-Level Synthesis Of Digital Circuits 3 0 0 3 34
22. SECX5083 Programming In PERL 3 0 0 3 35
23. SECX5051 RF MEMS and its Applications 3 0 0 3 36
L - Lecture Hours; T - Tutorial Hours; P - Practical Hours; C - Credits
M.Tech (VLSI DESIGN) v REGULATIONS 2010

TRANSFORMS & PROBABILITY FOR L T P Credits Total Marks

SECX5016 ELECTRONICS ENGINEERING
3 1 0 4 100
(Common to VLSI, NanoTech, Embedded)
UNIT I ID TRANSFORMS 10 hrs.

Review of Fourier analysis - Analysis of different periodic & non periodic waveforms – Sampling Theorem -
DFS - DTFT - DFT - inverse DFT- properties - FFT – radix r algorithm – DIT FFT & DIF FFT - Convolution – review
of Z transform- Hilbert transform
UNIT II 2D TRANSFORMS 10 hrs.

Need for transform – 2D Orthogonal and Unitary transform and its properties – 2D DFT – Properties – FFT –
Statement , proof and properties of Separable transforms – Walsh , Hadamard , Haar , Discrete Sine , DCT , Slant,
SVD & KL transforms
UNIT III WAVELET TRANSFORMS 10 hrs.

Wavelet transforms - 1D & 2D Wavelet transform - Time and frequency decompositions - STFT - Continues
and discrete - CWT, DWT , Harr wavelet and Shannon wavelet– Fast Wavelet transform – Wavelet Packets.
UNIT IV PROBABILITY & RANDOM VARIABLES 10 hrs.

Probability concepts- Random variable - moment generating function - discrete types, continues types -2D variable
random variables – marginal , conditional , joint probability distribution - Binomial, Poisson , uniform , normal and
Exponential distributions
UNIT V RANDOM PROCESS 10 hrs.

Notion of stochastic processes , Auto Correlation – Cross Correlation – WSS – Ergodicity - power spectral
density function – properties - Discrete random process – expectations – variance , co variance – scalar product –
energy of discrete signals – parseval’s theorem – Wiener Khintchine relation –- Discrete random signal processing by
linear systems - response of linear discrete systems to white noise - Two dimensional random variables - transformation
of random variables - regression system - simulation of white noise – low pass filtering of white noise.
TEXT BOOK:
1. Ronald W. Schafer, Alan V. Oppenheim, Discrete Time Signal Processing", Prentice Hall 3rd Edition, 2009.
REFERENCE BOOKS:
1. Gonzalez, Woods and Eddins, “Digital Image Processin” Prentice Hall, 3rd Edition, 2008.
2. Raghuveer M. Rao, Ajith S. Bopardikar, “Wavelet Transform: Introduction to theory & Applications; Prentice Hall 1st Edition, 1998.
3. Yaglon.A.M “Probability and information”, Springer Publication- 1983
4. W. John Wodds “Probability and random process with application to signal processes” Prentice Hall-2001
5. Atkinson.F.V “Discrete and continuous boundary problems”, Academic Press Inc -volume 8 -1998
UNIVERSITY EXAM QUESTION PAPER PATTERN

Max. Marks: 80 Exam Duration : 3 hrs.
Part A: 6 Questions of 5 marks each – No choice 30 marks
Part B: 5 Questions from each of the five units of internal choice, each carrying 10 marks 50 marks
(Distribution may be 40% Theory & 60% Problem)
M.Tech (VLSI DESIGN) 1 REGULATIONS 2010

ADVANCED DIGITAL SYSTEM DESIGN L T P Credits Total Marks

SECX5017
(Common to VLSI, Embedded, Appl. Elec.) 3 0 0 3 100
UNIT I SEQUENTIAL LOGIC CIRCUITS 10 hrs.

Mealy machine, Moore machine, Trivial/Reversible/Isomorphic sequential machines, State diagrams, State table
minimization, Incompletely specified sequential machines, State assignments, Design of synchronous and asynchronous
sequential logic circuits working in fundamental and pulse mode.
UNIT II SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 10 hrs.

Analysis of clocked synchronous sequential Networks (CSSN), Modeling of CSSN-State table assignment and
reduction – Design of CSSN-Design of iterative circuits- ASM Chart- ASM Realization.
UNIT III ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 10 hrs.

Analysis of Asynchronous sequential Circuits (ASC)-Flow table reduction -Races in ASC State assignment-
Problem and the Transition table-Design of ASC-Static and Dynamic hazards-Data synchronizers-Designing of Vending
machine controller-Mixed operating mode Asynchronous circuits.
UNIT IV PROGRAMMABLE LOGIC DEVICES 10 hrs.

Basic concepts, programming technologies, Programmable Logic Element(PLE),Programmable Logic
Array(PLA),Programmable Array Logic(PAL),Structure of standard PLD’s, Complex PLD’s(CPLD)-System design using
PLD’s-Design of combinational and sequential circuits using PLD’s, Programmable PAL device using PALASM, Design
of state machine using Algorithmic State Machines(ASM) chart as design tool.
UNIT V STUDY OF FPGA AND XILINX 10 hrs.

Introduction to Field Programmable Gate Arrays-Types of FPGA –Xilinx XC3000 series, Logic Cell
Array(LCA),Configurable Logic Blocks(CLB),Input/Output Block(IOB)-Programmable Interconnect Point(PIP),Introduction
to ACT2 family and Xilinx XC4000 families, Design examples.
TEXT BOOK:
1. Donald G.Givone ”Digital Principles and Design”, Tata Mc graw hill 2002.
REFERENCE BOOKS:
1. John M Yarbrough “Digital Logic Applications and Design”, Thomson Learning 2001
2. Nripendra N Biswas “Logic Design Theory”, Prentice Hall of India, 2001
3. Charles H Roth Jr “Fundamentals of Logic Design”, Thomson Learing 2004


VLSI DESIGN L T P Credits Total Marks

SECX5018
(Common to VLSI, Embedded) 3 0 0 3 100
UNIT I 10 hrs.
Review of MOS electrical properties – Expression for threshold voltage and drain current - Energy band structure
and band bending in the different region of operation - Secondary effects of MOSFET-review of CMOS and bipolar
technologies.
UNIT II 10 hrs.
Basic inverter - Inverter Device sizing - Enhancement load and Depletion load inverters – CMOS inverter –
CMOS inverter logic levels – Inverter device sizing – combinational logic implementation using NMOS and CMOS
inverters - NMOS and CMOS design rules – stick diagram and layout.
UNIT III 10 hrs.

Steering logic design – programmable logic arrays – Folded PLA‘s – structured gate arrays – Dynamic MOS
storage circuits – performance of Dynamic logic – clocked CMOS logic
UNIT IV 10 hrs.
CMOS static flip flops - dynamic sequential circuits – CMOS Logic – NORA CMOS - True single phase clocked
logic – Capacitors and performance in CMOS – driving large capacitance - Resistance and performance
UNIT V 10 hrs.
Design of addres: Static, Dynamic, Manchester carry chain, Carry bypass adder, CSA, Carry look ahead adder
–Multipliers : Baugh wooley, Booth Multiplier – Barrel shifter – NOR and NAND ROMs – operations in CMOS SRAM
– Sence amplifiers
TEXT BOOK:
1. Jan M . Rabaey “Digital Integrated Circuits”, Pearson Education Ltd-2003
REFERENCE BOOKS:
1. Randall L, Geigar and Allence “VLSI Design for Analog and Digital circuits”, McGraw Hill Co-1990
2. Fabricius E “Introduction to VLSI Design”, McGraw Hill 1990.
3. Douglas A. Pucknell “Basic VLSI Design”, Prentice Hall of India, 1994
4. Franco Maloberti “Analog design for CMOS VLSI systems”, Kluwer Academic Publishers-2001
5. Abdellatif Bellaouar “Low-Power Digital VLSI Design: Circuits and Systems”, Kluwer Academic Publishers-2000

Part A: 6 Questions of 5 marks each – No choice. 30 marks

MOS DEVICE MODELING L T P Credits Total Marks

SECX5019
(Common to VLSI, NanoTech) 3 0 0 3 100
UNIT I 10 hrs.
Overview of MOS: Characteristics of a MOS transistor-Surface properties of Silicon : Energy band diagram for
the ideal case-Calculation of the threshold voltage(vt) – Non ideal effects- CV plots: importance – Ideal case – High
frequency CV plots – low Frequency CV plots – Equations to CV plots – Deep depletion – Deviations from the Ideal
CV plots - interface traps, Effect of AC signal on the interface states – Techniques to measure Cit, computation of
Cs and Ps – Limitation in high frequency techniques – Comparison of measurements at high and low frequency
techniques.
UNIT II 10 hrs.
Sources of oxide trapped charge – radiation created oxide trapped charge – Experimental results – How oxide
Trapped charge can be annealed out – models to explain the technique – Shifts in threshold voltage in P-channel
and N-channel MOSFET – Disadvantages – Shifts at dynamic bias – radiation hardening – Other alternatives
dielectrics – gate metallization
UNIT III 10 hrs.

MOSFET- Parameters of importance – Qualitative analysis of MOSFET – Mathematical model of IV
characteristics – SPICE level1,level2, level3 models – Change in velocity with electric field – Expression for Id in the
sub threshold region of operation.
UNIT IV 10 hrs.
Non uniform doping and effect on threshold voltage – short channel effect – Narrow width effect – Small geometry
effects – Shrink and Scaling. Small signal analysis of MOSFET – Derivation of the different parameters associated
with the small signal model – Cutoff frequency – Hot carrier effects – 1988 model – Monte Carlo analysis
UNIT V 10 hrs.
MOSFET devices – HMOS, DMOS, DIMOS, UMOS, VMOS, Sy MOSFET, SOS, Si MOX, BESOI, SEU, FAMOS,
MCOS – Comparison with the conventional CMOS. MOS Device application : Depletion mode device – MOSFET
connected as load devices - MOSFET as resistors, Static protection.
TEXT BOOK:
1. Dewitt G. Ong “Modern MOS technology: processes, Devices and Design”, Mcgraw Hill, 1984.
REFERENCE BOOKS:
1. Yannis Tsividis “Operation and Modeling of MOS Transistors”, Mcgraw Hill, 1999
2. Shoji.M “CMOS Digital circuit Technology”, Prentice Hall, 1988.
3. Sorab K.Ghandhi “Semiconductor device principle”, John wiley and sons, 1983.
4. Amar Mukerjee. “Introduction to Nmos and Cmos VLSI Systems design”, Prentice Hall, 1986


VLSI TECHNOLOGY L T P Credits Total Marks

SECX5020
UNIT I CRYSTAL GROWTH, WAFER PREPARATION, EPITARY AND OXIDATION. 10 hrs.

Electronic grade silicon – Basic steps in IC fabrication-crystal plane and orientation – Defects in the lattice
–Czochralski crystal growing – silicon shaping – Processing consideration – Vapour phase epitaxy –Liquid phase
epitaxy-selective epitaxy- Molecular beam epitaxy - Epitaxial Evaluation – Growth mechanism and kinetics – Thin
oxides – Oxidation Techniques and systems – Oxide properties – Redistribution of dopants at interface – Oxidation
of polysilicon – Oxidation induced effects.
UNIT II LITHOGRAPHY AND RELATIVE PLASMA ETCHING 10 hrs.

Mask Making – Optical lithography – Electron lithography – X-ray lithography – Ion lithography – Plasma properties
– Feature size control and Anisotropie Etch mechanism – Lift off Techniques – Plasma reactor – Fl2 &Cl2 based
etching – Relative plasma etching Techniques and Equipments.
UNIT III DEPOSITION, DIFFUSION , ION IMPLANTATION AND METALIZATION 10 hrs.

Deposition process – polisilicon - plasma assisted deposition – models of diffusion in solids – Fick’s one
dimensional diffusion equation – Atomic diffusion mechanism – measurement techniques – Range theory – Carrier
recovery due to annealing - Implantation equipment – Annealing Shalloe junction – high energy implantation – Physical
vapour deposition – patterning.
UNIT IV METALLIZATION 10 hrs.

Metallization applications – metallization choices – Patterning – Metallization problems – New role of metallization-
metallization systems – sputtering – problems associated with Al – Cu interconnect – Comparison of RC delay of
Polysilicon, Al.
UNIT V ANALYTICAL , ASSEMBLY TECHNIQUES & PACKAGING OF VLSI DEVICES 10 hrs.

Analytical beams – Beams specimen interaction – Chemical methods – package types – baking design
considerations – VLSI assembly technology – Package Fabrication Technology.
TEXT BOOK:
1. S.M.Sze “VLSI Technology“, Tata Mcgraw Hill, 2003.
REFERENCES BOOKS:
1. Sorab. K. Gandhi “VLSI Fabrication and Principles“, John wiley and sons, 1983.
2. Amar Mukherjee “Introduction to NMOS & CMOS VLSI system Design“, Prentice Hall, 1986.
3. Mccanny and J.C.White “VLSI Technology and design”, Academic Press, 1987.
4. Dasgupta “VLSI Technology“, Pearson Education Pvt Ltd 2001


ADVANCED DIGITAL SIGNAL AND IMAGE L T P Credits Total Marks

SECX5021 PROCESSING
3 0 0 3 100
(Common to VLSI, NanoTech, Embedded)
UNIT I SPECTRUM ESTIMATION & PREDICTION 10 hrs.

Review of FIR , IIR, filters-Signal analysis using Fourier Transform - Periodogram- sample auto correlation- sum
decomposition theorem- spectral factorization theorem- non parametric method- correlation method- co variance
estimator- unbiased, consistant estimator- periodogram estimator- Bartlett spectrum estimation- Welch estimation- model
based approach- AR- MA- ARMA signal modeling- parameter estimation using yule walker method- least mean square
error criterion- Wiener filter-linear prediction- forward backward prediction- levinson recursion algorithm for solving toeplitz
system of equations
UNIT II ADAPTIVE FILTERS 10 hrs.

FIR adaptive filter- Newton steepest descent method – widrow hoff LMS adaptive algorithm- adaptive channel
equalization- adaptive echo cancellor- adaptive noise cancellasion- RLS adaptive filter- simplified IIR LMS adaptive filter.
UNIT III MULTI RATE SIGNAL PROCESSING 10 hrs.

Mathematical description of change of sampling rate- interpolation- decimation- continuous time model- direct
digtal domain approach- decimation by an integer factor- interpolation by an integer factor- single and multi stage
realization-poly phase realision- filteer bank implementation- application to sub band coding .
UNIT IV IMAGE ENHANCEMENT AND RESTORATION 10 hrs.

Elements of digital image processing systems- elements of visual perception- structure of human eye-
Monochrome vision model- image enhancement and restoration-Spatial domain method- histogram processing- spatial
filtering- edge crispening- interpolation- homomorphic filtering – degradation model- diaginalization of Circulant and
Block Circulant Matrices-Algebraic Approach to restoration- constrained and unconstrained restoration- inverse filtering
and wiener filter-Image morphology.
UNIT V IMAGE DATA COMPRESSION 10 hrs.

Fundamentals of coding- image compression model- fundamental coding theorem shannon’s coding, Huffman
coding- pixel coding- predictive techniques- lossy and loseless predictive coding- variable length coding, bit plain coding-
transform coding, zonal and threshold coding, image compression standard- CCITT and JPEG standards.
TEXT BOOK:
1. Monson H.Hayes “Statistical digtal signal processing and modeling”, John Wiley & Sons, 2002.
REFERENCE BOOKS:
1. John G Proakis “Digtal signal processing”, Pearson Prentice Hall, 2007.
2. Simon Haykin “Adaptive filter theory”, Prentice Hall, 2002.
3. Anil K Jain “Fundamental of Digtal image processing”, Prentice Hall, 1989.
4. R.C. Gonzalez “Digtal image processing”, Pearson Prentice Hall, 2008.

Part B: 5 Questions from each of the five units of internal choice, each carrying 10 marks. 50 marks

ANALOG AND MIXED SIGNAL INTEGRATED L T P Credits Total Marks

SECX5022 CIRCUITS
3 1 0 4 100
(Common to VLSI, NanoTech)
UNIT I SINGLE STAGE AMPLIFIERS AND CURRENT MIRRORS 10 hrs.

Basics of CMOS – Analog model of MOSFET – low and high frequency models – Simple CMOS current mirror
- source degenerated current mirrors – high output impedance current mirrors –All NMOS Operational Amplifier Design–
Bipolar current mirrors – Bipolar gain stages – gain enhancement techniques – Frequency response.
UNIT II OP AMP DESIGN AND ADVANCED CURRENT MIRRORS 10 hrs.

Two stage CMOS op amp – op amp as a comparator – Charge injection errors, Latched Comparators – Advanced
current mirrors – folded cascade and current mirror op amp – Linear settling time revisited, fully differential op amp
- Analysis of Differential Amplifier with active load, supply and temperature independent biasing techniques.
UNIT III VOLTAGE REFERENCE, SAMPLE AND HOLD CIRCUITS 10 hrs.

Sample and hold circuits – MOS sample and hold basics – examples of CMOS S/H circuits – Bipolar and
BiCMOS S/H circuits – Bandgap reference basics – translinear gain cell – Translinear multiplier- Basics of OTA
Amplifiers Design.
UNIT IV DATA CONVERTERS AND NEURAL INFORMATION PROCESSING 10 hrs.

High speed A/D and D/A converters – High resolution converters – Sigma delta A/D converter – Interpolative
Modulators - Testing of converters Biologically Inspired Neural Networks – Low Power Neural Networks – Analog cell
Layout – Mixed Analog – Digital Layout.
UNIT V SWITCHED CAPACITOR CIRCUITS AND PLL 10 hrs.

Basic building blocks of switched capacitor circuits – Basic operation and Analysis –Switched capacitor amplifier
– Switched capacitor integrators – Z Domain Model Representation of Switched Capacitor Circuits – Switched Capacitor
filter Design – Charge injection. Basic loop architecture of PLL – Linearized PLL model – Phase detectors – Sequential
phase detector – PLL with charge pump phase comparator – VCO.
TEXT BOOKS:
1. David A Johns and Ken Martin “Analog Integrated circuit design”, John wiley & Sons,2004.
2. Gray & Mayer “Analysis and Design of Analog Integrated Circuits”, John wiley and Sons, 4th edition, 2005.
REFERENCE BOOKS:
1. Behzad Razavi “Design of Analog CMOS Integrated circuits”, Tata Mcgraw Hill India Pvt.Ltd, 2008.
2. Franco Maloberti “Analog Design for CMOS VLSI Systems”, Kluwer Academic Publisher, 2001.
3. Roger T.Howe and Charles G.Sodini “ Micro Electronics an Integrated Approach”, Pearson Education Pvt Ltd 2004.
4. Roubik Gregorian “Analog MOS Integrated Circuits for Signal Processing”, John wiley and sons, 2004
5. Rudy Van de Plassche “CMOS Integrated A/D and D/A converters”, Kluwer Academic Publisher, 2003.


L T P Credits Total Marks

SECX5023 CAD FOR VLSI CIRCUITS
3 0 0 3 100
UNIT I INTRODUCTION 10 hrs.

Basic terminologies in data structures – Complexity issues anNP – hardness. Basic data structures – Atomic
operations, Linked list of blocks, Bin-based method, Corner Stitching, Layout Specification languages. Clock routing,
clocking schemes, Design considerations – problem formulation – clock routing algorithm – power and ground routing.
UNIT II LOGIC OPTIMIZATION 10 hrs.

Logic level synthesis and optimization, two level combinational logic optimization Introduction – Logic optimization
principles- operations on two level logic covers – Algorithms for logic minimization – Symbolic minimization and encoding
problems – Minimization of Boolean relations– Models and transformations for combinational networks – The algebraic
model – The Boolean model – Synthesis of networks – Algorithms for delay evaluation and optimization .
UNIT III OVERVIEW ON TOOLS FOR LAYOUT 10 hrs.

Partitioning : Objectives – Kernighan Lin algorithm – Pseudo code – Fiduccia Matheyses Heuristic – Ladder
network Partitioning – Simulated annealing, Wirelength estimator : Steiner Tree – Spanning tree algorithm.
UNIT IV FLOOR PLANNING AND PLACEMENT TECHNIQUES 10 hrs.

Constraints involved – including rotation – changing the aspect ratio. Force Directed placement technique –
Pseudo code – Min cut placement – Placement by the generic algorithm – Placement based on steepest descent –
GASP – Linear programming method – Branch and Bound algorithm – Routing algorithms. Global and Detailed routing
– Linear searching – Channel intersection graph - Maze routing algorithm – Greedy channel router.
UNIT V VERIFICATION AND CIRCUIT EXTRACTION 10 hrs.

Ordered binary decision diagram : Operation, synthesis OBDDs. Paradigmatic application of OBDDs. Optimization
of variable ordering Compaction : Problem formulation, Classification, One dimensional compaction, Hierarchical
Compaction, Recent trends – Applications of VLSI circuits.
TEXT BOOK:
1. Sherwani “Algorithms for VLSI Physical Design Automation”, Kluwer Academic Publisher, 1995.
REFERENCE BOOKS:
1. Soha Hassoun and Tsutomu Sasao “Logic Synthesis and verification”, Kluwer Academic Publisher, 2003.
2. Giovanni De Michele “Synthesis and optimization of digital circuits”, Mc Graw Hill, 1994.
3. Sherwani “An Introduction to Physical VLSI Design”, Prentice Hall of India, 2004.

Part B: 5 Questions from each of the five units of internal choice, each carrying 10 marks each. 50 marks

VLSI SIGNAL PROCESSING L T P Credits Total Marks

SECX5024
UNIT I 10 hrs.
Introduction to DSP systems –Typical DSP algorithms, DSP application demands – representation of DSP
algorithms – Iteration bound – data flow graph representation, loop bound and iteration bound, Algorithms for computing
Iteration bound, Iteration bound of multi rate data flow graphs- pipelining and parallel processing – pipelining of FIR
digital filter , parallel processing, pipelining and parallel processing for low power.
UNIT II 10 hrs.
Retiming – definition and properties, solving systems of inequalities, Retiming techniques – Unfolding –Properties
and algorithm for unfolding, critical path and applications of unfolding – folding transformation, register minimization
technique, register minimization in folded architectures - folding of multi rate systems
UNIT III 10 hrs.

Systolic architecture design – methodology, FIR systolic array, selection of scheduling vector , matrix to matrix
multiplication , 2D systolic array design, systolic design for space representation containing delays – fast convolution
algorithms – Redundant arithmetic - carry free radix 2 addition and subtraction - Radix 2 hybrid redundant multiplication
architectures - data format conversion - Redundant to non-redundant converter -Numerical strength reduction.
UNIT IV 10 hrs.
Bit level arithmetic structures- parallel multipliers - interleaved floor plan and bit plan based digital filters - Bit
serial multipliers. Bit serial filter design and implementation - Canonic signed digit arithmetic - Distributed arithmetic-
Synchronous pipelining and clocking styles - clock skew and clock distribution in bit level pipelined VLSI designs -
Wave pipelining - constraint space diagram and degree of wave pipelining - Implementation of wave-pipelined systems
- Asynchronous pipelining – Schur algorithm .
UNIT V 10 hrs.
Design of VLSI Architectures for Digital Signal Processing- Architectural Design at Register Transfer Level -
Design of Datapath elements Control structures Testable and self-reconfigurable fault-tolerant structures -
Speed-Area-Power tradeoff Issues related to mixed signal design and SoC - CORDIC algorithm and multiplier less
architectures - Scaling versus power consumption.
TEXT BOOK:
1. Keshab K.Parhi “VLSI Digital Signal Processing systems”, John wiley & Sons, 1999.
REFERENCE BOOKS:
1. Mohammed Isamail and Terri fiez “Analog VLSI Signal and information processing“, Mc Graw Hill,New Delhi, 1994.
2. S.Y.Kung , H.J.White House “VLSI and Modern Signal Processing“, Prentice Hall, 1985.
3. Jose E.France, Yannis Tsvidis “ Design of Analog – Digital VLSI Circutis for Telecommunication and Signal Processing”,
Prentice Hall 1994.


LOW POWER VLSI DESIGN L T P Credits Total Marks

SECX5025
UNIT I 10 hrs.
Introduction- Need for Low power VLSI design– Charging and Discharging Capacitance- Short circuit current in
CMOS– CMOS leakage current- Static current- Principles of Low power design- Low power figure of Merits.
UNIT II 10 hrs.
Simulation power analysis- SPICE circuit analysis- Discrete Transistor Modeling and analysis - Gate Level Logic
simulation - Architecture level analysis - Data Correlation analysis in DSP systems - Monte Carlo Simulation - Random
Logic signal- Probability Power analysis techniques- Signal entropy.
UNIT III 10 hrs.

Transistor and gate sizing-Network Restructuring and Reorganization- special latches and Flip flops-Low power
digital cell library - Gate Reorganization- Signal Gating –Logic Encoding -State Machine encoding- Precomputation
Logic.
UNIT IV 10 hrs.
Special Techniques- Power reduction in clock networks- CMOS floating node -Low power Bus -Delay Balancing-
Low power techniques for SRAM- Architecture and system- Power and performance management -Switching activity
reduction -Parallel Architecture –Flow graph transformation.
UNIT V 10 hrs.
Advanced techniques- Adiabatic Computation- Pass transistor Logic synthesis -Asynchronous circuits - Software
Design for Low power-Sources of software power dissipation- Software power optimization.
TEXT BOOK:
1. Gary Yeap "Practical Low Power Digital VLSI design", Kluwer Academic Publishers - 1997 Edition
REFERENCE BOOKS:
1. Sharat Prasad and Koushik Roy "Low power CMOS VLSI Circuit design”, John Wiley Publications", 2000 Edition
2. Kiat Seng Yeo &Kaushik Roy “Low voltage, Low power VLSI subsystems”, McGraw-Hill 2009.
3. Meloberti Franco “Analog design for CMOS VLSI systems“, Kluwer Academic Publishers-2001
4. Abdellatif Bellaouar “Low-Power Digital VLSI Design: Circuits and Systems”, kluwer Academic Publishers - 1995
5. Saraju P. Mohanty- Nagarajan Ranganathan, Elias Kougianos, Priyardarsan Patra “Low-Power High-Level Synthesis for
Nanoscale CMOS Circuits”, Springer-2008.



SECX5026 TESTING OF VLSI CIRCUITS
3 1 0 4 100

Validation and testing of manufactured circuits – Test procedures – Issues in design for Testability - Observability
and Controllability Adhoc Testing – Scan based Testing – Boundary scan Design – Design for Testability.
UNIT II FAILURES AND FAULTS 10 hrs.

Modeling of faults - Stuck at faults- Fault diagnosis of Digital circuits. Test generation techniques for combinational
circuits – Boolean difference – D- Algorithm – Detection of multiple faults in combinational circuits.
UNIT III TESTING OF SEQUENTIAL CIRCUITS 10 hrs.

Test generation for sequential circuits – State table verification - functional fault model – Equivalence Checking
- Level sensitive scan design – Clocked Hazard free latches – Arithmetic and Reed Muller Coefficients - Software
and Hardware Fault Tolerance.
UNIT IV BUILT-IN SELF-TEST (BIST) 10 hrs.

Test pattern generation for built in self test. Exhaustive pattern generation and deterministic testing - Output
response Analysis – Transition count syndrome checking Signature Analysis – Circular BIST.
UNIT V TESTABLE MEMORY DESIGN 10 hrs.

RAM fault model – Test algorithm for RAMs. GALPAT – March Test – Detection of pattern sensitive faults-
built in self test techniques for RAM chips. Self testable SRAM architecture. Test generation and BIST for Embedded
RAMs
Case study:- Online testing approach for very deep submicron ICs.
TEXT BOOK:
1. Michael L.Bushnell & Vishwani. D.Aggarwal Kulwer “Essentials of Electronic testing for digital, memory and mixed signal
VLSI circuit”, Kluwer academic Publishers 2000.
REFERENCE BOOKS:
1. Parag.K.lala “Digital circuit Testing and Testability”, Academic press-2007
2. Alfred L.Crouch “Design for test for Digital ICs and Embedded core systems“, Prentice Hall, 1999.
3. Giovanni De Michele “Synthesis and optimization of digital circuits”, Mcgraw Hill Higher Education, 1994.
4. Meloberti Franco "Analog design for CMOS VLSI systems", Kluwer Academic Publishers-2001


EDA TOOLS LABORATORY L T P Credits Total Marks

SECX6503
Analog Experiments
I. To acquire the knowledge of designing and simulation of basic analog circuits using Pspice
1. Analog amplifiers.
2. Oscillators
3. BJT biasing circuits
4. FET characteristics
5. Multivibrators
6. RLC circuits
7. Passive filters
8. Attenuators
9. Electrical circuit theorems
1. Superposition Theorem
2. Maximum power transfer theorem
3. Norton’s Theorem
4. Reciprocity Theorem
10. Waveform Generation Circuits
1. Schmitt Trigger
2. Square wave Generator
3. Switch mode power supply (SMPS)
4. Schmitt Trigger
11. Diode Experiments
12. Modulation Circuits
13. Op- amps
Digital Experiments
14. Combinational Circuits
15. Sequential Circuits
16. Inverters with various types of load
17. Scaling of MOS devices
II. Preparation of Layouts using MAGIC.

For all experiments shown above , the VLSI layout would be prepared by using the tool MAGIC.


SECX6504 VLSI DESIGN LABORATORY
0 0 4 2 100
LIST OF EXPERIMENTS
I. Verilog / VHDL Simulation, Synthesis & FGPA implementation of

1. 4 bit Adders & Subtractors (CLA, CSA, CMA, Parallel adders)
2. Design of FF (SR, D, T, JK, Master Slave with delays)
3. Design of code converters & Comparator
4. Design of Encoder, Decoder, Multiplexer, and De multiplexer
5. Design of registers using latches and flip-flops
6. Design of 8 bit Shift registers
7. Design of Asynchronous & Synchronous Counters
8. Modeling of Moore & Mealy FSM
9. Static & Rolling Display
10. Frequency Multipliers & Dividers
11. Design of ALU
12. Barrel Shifters
13. Key Scan
14. 4 bit Microprocessor
15. RISC CPU
16. Traffic light controller
17. Design of memories
18. Design of MAC unit
19. Design of Sorting Circuit
20. Design of FSM

SECX6505 DESIGN PROJECT LABORATORY
0 0 4 2 100
LIST OF EXPERIMENTS
To get a basic knowledge about the FPGA and ASIC flow

1. Layout Preparation for basic gates, adders, MUX and Flip flops
2. Layout Preparation for the combinational circuits using MUX
3. Layout Preparation for sequential circuits using Flip flops (Counters & registers)
4. Architecture development and layout preparation for Sine Wave generation
5. FPGA implementation and layout preparation for
a. Two stage Op Amp. b. Voltage controlled Oscillator
c. A/D and D/A converters d. 8 bit Microprocessor
e. Traffic light Controller f. Peripheral Devices
g. Low noise Amplifier h. Filter Design


SECX5027 ADVANCED PROGRAMMING IN HDL
3 0 0 3 100
UNIT I BASIC CONCEPTS IN VHDL 10 hrs.

Digital system design process - Hardware simulation – Introduction to VHDL - Language elements of VHDL –
Data objects – Data types – Operators – Variable assignment – Concurrent and sequential assignments.
UNIT II MODELING AND FEATURES IN VHDL 10 hrs.

Data flow modeling – Structural modeling – Behavioral modeling - Modeling a test bench –Generics and
configurations- Sub programs - Hardware modeling examples : Moore FSM, Mealy FSM.
UNIT III VERILOG HDL 10 hrs.

Basic concepts – Module – Delays - Language elements – Compiler directives, value set, data types, Parameters
– Expressions - Operands & operators - Gate level modeling –User defined Primitives – Combination UDP, Sequential
UDP.
UNIT IV MODELING AND FEATURES IN VERILOG HDL 10 hrs.

Data flow modeling – Structural modeling - Behavioral modeling – tasks and functions – System task and
functions – verification – Modeling a test bench - timing and delays – Switching level modeling.
UNIT V SYSTEM VERILOG 10 hrs.

Introduction to system verilog - Data types, Arrays, operators & Expressions - procedural & control flow statements
- process, tasks & functions - Random constraints - Interprocess synchronization and communication - clocking blocks
& program blocks - Interfaces & Mod ports
TEXT BOOKS:
1. J.Bhasker “VHDL Primer “, Prentice Hall, 1999
2. J.Bhasker “Verilog HDL”, Prentice Hall, 2000
REFERENCE BOOKS:
1. Douglas L. Perry "VHDL", McGraw Hill, 2002.
2. Stphen Brown "Foundamental of Digital logic with VHDL Design", Tata McGraw Hill, 2008.
3. Stphen Brown "Foundamental of Digital logic with Verilog Design", Tata McGraw Hill, 2008.
4. Simon Davidmann & Stuart Sutherland “System Verilog For Design”, Springs Science Business Media, 2006.


EMBEDDED SYSTEM DESIGN L T P Credits Total Marks

SECX5005 (Common to VLSI, Embedded, E&C, Power,
3 0 0 3 100
Appl. Elec.)

Embedded system- characteristics of embedded system- categories of embedded system- requirements of
embedded systems- challenges and design issues of embedded system- trends in embedded system- system
integration- hardware and software partition- applications of embedded system- control system and industrial automation-
biomedical-data communication system-network information appliances- IVR systems- GPS systems.
UNIT II DEVELOPMENT OF SOFTWARE ARCHITECTURE 10 hrs.

Development of software architecture – simple round robin architecture- design and implementation of digital
multimeter- round robin with interrupt architecture- implementation of communication bridge- function queue scheduling
architecture- RTOS architectur.
UNIT III HARDWARE ARCHITECTURE 10 hrs.

Hardware architecture- block schematic of a typical hardware architecture- CPU-memeory-I/O Devices- design
with microprocesors development-ADC- DAC interfacing LED/LCD interfacing. Case study of processor- 16 bit and 32
bit processor-DSP processor.
UNIT IV EMBEDDED SYSTEM PLATFORM AND DEVELOPMENT TOOLS 10 hrs.

Inter process communication- UART-IEEE 1394-IRDA-USB-PCI development tools- EPROM ERASER-signature
validator- accelerated design for video accelerator.
UNIT V OVERVIEW OF DESIGN TECHNOLOGIES 10 hrs.

Design methodologies and tools- designing hardware and software components- system analysis and architecture
design- system integration- structural and behavioral description smart cards.
TEXT BOOK:
1. Wayne wolf "Computers as components", morgan Kaufmann publishers, 2nd Edition, 2008.
REFERENCE BOOKS:
1. Jean.J. Labrosse “Embedded system building blocks”, CMB books, 2nd Edition, 1999.
2. Arnold Berger “Embedded system design”, CMB books, 1st Edition, 1999.
3. Narayan and Gong “Specifications and design of Embedded systems”, pearson education, 2nd Edition, 1999.

Part A: 6 Questions of 5 marks each – No choice. 30 marks

SEMICONDUCTOR DEVICES AND SIMULATION L T P Credits Total Marks

SECX5028
TOOLS 3 0 0 3 100
UNIT I IMPORTANT PARAMETERS GOVERNING THE HIGH SPEED PERFORMANCE OF DEVICES AND CIRCUITS
10 hrs.
Transit time of charge carriers, junction capacitances, ON-resistances and their dependence on the device geometry and
size, carrier mobility, doping concentration and temperature. Contact resistance and interconnection/interlayer capacitances in the
Integrated Electronics Circuits.
Materials for high speed devices and circuits : Merits of III –V binary and ternary compound semiconductors (GaAs, InP, InGaAs,
AlGaAs ETC.), silicon-germanium alloys and silicon carbide for high speed devices, as compared to silicon based devices. Brief outline
of the crystal structure, dopants and electrical properties such as carrier mobility, velocity versus electric field characteristics of these
materials. Material and device process technique with these III-V and IV – IV semiconductors.
UNIT II METAL SEMICONDUCTOR CONTACTS AND METAL INSULATOR SEMICONDUCTOR AND MOS DEVICES
10 hrs.
Native oxides of Compound semiconductors for MOS devices and the interface state density related issues. Metal
semiconductor contacts, Schottky barrier diode. Thermionic Emission model for current transport and current-voltage (I-V)
characteristics. Effect of interface states and interfacial thin electric layer on the Schottky barrier height and the I-V characteristics.
Metal semiconductor Field Effect Transistors (MESFETs): Pinch off voltage and threshold voltage of MESFETs. D.C.
characteristics and analysis of drain current. Velocity overshoot effects and the related advantages of GaAs, InP and GaN based
devices for high speed operation. Sub threshold characteristics, short channel effects and the performance of scaled down devices.
UNIT III HIGH ELECTRON MOBILITY TRANSISTORS (HEMT) 10 hrs.
Hetero-junction devices. The generic Modulation Doped FET(MODFET) structure for high electron mobility realization.
Principle of operation and the unique features of HEMT. InGaAs/InP HEMT structures.
Hetero junction Bipolar transistors (HBTs): Principle of operation and the benefits of hetero junction BJT for high speed
applications. GaAs and InP based HBT device structure and the surface passivation for stable high gain high frequency performance.
SiGe HBTs and the concept of strained layer devices.
UNIT IV INTRODUCTION TO MATLAB 10 hrs.
Menus and the toolbar , Computing with Matlab ,Script files and the Editor Debugger ,. Matlab Help System Matlab as
{best} calculator , Standard Matlab windows, Operations with variables a) Namingb) Checking existence c) Clearing d) Operations
.Relational and logical operators – Control statements IF-END, IF-ELSE-END, ELSE IF- SWITCH CASE – FOR Loop –While
loop- Debugging-Miscellaneous MAT lab functions and variables.
UNIT V ARRAYS, FUNCTIONS & FILES AND PLOTTING 10 hrs.
Columns and rows: creation and indexing , Size & length , Multiplication, division, power , Operations Writing script files:
Logical variables and operators, Flow control,Loop operators, Writing functions: Input/output arguments, Function visibility, path.
Example: Matlab startup. Basic 2D plots, XY- plotting functions , Subplots and Overlay plots , Special Plot types , Interactive
plotting , Function Discovery , Regression, 3-D plots .
TEXT BOOKS:
1. S. M. Sze and K. K. Ng “Physics of Semiconductor Devices”, John Wiley and Sons, 2007.
2. W. Liu "Fundamentals of III-V Devices: HBTs, MESFETs, and HFETs/HEMTs", John Wiley and Sons, 1999.
3. William J.Palm “Introduction to MATLAB 6.0 for Engineers” Mc Graw Hill, 2001.
REFERENCE BOOKS:
1. S. M. Sze, “High Speed Semiconductor Devices”, John Wiley and Sons, 1990.
2. J. S. Yuan, “SiGe, GaAs, and InP Heterojunction Bipolar Transistors”, John Wiley and Sons,1999.
3. J. D. Cressler and G. Niu, "Silicon-Germanium Heterojunction Bipolar Transistors", Artech House, 2003.
4. M.Herniter “Programming in MATLAB”, Thomson Learning, 2001.


FUZZY LOGIC & NEURAL NETWORKS L T P Credits Total Marks

SECX5084
(Common to VLSI, Embedded, Appl. Elec.) 3 0 0 3 100
UNIT I FUNDAMENTALS OF ANN 10 hrs.

Introduction – Neuron Physiology – Specification of the brain – Eye neuron model - Fundamentals of ANN –
Biological neurons and their artificial models – Learning processes –different learning rules – types of activation functions
– training of ANN – Perceptron model ( both single & multi layer ) – training algorithm – problems solving using
learning rules and algorithms – Linear seperability limitation and its over comings
UNIT II ANN ALGORITHM 10 hrs.

Back propagation training algorithm – Counter propagation network – structure & operation – training – applications
of BPN & CPN -Statistical method – Boltzmann training – Cauchy training – Hop field network and Boltzmann machine
– Travelling sales man problem - BAM – Structure – types – encoding and retrieving – Adaptive resonance theory
– Introduction to optical neural network – Cognitron & Neocognitron
UNIT III APPLICATION OF ANN 10 hrs.

Hand written and character recognition – Visual Image recognition –- Communication systems – call processing
– Switching – Traffic control – routing and scheduling –Articulation Controller - Neural Acceleration Chip ( NAC )
UNIT IV INTRODUCTION TO FUZZY LOGIC 10 hrs.

Introduction to fuzzy set theory –– membership function - basic concepts of fuzzy sets – Operations on fuzzy sets
and relations, classical set Vs fuzzy set – properties of fuzzy set – fuzzy logic control principles – fuzzy relations – fuzzy
rules – Defuzzification – Time dependent logic – Temporal Fuzzy logic (TFC) – Fuzzy Neural Network ( FANN ) - Fuzzy
logic controller – Fuzzification & defuzzification interface .
UNIT V APPLICATION OF FUZZY LOGIC 10 hrs.

Application of fuzzy logic to washing machine – Vaccum cleaner – Water level controller – temperature controller
- Adaptive fuzzy systems – Fuzzy filters – Sub band coding – Adaptive fuzzy frequency hoping.
TEXT BOOK:
1. Freeman & Skapura “Neural Networks”, Addison - Wesley, 1991.
REFERENCE BOOKS:
1.J.M .Zurada “Introduction to Artificial Neural Systems”, West, 1992.
2.Simons Haykin “ Neural Networks”, Macmillan, 1994.
3.B.Yagnanarayana “Artificial Neural Networks”, Prentice Hall of India, 2006.



SECX5029 ASIC DESIGN
3 0 0 3 100
UNIT I INTRODUCTION TO ASICS, CMOS LOGIC 10 hrs.

Introduction – Types of ASIC – Design flow - CMOS logic – CMOS Design rules –Combinational & Sequential
logic cells – Data path Programmable ASIC logic cells and i/o cells. Programmable interconnects- Transitor Parasitic
capacitance-Logical effort.
UNIT II ASIC TECHNOLOGY 10 hrs.

ASIC library design - Cell design - Architecture - Gate array design - PLDs and FPGAs - ASIC families. CAD
for ASIC design - Design entry - VHDL/Verilog - Netlist extraction
UNIT III PROGRAMMABLE ASICS 10 hrs.

Anti fuse – static RAM –EPROM and EEPROM technology- PREP benchmarks-Actel ACT- Xilinx LCA –Altera
MAX DC & AC inputs and outputs-Clock & Power inputs- Xilinx i/o blocks.
UNIT IV DESIGN AUTOMATION TOOLS & ALGORITHMS 10 hrs.

Functional simulation - Synthesis - Layout, Placement, Floor planning – Routing Techniques for Simulation,
Synthesis, Layout, Placement, Positioning, Floor planning, Routing.
UNIT V TESTING 10 hrs.

Design for testability – Application Examples for ASICs: Low noise audio circuit, DC-DC converter - Case study:
ARM Processor.
TEXT BOOK:
1. M.J.S .Smith "Application - Specific Integrated Circuits", Addison -Wesley Longman Inc., 1997.
REFERENCE BOOKS:
1. S.H.Gerez, “Algorithms for VLSI Design Automation”, John Wiley, 1998.
2. Alfred L.Grouch, “Design for Test”, Prentice Hall - Professional Technical Reference, 1999.
3. Mohammed Ismail and Terri Fiez" Analog VLSI Signal and Information Processing", Mc Graw Hill, 1994.
4. S. Y. Kung, H. J. Whilo House, T. Kailath "VLSI and Modern Signal Processing", Prentice Hall, 1984.
5. Jose E. France, Yannis Tsividis " Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing
Prentice Hall, 1994.


AMS HARDWARE DESCRIPTION AND L T P Credits Total Marks

SECX5030
VERIFICATION LANGUAGES 3 0 0 3 100
UNIT I FUNDAMENTAL CONCEPTS AND MODELING IN VHDL-AMS 10 hrs.

Modeling systems – Domains and levels of modeling –Digital modeling, Analog modeling and Mixed signal
modeling example – Modeling languages – Modeling concepts- Test benches- Constant and Variables -Scalar types
– Type Declaration – Integer, Floating point, Physical and Enumeration types – Type classification –subtype – Type
Qualification and conversion –Scalar Natures –Attributes of Scalar types and natures –Expressions and Operators.
UNIT II DIGITAL MODELING CONSTRUCTS IN VHDL-AMS 10 hrs.

Entity Declarations- Architecture bodies- Concurrent statements- Signal declarations- Digital Behavioral
Descriptions-Signal assignment – signal attributes –wait statement – Delta delays- Transport and inertial Delay
Mechanisms- process statements- Concurrent signal assignment and assertion statements –Digital structural
descriptions-Component instantiation and port maps.
UNIT III ANALOG MODELING CONSTRUCTS IN VHDL-AMS 10 hrs.

Free Quantities – Quantity ports –Terminals and branch Quantities- Attributes of terminals and Quantities –
Simultaneous Statements –Simultaneous If, Case, Null statement- Analog structural Descriptions - Discontinuities and
Break statements – concurrent break statements – step limit specifications- Mixed signal descriptions- A/D and D/A
Conversion- Mixed Technology Descriptions.
UNIT IV INTRODUCTION TO SYSTEM VERILOG 10 hrs.

Introduction to system verilog- Data types – Arrays - Data declarations –Attributes –operators and Expressions
- procedural statements and control flow statements- process, tasks and functions- classes - Random constraints.
UNIT V INTERPROCESS SYNCHRONIZATION & COMMUNICATION IN SYSTEM VERILOG 10 hrs.

Introduction – scheduling Semantics – Clocking blocks – Program blocks – Assertions – Hierarchy - interfaces
– coverage- parameters – configuration libraries – system tasks and system functions – compiler directives.
TEXT BOOKS:
1. J. Ashenden & Peterson “The System Designer’s Guide to VHDL-AMS”, Morgan Kaufmann Publishers, 2003.
2. Chris Spear “System Verilog for Verification”, Springer Science+Business Media, 2008.
REFERENCE BOOKS:
1. Simon Davidmann & Stuart Sutherland “System Verilog For Design”, Springer Science+Business Media, 2008.
2. Stephen Brown "Funtamentals of Digital logic with verilog Design", Tata McGraw Hill, 2008.


ELECTROMAGNETIC INTERFERENCE & L T P Credits Total Marks

SECX5031 COMPATIBILITY
3 0 0 3 100
(Common to VLSI, Embedded)
UNIT I EMI ENVIRONMENT 10 hrs.

Introduction to EMI/EMC-Basics of electro Magnetic interference(EMI)Fundamentals of electromagnetic
compatibility(EMC)-Radiation hazards Transients and other EMI sources Transients Electrostatics
discharge(ESD)-Tempest- Lightning – Standards of EMI
UNIT II EMI COUPLING 10 hrs.

EMI from apparatus and circuits: Introduction-Electromagnetic emission-Appliances-noise from relays and
switches-nonlinearities in circuits-Passive inter modulation-Cross talk in transmission lines-Transmission in power supply
lines-Electromagnetic interference.
UNIT III EMI SPECIFICATION/STANDARDS AND MEASUREMENTS 10 hrs.

Units of specification-civilian standards and military standards.Basics of EMI measurements-EMI measurement
tools-TEMcell-measurement using TEM cell-Reverberating chamber-GTEM cell-Anechoic chamber-Open area test site-RF
absorbers-conducted interference measurements-conducted EMI from equipments-Experimental setup for measuring
conducted EMI-Measurement of DM interferences.
UNIT IV EMI CONTROL TECHNIQUE 10 hrs.

Shielding technique-Filter techniques-Grounding techniques-Bonding techniques-Cable connectors and
components-Isolation transformer-Transient suppressor
UNIT V EMC DESIGN OF PCB 10 hrs.

Designing for EMC:Introduction-Different techniques involved in designing for EMC-EMC guide lines for PCB
designs-EMC design guide line for audio and control circuit design-EMC guide lines for RF design-EMC guidelines
for power supply design-Mother board designs and propagation delay performance models
TEXT BOOK:
1. Bernhard Keiser ”Principles of Electromagnetic Compatibility”, Artech house, 3rd edition 1987.
REFERENCES BOOKS:
1. Henry W.Ott “Noise reduction Techniques in Electronics systems”,Johnwiley and sons.New York.1976.
2. DonWhite consultant incorporate-Handbook of EMI/EMC- Vol 1-1985
3. Clayton R. Paul "Introduction to EMC", Wiley & sons, 2006.
4. Sathyamurthy.S ”Basics of Electro Magnetic Compatibility”, Society of EMC Engineerings (India), 2003.
5. Kodali.V.P "Engineering EMC Principles, Measurements and Technologies", IEEE Press, 2001.


DIGITAL SIGNAL PROCESSORS ARCHITECTURES L T P Credits Total Marks

SECX5032
AND APPLICATIONS 3 0 0 3 100
UNIT I FUNDAMENTALS OF PROGRAMMABLE DSP’S 10 hrs.

Multiplier and Multiplier accumulator – Modified Bus Structures and Memory access in P-DSP’s – Multiple access
memory – Multi – port memory – VLIW architecture – pipelining – Special Addressing modes in P-DSP’s – On Chip
Peripherals.
UNIT II TMS320C5X PROCESSOR 10 hrs.

Architecture – Assembly Language syntax- Addressing modes- Assembly language Instructions – pipeline
structure, Operation – Block diagram of DSP Starter kit – Application Programs for processing real time signals.
UNIT III TMS320C3X PROCESSOR 10 hrs.

Architecture –Data formats – Addressing modes – Groups of addressing modes – Instruction sets – Operation
– Block diagram of DSP starter kit – Application, Programs for processing real time systems – Generating and finding
the sum of series, Convolution of two sequences , Filter design.
UNIT IV ADSP PROCESSORS 10 hrs.

Architecture of ADSP-21XX and ADSP – 210XX series of DSP processors – Addressing modes and Assembly
language instructions – Applications programs – Filter design, FFT calculation- Blackfin DSP Processor
UNIT V ADVANCED PROCESSORS 10 hrs.

Architecture of TMS320C54X: Pipe line operation, Code Composer Studio – Architecture of TMS320C6X –
Architecture of Motorola DSP563XX – Comparison of the features of DSP family processors.
TEXT BOOK:
1. B.Venkataramani and M.Bhaskar, “Digital Signal Processors – Architecture Programming and Application” -
Tata McGraw – Hill Publishing Company Limited. New Delhi, 2008.
REFERENCE BOOKS:
1. User guides Texas Instrumentation, Analog Devices, Motorola.
3. Anil K Jain “Fundamental of Digtal image processing”, Prentice Hall, 1989.


BLUETOOTH TECHNOLOGY L T P Credits Total Marks

SECX5085

Introduction to Wireless technologies: WAP services, serial and parallel Communication, Asynchronous and
synchronous communication, EDM, TFM, Spread spectrum technology
Introduction to Bluetooth: Specification, core protocols, cable replacement protocol
UNIT II BLUETOOTH RADIO AND NETWORKING 10 hrs.

Bluetooth Radio: Type of Antenna, Antenna Parameters, Frequency hoping Bluetooth Networking: Wireless
networking, Wireless network types, devices roles and states, adhoc network, scatter net.
UNIT III CONNECTION ESTABLISHMENT PROCEDURE 10 hrs.

Connection establishment procedure, notable aspects of connection establishment, Mode of connection, Bluetooth
Security, Security architecture, Security level of services, profile and usage model: Generic access profile (GAP), SDA,
serial profile, Secondary Bluetooth profile.
UNIT IV HARDWARE 10 hrs.

Hardware: Bluetooth implementation, Baseband overview, packet format, Transmission
Buffers, Protocol implementation: link manager protocol, logical link control Adaptation protocol, Host control
interface, protocol interaction with layers.
UNIT V APPLICATIONS 10 hrs.

Programming with Java: Java Programming, J2ME architecture, Javax, Bluetooth package interface, classes,
exceptions, Javax.obex package:interfaces, classes Bluetooth services overview of IRDA, HomeRF, Wireless LANs,
JINI
TEXT BOOK:
1. C.S.R.Prabhu and A.P.Reddi “Bluetooth Technology”, Prentice Hall of India 2004.
REFERENCE BOOKS:
1. Charels P.Pfleeger “Security in computing”, Prentice Hall 2003
2. Andreas F.Molisch “ Wideband wireless Digital Communication”, Prentice Hall, 2001.
3. George.V.Tsoulous “Adaptive Antennas for wireless Communication”, IEEE Press, 2001



SECX5033 DESIGN OF SEMICONDUCTOR MEMORIES
3 0 0 3 100
UNIT I RANDOM ACCESS MEMORY TECHNOLOGIES 10 hrs.

Static Random Access Memory(SRAMs):SRAM cell structure-MOS SRAM architecture-MOS SRAM cell and peripheral
circuit operation-bipolar SRAM technologies- Silicon on insulator(SOI) technology-advanced SRAM archtectures and
technologies, application specific SRAMs-CMOS CRAMs - DRAMs cell theory and advanced cell structures-BiCMOS
DRAMs-soft error failure in DRAMs -Advanced DRAM designs and architecture-application specific DRAMs.
UNIT II NONVOLATILE MEMORIES 10 hrs.

Masked Read-only memories (ROMs) : High density ROMs-Programmable read only memories(PROMs) - Bipolar
PROMs- CMOS PROMs-erssable(UV)- Programmable read only memories (EPROMs)-Floating Gate EPROMcell-one -
time programmable (OTP) EPROMs-Electrically Erasable PROMs(EEPROMs)- EEPROM technology and
architecture-nonvolatile SRAM-Flash memories(EPROMs or EEPROM)-Advanced flash memory architecture.
UNIT III ADVANCED MEMORY TECHNOLOGIES AND HIGH –DENSITY MEMORY PACKAGING
TECHNOLOGIES 10 hrs.
Ferroelectric Random Access Memories(FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog memories magneto
resistive random access memories(MRAMs) – Experimental memory devices.
Memory hybrids and MCMs(2D)-Memory stacks and MCMs (3D)-Memory MCM testing and reliability
issues-memory cards-high density memory packaging future directions.
UNIT IV SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS 10 hrs.

General Reliability issues-RAM failure modes and mechanism-nonvolatile memory reliability-reliability modeling
and failure rate prediction- design for reliability-reliability test structures-reliability screening and qualification.
Radiationeffects-single event phenomenon(SEP)-radiation hardening techniques-radiation hardening process and design
issues-radiation hardened memory characteristics-radiation hardness assurance and testing-radiation dosimetry - water
level radiation testing and structures.
UNIT V MEMORY FAULT MODELING,TESTING AND MEMORY DESIGN FOR TESTABILITY AND DAULT
TOLERANCE 10 hrs.
RAM fault modeling,electrical testing,Pseudo random testing-megabit DRAM-nonvolatile memory modeling and
testing-IDDQ fault modeling and testing-application specific memory testing and the tools for fault modeling and testing
TEXT BOOK:
1. Ashok K.Sharma “Semiconductoer Memories Technology,testing and reliability", IEEE Press, 1997.
REFERENCE BOOKS:
1. Ivan Sutherland Bob sproull, David Harris, "Logical Efforts, Designing Fast CMOS Circuits", Kluwr Academic Press, 1999.
2. David Harris, "Skew Tolerant domino Design", Prentice Hall of India Private Ltd , 2000


CRYPTOGRAPHY & NETWORK SECURITY L T P Credits Total Marks

SCSX5031
UNIT I INTRODUCTION & MATHEMATICAL FOUNDATION 10 hrs.

Beginning with a simple communication game – wresting between safeguard and attack – Probability and
Information Theory - Algebraic foundations – Number theory.
UNIT II ENCRYPTION – SYMMETRIC TECHNIQUES 10 hrs.

Substitution Ciphers - Transposition Ciphers - Classical Ciphers – DES – AES – Confidentiality Modes of
Operation – Key Channel Establishment for symmetric cryptosystems.
UNIT III ENCRYPTION – ASYMMETRIC TECHNIQUES & DATA INTEGRITY TECHNIQUES 10 hrs.
Diffie-Hellman Key Exchange protocol – Discrete logarithm problem – RSA cryptosystems & cryptanalysis –
ElGamal cryptosystem – Need for stronger Security Notions for Public key Cryptosystems – Combination of Asymmetric
and Symmetric Cryptography – Key Channel Establishment for Public key Cryptosystems - Data Integrity techniques
– Symmetric techniques - Asymmetric techniques
UNIT IV AUTHENTICATION 10 hrs.

Authentication Protocols Principles – Authentication protocols for Internet Security – SSH Remote logic protocol
– Kerberos Protocol – SSL & TLS – Authentication frame for public key Cryptography – Directory Based Authentication
framework – Non - Directory Based Public-Key Authentication framework .
UNIT V SECURITY PRACTICES 10 hrs.

Protecting Programs and Data – Information and the Law – Rights of Employees and Employers – Software
Failures – Computer Crime – Privacy – Ethical Issues in Computer Security.
TEXT BOOK:
1. Wenbo Mao “Modern Cryptography – Theory and Practice”, Pearson Education, First Edition, 2006.
REFERENCE BOOKS:
1. Douglas R. Stinson “Cryptography Theory and Practice ”, Third Edition, Chapman & Hall/CRC,2006.
2. Charles B. Pfleeger, Shari Lawrence Pfleeger “Security in Computing”, Fourth Edition, Pearson Education, 2007.
3. Wade Trappe and Lawrence C. Washington “Intrduction to Cryptography with Coding Theory” Second Edition, Pearson
Education, 2007.



SECX5034 VLSI FOR WIRELESS COMMUNICATION
3 0 0 3 100
UNIT I 10 hrs.
Review of Modulation Schemes – BFSK- BPSK –QPSK – OQPSK – Classical Channel - Additive White Gaussian
Noise – Finite Channel Bandwidth - Wireless Channel- Path Environment - Path Loss – Friis Equation - Multipath
Fading – Channel Model - Envelope Fading – Frequency Selective Fading – Fast Fading - Comparison of different
types of Fading- Review of Spread Spectrum – DSSS – FHSS - Basic Principle of DSSS - Modulation –Demodulation
- Performance in the presence of noise-narrowband and wideband interferences.
UNIT II 10 hrs.
Receiver Front End – Motivations - General Design Philosophy- Heterodyne and Other architectures - Filter
Design - Band Selection Filter – Image Rejection Filter - Channel Filter - Non idealities and Design Parameters -
Harmonic Distortion – Intermodulation -Cascaded Nonlinear Stages – Gain Compression – Blocking – Noise - Noise
Sources -Noise Figure - Design of Front end parameter for DECT.
UNIT III 10 hrs.

Low Noise Amplifier – Introduction - Matching Networks – Matching for Noise and Stability – Matching for Power
– Implementation - Comparison of Narrowband and Wideband LNA - Wideband LNA Design - Narrowband LNA –
Impedance matching -Power matching- Salient features of LNA –Core Amplifier Design.
UNIT IV 10 hrs.
Demodulators - Delta Modulators - Low Pass Sigma Delta Modulators – High Order Modulators - One Bit DAC
and ADC –Passive Low Pass Sigma Delta Modulator - Band pass Sigma Delta Modulators – Comparison - PLL
based Frequency Synthesizer - Loop Filter Design and Implementation.
UNIT V 10 hrs.
Implementations: VLSI architecture for Multitier Wireless System - Hardware Design Issues for a Next generation
CDMA System - Efficient VLSI Architecture for Base Band Signal processing.
TEXT BOOK:
1. Bosco Leung “ VLSI for wireless Communication”, Prentice Hall, 2002.
REFERENCE BOOKS:
1. Andreas F.Molisch “ Wideband wireless Digital Communication”, Prentice Hall PTR, 2001.
2. George.V.Tsoulous “Adaptive Antennas for wireless Communication", IEEE Press, 2001.
3. Xiaodong Wang and H.Vincent “Wireless Communication System ,Advanced Techniques for Signal Reception”, Pearson
Education. 2004



SECX5035 RF IC DESIGN
3 0 0 3 100
UNIT I RF ELECTRONIC CONCEPTS 10 hrs.

Introduction – RF Microwave Vs DC or AC signals – Importance of radio frequency design – RF behaviour of
passive components – High frequency resistors - High frequency capacitors - High frequency inductors – Chip
components – Circuit board consideration –Chip resistors-Chip capacitors-Surface mounted inductors- resonant circuits
– Analysis of a simple circuit and Phasor domain – Impedance transformation – Insertion loss- Impedance transformers-
RF impedance matching. BJT and MOSFET behavior at RF.
UNIT II SMITH CHART 10 hrs.

Introduction to smith chart – Applications of smith chart – From reflection coefficient to load impedance – Parametric
reflection coefficient equation – Graphical representation – Impedance transformation – Admittance transformation – Parallel
line series connection. Definition of impedance matching – Selection of a matching network –Goal of impedance matching
– Design of matching circuits using lumped elements – Matching network design using distributed elements.
UNIT III MATCHING AND BIASING NETWORK 10 hrs.

Impedance Matching using discrete component- Two component matching networks-Forbidden regions, Frequency
response, Quality factor, T and Pi matching networks, micro-strip line matching network- discrete component from
micro strip lines, single stub matching networks, double stub matching networks, amplifier classes of operation and
biasing network, classes of operation and efficiency of amplifiers, bipolar transistors biasing networks, Field Effect
transistors biasing networks.
UNIT IV DESIGN OF AMPLIFIERS 10 hrs.

Stability considerations in active network – Gain considerations in amplifiers – Power gain concepts – Unilateral
transistor – Mismatch factor – Input &output VSWR – Maximum gain design – Constant gain circles – Unilateral figure
of merit – Bilateral case – Amplifiers RF circuit design –Design of different types of amplifiers –Narrow band amplifier
design – High gain amplifier design – Maximum gain amplifier design – Low noise amplifier design -Maximum noise
amplifier design –Broad band amplifier design- Multistage small signal amplifier design – High power amplifier –Large
signal amplifier design - Integrated RF Filters,
UNIT V RF MICROWAVE OSCILLATOR DESIGN 10 hrs.

Introduction – Basic oscillator model –negative resistance oscillator –High frequency oscillator configuration -
Oscillator Vs amplifier design – Oscillation condition – Two port NR oscillators – One port NR oscillators –Condition
of stable operation – Design of transistor oscillator -Fixed frequency oscillator - dielectric resonator oscillator - Frequency
tunable oscillator – YIG tuned oscillator – Varactor tuned oscillator – Gunn element oscillator,Mixers.
TEXT BOOKS:
1. Matthew M.Radmanesh ”Radio frequency & Microwave Electronics illustrated“, Prentice Hall, 2001.
2. Reinhold Ludwig Panel Brechko ”RF circuit design“, Pearson Education, 2009.
REFERENCE BOOKS:
1. Robbert J Webber ”Radio frequency & design applications“, IEEE Press, 2001
2. Jeremy Everard “Fundamentals of RF Circuit Design”, John Wiley, 2001.
3. Thomas H.Lee, “The Design of RF Integrated Circuits” ,Cambridge university press, 2004.


COMPUTER ARCHITECTURE AND PARALLEL L T P Credits Total Marks

SECX5036
PROCESSING 3 0 0 3 100
UNIT I THEORY OF PARALLELISM 10 hrs.

Parallel computer models-the state of computing, multiprocessors and Multicomputers and Multivectors and SIMD
computers, PRAM and VLSI models, Architectural development tracks.
UNIT II APPLICATIONS 10 hrs.

Programs and network properties-conditions of parallelism, Program partitioning and scheduling, program flow
mechanisms, system interconnect architectures, principles of scalable performance matrices and measures, parallel
processing applications, speed up performance laws, scalability analysis and approaches.
UNIT III HARWARE TECHNOLOGIES 10 hrs.

Processor and memory hierarchy advanced processor technology, superscalar and vector processors, memory
hierarchy technology, virtual memory technology, bus cache and shared memory-backplane bus systems, cache memory
organizations, shared memory organizations, sequential and weak consistency models
UNIT IV PIPELINING AND SUPER SCALAR TECHNOLOGIES 10 hrs.

Parallel and scalable architectures, Multiprocessor and multicomputers, Multivector and SIMD computers, Scalable,
Multithreaded and data flow architecture.
UNIT V SOFTWARE AND PARALLEL PROGRAMMING 10 hrs.

Parallel models, Languages and compilers, Parallel program development environments, UNIX, MACH and OSF/1
for parallel computers.
TEXT BOOK:
1. Kai Hwang “Advanced computer Architecture”, Tata McGraw Hill International, 1993.
REFERENCE BOOKS:
1. William Stalling “Computer Organization and Architecture”, Pearson Education, INC, 2010.
2. M.J.Quinn “Designing Efficient Algorithms for parallel computers”, McGraw Hill international, 1987.



SECX5037 MIXED SIGNAL PROCESSING
3 0 0 3 100

Introduction-modeling basic analog concepts-analog circuit analysis-network independent-dependence data
sampled analog systems, loading.
UNITT II VHDL APPLICATION TO ANALOG AND MIXED SIGNAL EXTENSIONS 10 hrs.

Introduction-language design objectives-Theory of differential algebraic equation-the 1076.1 language-tolerance
groups-conservative systems-time and the simulation cycle-A/D and D/A interaction-Question point-frequency domain
modeling and examples.
UNIT III ANALOG EXTENSIONS TO VERILOG 10 hrs.

Introduction-equation construction-solution-waveform filter functions-simulator-control analysis-multi-disciplinary
model.
UNIT IV BEHAVIORAL GENERIC MODEL OF OPERATIONAL AMPLIFIERS 10 hrs.

Introduction-description of generic opamp model-structure-configuration-functional specification-auxiliary
block-conflict resolution-application examples.
UNIT V NON-LINEAR STATE SPACE AVERAGED MODELING OF 3-STATE DIGITAL PHASE-

FREQUENCY DETECTOR 10 hrs.
Introduction-modeling of multi state phase frequency detector-resetable integrator-AC analysis-sample application.
TEXT BOOK:
1. Alain Vachoux jean-Michel Borage oz levia “Analog and mixed signal hardware description language (current issues in
electronic modeling V.10)", Kluwer academic publishers 1997.
REFERENCE BOOKS:
1. Philip E-Allen, Dougles R.Holberg “CMOS analog circuit design” second edition oxford university press 2002.
2. Behzad Razavi “Design of analog CMOS integrated circuits” Tata McGraw Hill edition 2002.
3. John G Proakis “Digtal signal processing”, Pearson Prentice Hall, 2007.



SECX5038 HIGH SPEED VLSI DESIGN
3 0 0 3 100
UNIT I 10 hrs.
Clocked logic styles, single-Rail Domino logic styles, Dual-Rail Domino structures, Latched Domino structures,
clocked pass gate logic Non clocked logic styles, Static CMOS ,DCVS logic ,N0n-clocked pass Gate Families.
UNIT II 10 hrs.
Circuit design Margining, Design induced Variations, process induced Variations, Application induced Variations,
Noise.
UNIT III 10 hrs.

Latching strategies, Basic Latch Design, Latching Differential logic,Hazards,Race Free Latches for Pre-charged
logic, Asynchronous latch techniques.
UNIT IV 10 hrs.
Signaling standards, chip-to-chip communication Networks, ESD Protection, Standards and Models with design
-Skew Tolerant design.
UNIT V 10 hrs.
Clocking styles, clock jitter, signal skew, clock skew, and data feed through clock generation, clock distribution,
and asynchronous clocking techniques.
TEXT BOOK:
1. Kerry Bernstein "High Speed CMOS Design styles", Kulwer Academic Publishers, 2002.
REFERENCES BOOKS:
1. Ivan Sutherland, Bob sproull, David Harris "Logical Efforts: Designing Fast CMOS Circuits", Kluwr Academic Publishers, 1999.
2. David Harris, "Skew Tolerant domino Design", Prentice Hall of India Private Ltd, 2000.


BASICS OF NANOTECHNOLOGY L T P Credits Total Marks

SECX5039
UNIT I INTRODUCTION TO NANOTECHNOLOGY 10 hrs.

Nanoscale technology : Consequences of the nanoscale for technology and society. Beyond Moore’s Law.
Molecular building blocks for nanostructure systems, Nano-scale 1D to 3D structures,
Energy Band Diagram : Energy level diagram, Fermi function, n-type operation, p-type operation, Rate equations
for a one-level model, Current in a one-level model, Inflow / Outflow, Pauli blocking, quantum of conductance, Potential
profile, Iterative procedure for self-consistent solution, Quantum capacitance, Negative Differential Resistance (NDR).
UNIT II ELECTRICAL RESISTANCE-AN ATOMISTIC VIEW 10 hrs.

Negative differential resistance-thermo electric effect-Nano transistors-inelastic spectroscopy-NEGF formalism-input
parameters-derivation of NEGF equations-model Hamiltonian.
UNIT III MOLECULAR ELECTRONIC DEVICES 10 hrs.

Basic Concepts- Self assembled Layers, Charge transport Mechanisms; Synthesis of Molecular wires and devices
– synthesis of two terminal devices, Fabrication of molecular transport devices; Simple SAM metal-insulator-metal
Tunneling.
UNIT IV NANOSCALE DEVICE MODELING 10 hrs.

Inadequacy of macroscopic models, Equilibrium, Non-Equilibrium, Density Matrix and current operator; NEGF
Formalism – Broadening.
UNIT V NANOSCALE DEVICE MODELING 10 hrs.

Quantum Point Contact- Hamiltonian, Self energy; SAM- Signals used to control and probe molecules, Synthesis;
Fabrication and overview of Nanotube devices- their properties.
REFERENCE BOOKS:
1. Mark A. Reed and Takhee Lee “Molecular Nano electronics”, American scientific Publisher, 2003.
2. Suprio Dutta "Tutorial on Electrical Resistance-an atomistic view", Purdue University, 2004.
3. Horst-Gunter Rubahn "Basics of Nano Technology", Wiley-VCH verlagGmbh & Co, 2008.
4. Chris Binns "Introduction to Nano science and Nano Technology", John wiley & sons, 2010.
Max. Marks: 80 Exam Duration : 3 hrs


NANO SENSORS AND APPLICATIONS L T P Credits Total Marks

SECX5040
UNIT I 10 hrs.
Fundamentals of Nano Sensors: Micro and nano-sensors, Fundamentals of sensors, biosensor, micro fluids,
MEMS and NEMS, Packaging and characterization of sensors, Method of packaging at zero level, dye level and first
level.Sensors.
UNIT II 10 hrs.
Quantum Structures and Devices:Quantum layers, wells, dots and wires, Mesoscopic Devices, Nanoscale
Transistors, Single Electron Transistors, MOSFET and NanoFET, Resonant Tunneling Devices, Carbon Nanotube based
logic gates, optical devices. Connection with quantum dots, quantum wires, and quantum wells.
UNIT III 10 hrs.

Sensors for aerospace and defense: Accelerometer, Pressure Sensor, Night Vision System, Nano tweezers,
nano-cutting tools, Integration of sensor with actuators and electronic circuitry, Civil applications: metrology, bridges
and other industrial applications.
UNIT IV 10 hrs.
Biosensors:Clinical Diagnostics, generation of biosensors, immobilization, characteristics, applications, conducting
Polymer based sensor, DNA Biosensors, optical sensors. Biochips. Metal Insulator Semiconductor devices, molecular
electronics, information storage, molecular switching, Schottky devices. Sensor for bio-medical applications: Cardiology,
Neurology and as diagnostic tool.
UNIT V 10 hrs.
Magnetic biosensors: Introduction, Magnetoresistance-based sensors, Hall effect sensors, Other sensors detecting
stray magnetic fields, Sensors detecting magnetic relaxations, Sensors detecting ferrofluid susceptibility.
REFERENCE BOOKS:
1. H. Mexiner " Sensors: Micro & Nanosensors, Sensor Market trends", Wiley-VCH-1995.
2. Ping Sheng, Zikang Tang "Nanoscience & Technology: Novel Structure and phenomena", Taylor & Francis-2003.
3. Michael Rieth "Nano Engineering in Science & Technology: An Introduction to the world of Nano design", World Scientific publishing
Co.pte.ltd-2003.
4. Vijay K.Varadan "Nanosensors, Microsensors and Biosensors and systems", SPIE International Society for Optical Engine-2007.
5. Larry Nagahara, Nongjian Tao, Thomas Thundal "Introduction to Nanosensors Series: Nanostructure Science and Technology",
Springer-verlag New York Inc-2008

Part B: 5 Questions from each of the five units of internal choice each carrying 10 marks 50 marks


SECX5041 DIGITAL DESIGN WITH CPLD APPLICATION
3 0 0 3 100
UNIT I INTRODUCTION TO DIGITAL SYSTEMS 10 hrs.

Analog vs Digital systems, digital devices, integrated circuits, programmable logic devices, digital design levels,
software aspects of digital design.
UNIT II LOGIC CIRCUITS 10 hrs.

Combinational circuit synthesis – minimization, Karnaugh Maps, sum of products and product of sums expressions
and their minimization, programmed minimization methods – Quine McCluskey minimization algorithm, timing hazards
– static and dynamic hazards, introduction to VHDL hardware description language.
UNIT III SEQUENTIAL LOGIC PRINCIPLES 10 hrs.

Bistable elements, Latches and flip–flops, S-R latch, D latch, Edge triggered D flip–flop, Master/slave flip–flops,
T flip–flop.
UNIT IV INTRODUCTION TO PLD’S & MAX PLUS II 10 hrs.

Programming PLDs using MAX PLUS II, Graphic Design File, Compiling MAX PLUS II Files, Hierarchical Design.
UNIT V COMBINATIONAL LOGIC DESIGN PRACTICES 10 hrs.

Documentation standards, Circuit timing, Combinational PLDs. Design using SSI and MSI devices Decoders,
Encoders, Three state buffers, Multiplexers, Parity circuits, Comparators, Adders, Subtractors, ALUs, Combinational
multipliers. Using VHDL and PLDs Combinational circuit design examples – barrel shifter, simple floating – point encoder,
cascading comparator.
TEXT BOOK:
1. Robert K. Dueck "Digital Design with CPLD Applications and VHDL", Thomson Asia Pte. Ltd., Singapore, 2001.
REFERENCE BOOKS:
1. John F. Wakerley "Digital Design: Principles and Practices", third edition updated, Prentice Hall, 1990.
2. Stephen Brown & Zvonko Vranesic "Fundamentals of Digital logic with VHDL design", first edition, McGraw Hill, 2008.
3. Alan B. Marcovitz "Introduction to logic design", McGraw Hill International edition 2007.
4. James Bignell & Robert Donovan "Digital Electronics", fourth edition, Thomson Asia Pte. Ltd., Singapore, 2006.



SECX5042 ALGORITHMS FOR VLSI DESIGN AUTOMATION
3 0 0 3 100
UNIT I METHODS FOR COMBINATIONAL OPTIMIZATION 10 hrs.

Introduction to Design Methodologies, Design Automation tools, algorithmic Graph Theory, Computational
complexity, Tractable and Intractable problems. Backtracking, Branch and Bound, Dynamic Programming, Integer Linear
Programming, Local Search, Simulated Annealing, Tabu search, Genetic Algorithms.
UNIT II CLUSTERING 10 hrs.

Layout Compaction, Placement, Floor planning And Routing Problems, Rajaraman and Wong Algorithm, Flow
Map Algorithm, Multi-Level Coarsening Algorithm.
UNIT III PARTITIONING & FLOOR PLANNING 10 hrs.

Kernighan and Lin Algorithm, Fiduccia and Mattheyses Algorithm, EIG Algorithm, FBB Algorithm.
Floorplanning algorithms - Stockmeyer Algorithm, Normalized Polish Expression, ILP Floor planning Algorithm,
Sequence Pair Representation.
UNIT IV PLACEMENT & ROUTING 10 hrs.

Mincut Placement, GORDIAN Algorithm, TimberWolf Algorithm. Routing - Steiner Min-Max Tree Algorithm ,
Multi-Commodity Flow Routing Algorithm , Iterative Deletion Algorithm , Yoshimura and Kuh Algorithm.
UNIT V PHYSICAL DESIGN AUTOMATION OF FPGA’S & MCM’S 10 hrs.

FPGA technologies, Physical Design cycle for FPGA’s, partitioning and routing for segmented and staggered
Models.MCM technologies, MCM physical design cycle, Partitioning, Placement - Chip Array based and Full Custom
Approaches.
TEXT BOOK:
1. S.H.Gerez, WILEY "Algorithms for VLSI Design Automation", Student Edition, John wiley & Sons (Asia) Pvt. Ltd., 1999.
REFERENCE BOOKS:
1. Sung Kyu Lim "Practical Problems in VLSI Physical Design Automation", Springer, 2008.
2. Naveed Sherwani "Algorithms for VLSI Physical Design Automation", 3rd edition, Kluwer Academic Publishers, 1995.
3. Hill & Peterson "Computer Aided Logical Design with Emphasis on VLSI", Wiley, 1993.
4. Wayne Wolf "Modern VLSI Design: Systems on silicon", Pearson Education Asia, 2nd Edition, 2006.

Part B: 5 Questions from each of the five units of internal choice,each carrying 10 marks 50 marks


SECX5043 HIGH-LEVEL SYNTHESIS OF DIGITAL CIRCUITS
3 0 0 3 100
UNIT I INTRODUCTION TO HIGH-LEVEL SYNTHESIS 10 hrs.

System-Level Design of Hardware Systems - Overview of High-Level Synthesis - Role of Parallelizing Compiler
Transformations in HLS - HLS for Behaviors with Complex Control Flow - Intermediate Representations in High-Level
Synthesis - Use of Loop Transformations in Compilers and High-Level Synthesis
UNIT II MODELS AND REPRESENTATIONS 10 hrs.

Modeling the Problem - Design Description Modeling - Modeling Data Dependencies - Better Design Visualization
- Modeling Control Flow - Modeling Hardware Resources, Timing and Data Types - Formulation of the Scheduling
Problem - Constraints due to Data Dependencies - Resource-Constrained Scheduling - Model-ing Parallelizing Code
Motions - Scheduling Designs with Control Flow - Modeling Resource Utilization
UNIT III PARALLELIZING HIGH-LEVEL SYNTHESIS 10 hrs.

Methodology- Design Flow through a PHLS Framework -Passes and Techniques- Pre-Synthesis Compiler
Optimizations -Common Sub-Expression Elimination- Loop-Invariant Code Motion- Loop Unrolling -Loop Index Variable
Elimination -Compiler and Synthesis Transformations-Limits of Parallelism within Basic Blocks-Speculation and
Predicated Execution in Compilers-Role of Speculative Code Motions in High-Level Synthesis-Dynamic Common
Sub-Expression Elimination-Chaining Operations Across Conditional Boundaries-Loop Shifting
UNIT IV CODE TRANSFORMATIONS AND SCHEDULING 10 hrs.

Software Architecture of the Scheduler-Priority-based Global List Scheduling Heuristic-Collecting the List of
Available Operations-Trailblazing-Based code motion algorithm-Dynamic CSE Algorithm-Design Traversal
Algorithms-Dynamic Branch Balancing-Incorporating Chaining into the Scheduler-Loop Shifting Algorithm-Resource
Binding and Control Synthesis- Introduction -Resource Binding-Modeling Interconnect Minimizing Resource
Binding-Operation to Functional Unit Binding-Variable to Register Binding- Control Synthesis in the PHLS Framework
UNIT V SPARK: IMPLEMENTATION, SCRIPTS AND DESIGN EXAMPLES 10 hrs.

Implementation of the SPARK PHLS Framework-Command-line Options and Scripts in SPARK-Interdependencies
between the Code Motions- Enabling and Disabling One Code Motion at a Time - Enabling Multiple Code Motions
at a Time- Ways of Calculating Priority- Design Examples- Study of Loop Unrolling and Loop Shifting - Synthesis of
an Instruction Length Decoder.
TEXT BOOK:
1. Sumit Gupta, Rajesh K. Gupta “A Parallelizing Approach to The High-Level Synthesis of Digital Circuits”, Kluwer Academic Publishers,
2004
REFERENCE BOOKS:
1. Philippe Coussy , Adam Morawiec “High Level Synthesis from Algorithm to Digital Circuit”, Springer 2008.
2. Richard Sharp “Higher-Level Hardware Synthesis”, Springer 2004.



SECX5083 PROGRAMMING IN PERL
3 0 0 3 100

Typical uses of Perl – Event driven Simulators -Perl -Perl philosophy - A Perl program-Three virtues of a
programmer - Parts of Perl - The Perl interpreter - Manuals/Documentation-Perl Modules - Perldoc: Using perldoc -
Other ways to access perldoc - Creating and running a Perl program: Perl program- Running a Perl program from
the command line Executing code-The "shebang" line for Unix-The "shebang" line for non-Unixes -Command line
options and warnings-Lexical warnings.
UNIT II VARIABLES AND ARRAYS 10 hrs.

Perl variables- Special characters - Advanced variable interpolation- Arrays-Initializing an array-Reading and
changing array values -Array slices - Array interpolation Counting backwards - Finding out the size of an array -Printing
out the values in an array-Hashes -Initializing a hash-Reading hash values -Adding new hash elements -Changing
hash values-Deleting hash values-Finding out the size of a hash -Other things about hashes-Special variables.
UNIT III OPERATORS AND FUNCTIONS 10 hrs.

Operators- Arithmetic operators-String operators-Other operators –Functions-Types of arguments-Return values
-Some easy functions-String manipulation-Finding the length of a string-Case conversion -Numeric functions -Type
conversions -Manipulating lists and arrays-push, pop, shift and unshift -Ordering lists-Converting strings to lists.
UNIT IV CONDITIONAL CONSTRUCTS 10 hrs.

The if conditional construct -Comparison operators -Existence and definitiveness-boolean logic operators -Logic
operators and short circuiting -Boolean assignment -Loop conditional constructs -while loops-for and foreach-Practical
uses of while loops: taking input from STDIN -Named blocks-Breaking out or restarting loops-Smart-match-given and
when.
UNIT V SUBROUTINES AND REGULAR EXPRESSIONS 10 hrs.

Subroutines: Introducing subroutines-Using subroutines in Perl.-Calling a subroutine- Passing arguments to a
subroutine -Passing in scalars -Passing in arrays and hashes-Returning values from a subroutine -Regular expressions
-Regular expression operators and functions-m/PATTERN/ - the match operator -s/PATTERN/REPLACEMENT/ - the
substitution operator-Binding operators -Easy modifiers -Meta characters -Some easy meta characters-Quantifiers
-Grouping techniques -Character classes -Alternation-The concept of atoms.
TEXT BOOK:
1. Kirrily Robert,Paul Fenwick,Jacinta Richardson, "Programming Perl", O’Reilly & Associates, Inc 2000.
REFERENCES BOOKS:
1. Gabor Szabo "Fundamentals of Perl", 1.11 Edition,Published Sun May 27 23:22:58 2007.
2. Perl Programmers Reference Guide-Version 5.005_02-18-Oct-1998


RF MEMS AND ITS APPLICATIONS L T P Credits Total Marks

SECX5051
(Common to VLSI, NanoTech, Appl. Elec.) 3 0 0 3 100

MEMS-Microfabrications for MEMS -Surface micromachining of silicon -Wafer bonding for MEMS-LIGA
process-Micromachining of polymeric MEMS devices -Three-dimensional microfabrications.Transducers: Electromechanical
transducers-Piezoelectric transducers -Electrostrictive transducers -Magnetostrictive transducers -Electrostatic
actuators-Electromagnetic transducers -Electrodynamic transducers- Actuators: Electrothermal actuators-Comparison of
electromechanical actuation schemes.
UNIT II MICRO SENSING FOR MEMS 10 hrs.
Piezoresistive sensing - Capacitive sensing - Piezoelectric sensing - Resonant sensing - Surface acoustic wave sensors.
Materials: Materials for MEMS - Metal and metal alloys for MEMS - Polymers for MEMS - Other materials for MEMS.Metals
: Evaporation –Sputtering. Semiconductors :Electrical and chemical properties-Growth and deposition.Thin films for MEMS and
their deposition techniques -Oxide film formation by thermal --oxidation -Deposition of silicon dioxide and silicon nitride -Polysilicon
film deposition -Ferroelectric thin films. Materials for polymer MEMS: Classification of polymers -UV radiation curing -SU-8 for
polymer MEMS.
UNIT III MICRO MACHINING AND LITHOGRAPHY 10 hrs.
Micromachning : Bulk micromachining for silicon-based MEMS -Isotropic and orientation-dependent wet etching - Dry etching
-Buried oxide process -Silicon fusion bonding -Anodic bonding -Silicon surface micromachining Sacrificial layer technology - Material
systems in sacrificial layer technology - Surface micromachining using plasma etching -Combined integrated-circuit technology and
anisotropic wet etching .Lithography : Microstereolithography for polymer MEMS -Scanning method -Two-photon
microstereolithography Surface micromachining of polymer MEMS -Projection method -Polymeric MEMS architecture with silicon,
metal and ceramics -Microstereolithography integrated with thick film lithography.
UNIT IV MEMS INDUCTORS AND CAPACITORS 10 hrs.
Introduction- MEMS/micromachined passive elements: pros and cons. MEMS inductors : Self-inductance and mutual
inductance - Micromachined inductors - Effect of inductor layout - Reduction of stray capacitance of planar inductors-Approaches
for improving the quality factor Folded inductors - Modeling and design issues of planar inductors - Variable inductors – Polymer
based inductors.MEMS capacitors: MEMS gap-tuning capacitors - MEMS area-tuning capacitors - Dielectric tunable capacitors.
Micromachined antennae : Introduction - Overview of microstrip antennae- Basic characteristics of microstripeantennae - Design
parameters of microstrip antennae - Micromachining techniques to improve antenna performance - Micromachining as a fabrication
process for small antennae - Micromachined reconfigurable antennae.
UNIT V APPLICATIONS 10 hrs.
Switching: Introduction- Switch parameters- Basics of switching - Mechanical switches-Electronic switches- Switches for RF
and microwave applications - Mechanical RF switches - PIN diode RF switches - Metal oxide semiconductor field effect transistors
and monolithic microwave integrated circuits. RF MEMS switches : Integration and biasing issues for RF switches -Actuation
mechanisms for MEMS devices-Electrostatic switching - Approaches for low-actuation-voltage switches - Mercury contact switches
-Magnetic switching - Electromagnetic switching - Thermal switching.Dynamics of the switch operation : Switching time and dynamic
response - Threshold voltage. MEMS switch design, modeling and evaluation:Electromechanical finite element analysis - RF design
- MEMS switch design considerations.
TEXT BOOK:
1. Vijay K.Varadan, K.J.Vinoy and K.A.Jose “RF MEMS and Their Applications", John Wiley & Sons Ltd., 2003.
REFERENCE BOOKS:
1. P. Rai-choudhury “MEMS and MOEMS Technology and Applications”, SPIE The Internation Society for Optical Engineering, 2003.
2. S. Senturia "Microsystem Design", Kluwer Academic Publisher, 2001.
3. J.W. Gardner, V.K. Varadan, O.O. Awadelkarim "Microsensors, MEMS & Smart Devices", JohnWiley & Sons, 2001.


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SATHYABAMA UNIVERSITY

(Established under section 3 of UGC Act, 1956)

(ii) Practical courses

M.Tech (VLSI DESIGN) i REGULATIONS 2010

7. Award of Credits and Grades

RANGE OF MARKS FOR GRADES

Range of Marks Grade Grade Points (GP)

CUMULATIVE GRADE POINT AVERAGE CALCULATION

where Ci - Credits for the subject

GP i - Grade Point for the subject

Σi - Sum of all subjects successfully cleared during all the semesters

M.Tech (VLSI DESIGN) ii REGULATIONS 2010

8. Classification of the Degree Awarded

CGPA ≥ 9.0 - First Class - Exemplary

CGPA ≥ 7.50 < 9.0 - First Class with Distinction

CGPA ≥ 6.00 < 7.50 - First Class

CGPA ≥ 5.00 < 6.00 - Second Class

Minimum CGPA requirements for award of Degree is 5.0 CGPA.

10. Revision of Regulations and Curriculum

M.Tech (VLSI DESIGN) iii REGULATIONS 2010

M.Tech – VLSI DESIGN

M.Tech (VLSI DESIGN) iv REGULATIONS 2010

Sl.No. SUBJECT CODE SUBJECT TITLE L T P C

Total Credits For the Course: 70

LIST OF ELECTIVE SUBJECTS

Sl.No. SUBJECT CODE SUBJECT TITLE L T P C Page No.

L - Lecture Hours; T - Tutorial Hours; P - Practical Hours; C - Credits

M.Tech (VLSI DESIGN) v REGULATIONS 2010

TRANSFORMS & PROBABILITY FOR L T P Credits Total Marks

UNIT I ID TRANSFORMS 10 hrs.

UNIT II 2D TRANSFORMS 10 hrs.

UNIT III WAVELET TRANSFORMS 10 hrs.

UNIT IV PROBABILITY & RANDOM VARIABLES 10 hrs.

UNIT V RANDOM PROCESS 10 hrs.

UNIVERSITY EXAM QUESTION PAPER PATTERN

M.Tech (VLSI DESIGN) 1 REGULATIONS 2010

ADVANCED DIGITAL SYSTEM DESIGN L T P Credits Total Marks

UNIT I SEQUENTIAL LOGIC CIRCUITS 10 hrs.

UNIT II SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 10 hrs.

UNIT III ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 10 hrs.

UNIT IV PROGRAMMABLE LOGIC DEVICES 10 hrs.

UNIT V STUDY OF FPGA AND XILINX 10 hrs.

UNIVERSITY EXAM QUESTION PAPER PATTERN

M.Tech (VLSI DESIGN) 2 REGULATIONS 2010

VLSI DESIGN L T P Credits Total Marks

UNIT III 10 hrs.

UNIVERSITY EXAM QUESTION PAPER PATTERN

M.Tech (VLSI DESIGN) 3 REGULATIONS 2010

MOS DEVICE MODELING L T P Credits Total Marks

UNIT III 10 hrs.

UNIVERSITY EXAM QUESTION PAPER PATTERN

M.Tech (VLSI DESIGN) 4 REGULATIONS 2010

VLSI TECHNOLOGY L T P Credits Total Marks

UNIT I CRYSTAL GROWTH, WAFER PREPARATION, EPITARY AND OXIDATION. 10 hrs.

UNIT II LITHOGRAPHY AND RELATIVE PLASMA ETCHING 10 hrs.

UNIT III DEPOSITION, DIFFUSION , ION IMPLANTATION AND METALIZATION 10 hrs.

UNIT IV METALLIZATION 10 hrs.

UNIT V ANALYTICAL , ASSEMBLY TECHNIQUES & PACKAGING OF VLSI DEVICES 10 hrs.