SMK FOMRA INSTITUTE OF TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNIATION

LAB MANUAL

VLSI DESIGN LAB II

LAB CODE: VL9225 SEM/Branch ME VLSI (II nd SEM)

SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

List of Experiments

Lab code: VL9225 Lab Name: VLSI Design Lab II

1. Implementation of 8 bit ALU in FPGA/CPLD.

2. Implementation of 4 bit sliced processor in FPGA/CPLD.

3. Implementation of elevator controller using embedded

microcontroller.

4. Implementation of alarm clock controller using embedded

microcontroller.

5. Implementation of model train controller using embedded

microcontroller.

6. System design using PLL.

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INDEX

S.No. Name of the Experiment Page no.

1. 8 bit ALU 4-7

2. 4 bit sliced processor 8-11

3. Elevator controller 12-15

4. Alarm clock controller 16-19

5. Model train controller 20-32

6. System design using PLL 33-38

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Exp. No. 1

AIM:
Implementation of 8 bit ALU in FPGA/CPLD.

Software used: XILINX9.1, FPGA kit.

Algorithm:
1. Start.
2. Declare the input and output ports.
3. Perform the calculations and assign the result to output port.
4. Create the test bench waveform.
5. Simulate and verify the output.
6. Stop.
7. Implement of FPGA kit.

Verilog Module:

module alu8(z,read,data,s);
output reg [7:0]z;
input[7:0]data;
input read;
input[1:0]s;
reg[7:0]y[1:0];
integer i;
always@(data or s)
begin
y[read]=data;
case(s)
2'b00:z=y[0]&y[1];
2'b01:z=y[0]|y[1];
2'b10:z=y[0]^y[1];
2'b11:z=y[0]-y[1];
endcase
end
endmodule

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Output waveform

RTL SCHEMATIC

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UCF (user constraint file)

#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "data<0>" LOC = "p74" ;
NET "data<1>" LOC = "p76" ;
NET "data<2>" LOC = "p77" ;
NET "data<3>" LOC = "p79" ;
NET "data<4>" LOC = "p78" ;
NET "data<5>" LOC = "p82" ;
NET "data<6>" LOC = "p80" ;
NET "data<7>" LOC = "p87" ;
NET "read" LOC = "p84" ;
NET "s<0>" LOC = "p85" ;
NET "s<1>" LOC = "p86" ;
NET "z<0>" LOC = "p100" ;
NET "z<1>" LOC = "p102" ;
NET "z<2>" LOC = "p124" ;
NET "z<3>" LOC = "p103" ;
NET "z<4>" LOC = "p105" ;
NET "z<5>" LOC = "p107" ;

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NET "z<6>" LOC = "p108" ;

NET "z<7>" LOC = "p113" ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

Result: 8bit ALU successfully implemented on FPGA kit.

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Exp. No. 2

AIM:
Implementation of 4 bit sliced processor in FPGA/CPLD.

Software used: XILINX9.1, FPGA kit.

Algorithm:
1.Start.
2.Declare the input and output ports.
3.Perform the calculations and assign the result to output port.
4.Create the test bench waveform.
5.Simulate and verify the output.
6.Stop.
7.Implement of FPGA kit.

VHDL Module

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity slicealu is
Port ( aa : in STD_LOGIC_VECTOR (7 downto 0);
ab : in STD_LOGIC_VECTOR (7 downto 0);
c : in STD_LOGIC;
operation : in STD_LOGIC_VECTOR (1 downto 0);
ssum : out STD_LOGIC_VECTOR (15 downto 0));

end slicealu;
architecture arcf_slicealu of slicealu is
component slice1alu is
Port ( aa : in STD_LOGIC_VECTOR (3 downto 0);
ab : in STD_LOGIC_VECTOR (3 downto 0);
c : in STD_LOGIC;
operation : in STD_LOGIC_VECTOR (1 downto 0);
ssum : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component slice2alu is

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Port ( aa : in STD_LOGIC_VECTOR (3 downto 0);

ab : in STD_LOGIC_VECTOR (3 downto 0);
c : in STD_LOGIC;
operation : in STD_LOGIC_VECTOR (1 downto 0);
ssum : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal s:std_logic_vector(7 downto 0):="00000000";
signal s1:std_logic_vector(7 downto 0):="00000000";
signal s2:std_logic_vector(6 downto 0):="0000000";
begin
a2:slice1alu port map(aa(3 downto 0),ab(3 downto 0),c,operation,s(7 downto 0));
a3:slice1alu port map(aa(7 downto 4),ab(7 downto 4),s(4),operation,s1(7 downto 0));
ssum(15 downto 0)<=s2(6 downto 0)&s1(4 downto 0)&s(3 downto 0);
end arcf_slicealu;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity slice1alu is

Port ( aa : in STD_LOGIC_VECTOR (3 downto 0);

ab : in STD_LOGIC_VECTOR (3 downto 0);
c : in STD_LOGIC;
operation : in STD_LOGIC_VECTOR (1 downto 0);
ssum : out STD_LOGIC_VECTOR (7 downto 0));

function addition(A,B:std_logic_vector(3 downto 0);

carry:std_logic)
return std_logic_vector is
variable cout:std_logic;
variable cin:std_logic:=carry;
variable sum:std_logic_vector(7 downto 0):="00000000";
begin
for i in 0 to 3 loop
cout:=(A(i) and B(i)) or (A(i) and cin) or(B(i) and cin);
sum(i):=A(i) xor B(i) xor cin;
cin:=cout;
end loop;

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sum(4):=cout;
return sum;
end;

function subtraction(A,B:std_logic_vector(3 downto 0);

carry:std_logic)
return std_logic_vector is
variable cout:std_logic;
variable cin:std_logic:=carry;
variable sum:std_logic_vector(7 downto 0):="00000000";
begin
for i in 0 to 3 loop
cout:=(not A(i) and B(i)) or (not A(i) and cin) or(B(i) and cin);
sum(i):=A(i) xor B(i) xor cin;
cin:=cout;
end loop;
sum(4):=cout;
return sum;
end;
end;
architecture arch_alu of slice1alu is
begin
ssum<=addition(aa,ab,c)when(operation<="00")
else subtraction(aa,ab,c)when(operation<="01");
end;

OUTPUT WAVEFORM

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RTL SCHEMATIC

Result: 4 bit sliced processor successfully simulated.

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

Exp. No. 3

AIM:
Implementation of elevator controller using embedded microcontroller.

Tools used: Basic Microcontroller kit, Interface Elevator kit VBMB 022

Steps:

1. Connect VBMB022 board to 8051 microcontroller kit.

2. Enter the following program from user RAM address 4100 H.
3. After checking the program, execute the same.
4. We can see the movement of lift 1 from ground floor to 4th floor.

Program:

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ADDRESS OPCODE MNEUMONICS COMMENTS

4100 74 03 Mov a,#03h default open doors

4102 90 FF CC Mov dptr,#stat_ou of lift1 & lift2
4105 F0 Movx @dptr,a
4106 12 41 41 Lcall delay
4109 74 02 Mov a,#02h Close door of lift1
410B F0 Movx @dptr,a
410C 74 80 Mov a,#80h Indicates lift1 is in gnd floor
410E 90 FF C0 Mov dptr,#lift1
4111 F0 Movx @dptr,a
4112 74 01 Mov a,#01h Indicates lift2 is in 7th floor
4114 90 FF C4 Mov dptr,#lift2
4117 F0 Movx @dptr,a
4118 12 41 41 Lcall delay
411B 90 FF C0 Mov dptr,#lift1
411E 74 40 Mov a,#40h
4120 F0 Movx @dptr,a
4121 12 41 41 Lcall delay
4124 74 20 Mov a,#20h
4126 F0 Movx @dptr,a
4127 12 41 41 Lcall delay
412A 74 10 Mov a,#10h
412C F0 Movx @dptr,a
412D 12 41 41 Lcall delay
4130 74 08 Mov a,#08h
4132 F0 Movx @dptr,a
4133 74 0B Mov a,#0bh Beep for door open
4135 90 FF CC Mov dptr,#stat_ou
4138 F0 Movx @dptr,a

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4139 12 41 41 Lcall delay

ADDRESS OPCODE MNEUMONICS COMMENTS

413C 74 03 Mov a,#03h door open

413E F0 Movx @dptr,a
413F Here:
413F 80 FE Sjmp here
4141 Delay:
4141 75 31 0A Mov For 1second delay
count1,#0A
4144 75 30 64 Mov count,#64
4144 Dl2:
4147 12 41 51 Lcall delay 1ms
4147 D2:
414A D5 30 Djnz count,d2
FA
414D D5 31 F4 Djnz count1,dl2
4150 22 Ret
4151 Delay 1ms: 1 millisecond
4151 75 8A 17 Mov t10,#017h TL0=17h, the low byte of timer0
4154 75 8C FC Mov th0,#0FCh TH0=FCh., the high byte of timer0
4157 12 41 5B Lcall t0 delay Activate the timer0 & wait upto
415A 22 Ret Timer overflow occurs
415B T0 delay
415B E5 89 Mov a,tmod
415D 54 F0 Anl a,#0F0h
415F 44 01 Orl a,#t0_ml
4161 F5 89 Mov tmod,a 2 timer0, mode1
4163 D2 8C Setb 8C 1 start the timer0
4165 30 8D Jnb 8D,4165 0FFFF-(16 bit timer value)+1; monitor timer
FD flag 0
4168 C2 8C Clr 8C 1 stop the timer0

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416A C2 8D Clr tf0 8D 1 clear the flag0

416C 22 ret 1 stop the timer0

4165 30 8D FD Jnb 8D,4165 0FFFF-(16 bit timer value)+1; monitor timer flag 0
4168 C2 8C Clr 8C 1 stop the timer0
416A C2 8D Clr tf0 8D 1 clear the flag0
416C 22 ret 1 stop the timer0

Result: Successfully implemented elevator on microcontroller kit.

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

Exp. No. 4

AIM:
Implementation of alarm clock controller using embedded microcontroller.

Tools used: Universal embedded trainer kit

Steps:
1. Open MPLAB IDE on your system.
2. Select device. PIC 16f877A.
3. Select CCS C compiler. Select language tool suite.(CCS C Compiler (ccsc.exe))
4. Create project using project wizard. Chose project>project wizard.
5. Give project name and directory.
6. Create new file and save as (file name.c)
7. Add file to project by right clicking source file.
8. Then Go for compilation. (project>compile F10)
9. Check the output window and simulation. If any error will be there, it will show in
output window.
10. Got to debugger>settings. See the output will come.
11. Open PIC ISP.
12. Select COM port and download file name.hex.GO for download. (While
downloading switch should be in programming mode.)
13. Download successful.
14. After that switch position is changed to exec mode and then reset the CPU code.
Code will be executed.

PROGRAM FOR ALARM CLOCK

//This Program is for Serial Real time Clock with alarm

//SCL - RC3
//SDA - RC4
//DEVICE ADDRESS - 0XA0 - 0XA1

#include <16F877A.H>
#use delay(clock=20000000)
#use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7)
#use I2C(MASTER,sda=PIN_C4,scl=PIN_C3)
unsigned int time[]={0x30,0x55,0x12};
unsigned int readtime[0x03];
unsigned long int hour,second,minute;

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int i,j;

void set_rtc_time()
{
for (i=2;i<=4;i++)
{
i2c_start();
i2c_write(0xa0 | 0x00);
i2c_write(i);
i2c_write(time[(i-2)]);
i2c_stop();
}
}
void get_rtc_time()
{
for (i=2;i<=4;i++)
{
i2c_start();
i2c_write(0xa0);
i2c_write(i);
i2c_start();
i2c_write(0xa0 | 0x01);
readtime[(i-2)]=i2c_read(0);
i2c_stop();
}
}
void alarm_set()
{
output_b(0xff);

if(minute==0x57)
{
if((second>=0x10)&&(second<=0x14))
{
printf("\n");
printf("ALARM SET!!!");

}
}

void main()
{
set_rtc_time();

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while(1)
{
get_rtc_time();
hour = readtime[2];
minute= readtime[1];
second=readtime[0];
printf(" Time : %x : %x : %x \n\r",readtime[2],readtime[1],readtime[0]);
alarm_set();

}
}

OUTPUT

Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09
Time : 12 : 57 : 09

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

Time : 12 : 57 : 09
Time : 12 : 57 : 10

ALARM SET!!! Time : 12 : 57 : 10

ALARM SET!!! Time : 12 : 57 : 10

ALARM SET!!! Time : 12 : 57 : 10

ALARM SET!!! Time : 12 : 57 : 10

ALARM SET!!! Time : 12 : 57 : 10

Result: Successfully implemented model train on embedded microcontroller kit.

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

Exp. No. 5

AIM:
Implementation of model train controller using embedded microcontroller.

Tools used: Universal embedded trainer kit, Model trainer kit.

Steps:
1. Connect Model train kit to PIC.
2. PIC connected to PC.
3. Open MPLAB IDE on your system.
4. Select device. PIC 16f877A.
5. Select CCS C compiler. Select language tool suite. (CCS C Compiler (ccsc.exe))
6. Create project using project wizard. Chose project>project wizard.
7. Give project name and directory.
8. Create new file and save as (file name.c)
9. Add file to project by right clicking source file.
10. Then Go for compilation. (Project>compile F10)
11. Check the output window and simulation. If any error will be there, it will show in
output window.
12. Go to debugger>settings. See the output will come.
13. Open PIC ISP.
14. Select COM port and download file name.hex.GO for download. (While
downloading switch should be in programming mode.)
15. Download successful.
16. After that switch position is changed to exec mode and then reset the CPU code.
Code will be executed.

Program:

This program get the data from the sw1 (up for on, down for off) & sw2 (up for forward,
down for Reverse) and rotate the train. Also get the data from the sensor and put the
signals.

#include <16F877.H>
#include <stdio.h>
#use delay(clock=20000000)
#use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7)
#use I2C(MASTER,sda=PIN_C4,scl=PIN_C3)

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unsigned char data,a,b,c;

unsigned char ls0[]={0x55,0x54,0x50,0x40,0x00,0x00,0x01,0x05,0x15,0x55};
//led0-led3 selector for forward direction.
unsigned char ls1[]={0x55,0x15,0x05,0x01,0x00,0x00,0x40,0x50,0x54,0x55};
//led0-led3 selector for reverse direction.

unsigned char sel[]={0x0c0,0x0c2,0xc4,0xc6,0xc8,0xca,0xcc,0xce,0x0c0};

unsigned char sel1[]={0x0ce,0xcc,0xca,0xc8,0xc6,0xc4,0xc2,0x0c0,0xce};

unsigned char i,i1,j,k=0x15,senout=0x00,senout1=0x00,senout2,senout3,buzzon=0;

void crossingon();
void crossingoff();
void init();
void initbuf();
void sensor();
void sensor1();
void station1forward();
void station2forward();
void station1reverse();
void station2reverse();
void sw();
void sw1();
void reverse();
void forward();

void main()
{
init();
initbuf();

while(1)
{
start1:
for(j=0x00;j<0x09;j++)
{
i1=0x05;
for(i=0x00;i<0x09;i++)
{
start:
if(i<=0x04)
{
i2c_start();
i2c_write(sel[j]); //write the
address for the device selection.

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i2c_write(k); //write the

register address.
i2c_write(ls0[i]); //write the data
for lso register.
i2c_write(ls0[i1]); //write the data
for ls1 register.
i1++;
printf("Rotate one movement here\n");
}
if(j==0x08) //start the next
rotation in the train.
goto start1;
stoptrain:
sw(); //read the data from
the buffer.
// if(c != 0x0) //check for sw1 & sw2 is
high.
// goto stoptrain;

if(i>=0x05)
{
i2c_start();
i2c_write(sel[j]);
i2c_write(k+1);
i2c_write(ls0[i-0x04]);
i2c_stop();
i2c_start();
i2c_write(sel[j+1]);
i2c_write(k);
i2c_write(ls0[i1-0x04]);
i1++;
printf("Rotate one movement here\n");
}
i2c_stop();
stoptrain1:
sw(); //read the data from
the buffer.
// if((c != 0x0)) //check for sw1 & sw2 is
high.
// goto stoptrain1;

sensor();

if(senout == 0x00)
goto stop1;

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senout++;
if(senout < 0x06)
delay_ms(200);
else if(senout == 0x06) //check the
station1.
{
delay_ms(0x2000); //wait some
delay in station1.

initbuf();
output_d(0x10); //glow
the yellow led for station1 in forward.
output_low(PIN_E2);
output_high(PIN_E2);

delay_ms(1000);

initbuf();
output_d(0x08); //glow
the green led for station1 in forward.
output_low(PIN_E2);
output_high(PIN_E2);
delay_ms(100);
}
if((senout > 0x06) && (senout <=0x0a))
delay_ms(200);
stop1:
if(senout1 == 0x00)
goto stop2;

senout1++;
if(senout1 < 0x06)
delay_ms(200);
else if(senout1 == 0x06) //check the
station2.
{
delay_ms(0x2000); //wait some
delay in station2.
initbuf();

output_d(0x04); //glow
the yellow led for station2 in forward.
output_low(PIN_E1);
output_high(PIN_E1);

delay_ms(1000);

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initbuf();
output_d(0x02); //glow
the green led for station2 in forward.
output_low(PIN_E1);
output_high(PIN_E1);
delay_ms(100);
}
if((senout1 > 0x06) && (senout1 <=0x0a))
delay_ms(200);
stop2:
if(i != 0x08)
delay_ms(200);
/* if(buzzon == 0x01)
{
output_low(PIN_E0);
delay_ms(10);
output_high(PIN_E0);
delay_ms(10);
}*/
}
}
}
}

void init()
{
for(i=0;i<0x08;i++)
{
i2c_start();
i2c_write(sel[i]);
i2c_write(0x15);
i2c_write(0x00);
i2c_write(0x00);
i2c_stop();
printf("Clear the display here\n");
}
}

void sensor()
{
output_low(PIN_B4);
a=input_d(); //get the data from the buffer.
output_high(PIN_B4);

b = a;

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b = b & 0x02;
if(b == 0x02) //sensor3 is set to low(enable) for close the
level crossing.
{
do{
output_low(PIN_B4);
a=input_d(); //get the data from the buffer.
output_high(PIN_B4);

c = a;
c = (c & 0x80);
}while(c != 0x0);
crossingon();
}

b = a;
b = b & 0x04;
if(b == 0x04) //sensor4 is set to low(enable) for open the
level crossing.
crossingoff();

b = a;
b = b & 0x08;
if(b == 0x08) //sensor5 is set to low(enable).
station2forward();

b = a;
b = b & 0x20;
if(b == 0x20) //sensor1 is set to low(enable).
station1forward();
}

void crossingon()
{
output_d(0xF0);
output_low(PIN_E1);
output_high(PIN_E1);

output_d(0xFF);
output_low(PIN_E0);
output_high(PIN_E0);

output_d(0x00);
output_low(PIN_E2);
output_high(PIN_E2);

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buzzon = 0x01;
}

void crossingoff()
{
initbuf();
buzzon = 0x0;
}

void station1forward()
{
initbuf();

output_d(0x20); //glow the red led for station1 in

forward.
output_low(PIN_E2);
output_high(PIN_E2);

delay_ms(100); //decrement the speed for stop the

train in station1.

senout=0x01;
}

void station2forward()
{
initbuf();
output_d(0x08); //glow the red led for statio2 in
forward.
output_low(PIN_E1);
output_high(PIN_E1);

delay_ms(100); //decrement the speed for stop the

train in station1.

senout1 = 0x01;
}

void sw()
{
output_low(PIN_B4);
a=input_d(); //get the data from the buffer.
output_high(PIN_B4);

b=a;
b= b & 0x40; //check for switch1.

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c=a;
c= (c & 0x80); //check for switch2.

if(b == 0x40)
reverse();
}

void reverse()
{
senout2 = 0x00, senout3 = 0x00;
init();
initbuf();
buzzon = 0x0;
while(1)
{
start3:
for(j=0x00;j<0x09;j++)
{
i1=0x05;
for(i=0x00;i<0x09;i++)
{
start4:
if(i<=0x04)
{
i2c_start();
i2c_write(sel1[j]); //write the
address for the device selection.
i2c_write(0x06); //write the
register address.
i2c_write(ls1[i]); //write the data
for lso register.

i2c_start();
i2c_write(sel1[j]); //write the
address for the device selection.
i2c_write(0x05); //write
the register address.
i2c_write(ls1[i1]); //write the data
for ls1 register.
i1++;
printf("Rotate one movement here\n");
}
if(j==0x08) //start the next
rotation in the train.
goto start3;

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

stoptrain2:
sw1(); //read the data from
the buffer.
// if(c != 0x0) //check for sw1 & sw2 is
high.
// goto stoptrain2;

if(i>=0x05)
{
i2c_start();
i2c_write(sel1[j]);
i2c_write(0x05);
i2c_write(ls1[i-0x04]);
i2c_stop();
i2c_start();
i2c_write(sel1[j+1]);
i2c_write(0x06);
i2c_write(ls1[i1-0x04]);
i1++;
printf("Rotate one movement here\n");
}
stoptrain3:
sw1(); //read the data from
the buffer.
// if((c != 0x0)) //check for sw1 & sw2 is
high.
// goto stoptrain3;

sensor1();

if(senout2 == 0x00)
goto stop3;

senout2++;
if(senout2 < 0x06)
delay_ms(200);
else if(senout2 == 0x06) //check the station2 in
reverse dircetion.
{
delay_ms(0x2000); //wait some
delay in station2 in reverse dirction.

initbuf();
output_d(0x80); //glow
the yellow led for station2 in reverse.
output_low(PIN_E2);

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

output_high(PIN_E2);

delay_ms(1000);

initbuf();
output_d(0x40); //glow
the green led for station2 in reverse.
output_low(PIN_E2);
output_high(PIN_E2);
delay_ms(100);
}
if((senout2 > 0x06) && (senout2 <=0x0a))
delay_ms(200);

stop3:
if(senout3 == 0x00)
goto stop4;

senout3++;
if(senout3 < 0x06)
delay_ms(200);
else if(senout3 == 0x06) //check the
station1.
{
delay_ms(0x2000); //wait some
delay in station1.

initbuf();
output_d(0x02); //glow
the yellow led for station1 in reverse.
output_low(PIN_E2);
output_high(PIN_E2);

delay_ms(1000);

initbuf();
output_d(0x01); //glow
the green led for station1 in reverse.
output_low(PIN_E2);
output_high(PIN_E2);
delay_ms(100);
}
if((senout3 > 0x06) && (senout3 <=0x0a))
delay_ms(200);
stop4:
if(i != 0x08)

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

delay_ms(200);
/* if(buzzon == 0x01)
{
output_low(PIN_E0);
delay_ms(10);
output_high(PIN_E0);
delay_ms(10);
}*/
}
}
}
}

void sensor1()
{
output_low(PIN_B4);
a=input_d(); //get the data from the buffer.
output_high(PIN_B4);

b = a;
b = b & 0x10;
if(b == 0x10) //sensor6 is set to low(enable).
station2reverse();

b = a;
b = b & 0x04;
if(b == 0x04) //sensor3 is set to low(enable) for close the
level crossing.
{
do{
output_low(PIN_B4);
a=input_d(); //get the data from the buffer.
output_high(PIN_B4);

c = a;
c = (c & 0x80);
}while(c != 0x0);
crossingon();
}

b = a;
b = b & 0x02;
if(b == 0x02) //sensor4 is set to low(enable) for open the
level crossing.
crossingoff();

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

b = a;
b = b & 0x01;
if(b == 0x01) //sensor2 is set to low(enable).
station1reverse();
}

void station1reverse()
{
initbuf();
output_d(0x04); //glow the red led for station1 in
forward.
output_low(PIN_E2);
output_high(PIN_E2);

delay_ms(100); //decrement the speed for stop the

train in station1.

senout3=0x01;
}

void station2reverse()
{
initbuf();
output_d(0x01); //glow the red led for statio2 in
forward.
output_low(PIN_E1);
output_high(PIN_E1);

delay_ms(100); //decrement the speed for stop the

train in station1.

senout2=0x01;
}

void sw1()
{
output_low(PIN_B4);
a=input_d(); //get the data from the buffer.
output_high(PIN_B4);

b=a;
b= b & 0x40; //check for switch1.

c=a;
c= c & 0x80; //check for switch2.
}

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

void initbuf()
{
output_d(0x00); //noy glow the station2 signal.
output_low(PIN_E1);
output_high(PIN_E1);

output_d(0x00); //noy glow the station2 signal.

output_low(PIN_E2);
output_high(PIN_E2);

output_d(0x00); //noy glow the station2 signal.

output_low(PIN_E0);
output_high(PIN_E0);
}

Result: Successfully implemented model train on embedded microcontroller kit.

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

Exp. 6

AIM: System design using PLL.

Software used: XILINX 9.1

Algorithm:
1. Start.
2. Declare the input and output ports.
3. Perform the calculations and assign the result to output port.
4. Create the test bench waveform.
5. Simulate and verify the output.
6. Stop.

Verilog Module
module pll(u1,u2,ID_clock,reset);
input u1,ID_clock,reset;
output u2;
parameter M=32;
parameter K=8;
parameter N=16;
parameter PHASE_DETECTOR_SELECT=1;//1 for xor,2 for JK FF
parameter M2=5;//log base 2 of M
parameter K2=3;//log base 2 of K
parameter N2=4;//log base 2 of N
wire reset,XOR_out,JK_out,DN_UP,K_clock,u2,u2_prime;
reg[(K2-1):0]Kup,Kdn;
reg carry_new,Borrow,Toggle_FF,carry_pulse,Borrow_pulse,advanced,delayed;
reg ID_out,ID_out_2,ID_out_4,ID_out_8,ID_out_16;
reg Borrow_new,toggle_FF,Carry_pulse,Carry_new,Carry;

assign K_clock=ID_clock;

jk jk1 (Q,J,K);

assign XOR_out=u1^u2_prime;
assign DN_UP=PHASE_DETECTOR_SELECT?XOR_out:JK_out;

//*******KCOUNTER*******//

always@(negedge K_clock or negedge reset)

begin
if(!reset)

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

begin
Kup<=0;
Kdn<=0;
Carry<=0;
Borrow<=0;
end
else
begin
if(DN_UP)Kdn<=Kdn+1;
else
begin
if(DN_UP)Kdn<=Kdn+1;
Carry<=Kup[K2-1];
Borrow<=Kdn[K2-1];
end
end
end

///**ID COUNTER****///

always@(posedge ID_clock)
begin
if(!Carry)
begin
Carry_new<=1;
Carry_pulse<=0;
end
else if(Carry_pulse)
begin
Carry_pulse<=0;
Carry_new<=0;
end
else if(Carry && Carry_new)
begin
Carry_pulse<=1;
Carry_new<=0;
end
else
begin
Carry_pulse<=0;
Carry_new<=0;
end
end
//always@(posedge Borrow or posedge ID_clock)
always@(posedge ID_clock)

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

begin
if(!Borrow)
begin
Borrow_new<=1;
Borrow_pulse<=0;
end
else if(Borrow_pulse)
begin
Borrow_pulse<=0;
Borrow_new<=0;
end
else if(Borrow && Borrow_new)
begin
Borrow_pulse<=1;
Borrow_new<=0;
end
else
begin
Borrow_pulse<=0;
Borrow_new<=0;
end
end
always@(posedge ID_clock or negedge reset)
begin
if(!reset)
begin
Toggle_FF<=0;
delayed<=1;
advanced<=1;
end
else
begin
if(Carry_pulse)
begin
advanced<=1;
Toggle_FF<=!Toggle_FF;
end
else if(Borrow_pulse)
begin
delayed<=1;
Toggle_FF<=!Toggle_FF;
end
else if(Toggle_FF==0)
begin
if(!advanced)Toggle_FF<=!toggle_FF;
else if(advanced)

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

begin
Toggle_FF<=Toggle_FF;
advanced<=0;
end
end
else
begin
if(!delayed)Toggle_FF<=!Toggle_FF;
else if(delayed)
begin
Toggle_FF<=Toggle_FF;
delayed<=0;
end
end
end
end

//always@(ID_clock)
always@(ID_clock or Toggle_FF)
begin
if(Toggle_FF)ID_out<=0;
else
begin
if(ID_clock)ID_out<=0;
else ID_out<=1;
end
end
assign u2=ID_out;

///***N COUNTER***///
always@(negedge ID_out or negedge reset)
begin
if(!reset)ID_out_2<=0;
else ID_out_2<=!ID_out_2;
end
always@(negedge ID_out_2 or negedge reset)
begin
if(!reset)ID_out_4<=0;
else ID_out_4<=!ID_out_4;
end
always@(negedge ID_out_4 or negedge reset)
begin
if(!reset)ID_out_8<=0;
else ID_out_8<=!ID_out_8;
end
always@(negedge ID_out_8 or negedge reset)

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

begin
if(!reset)ID_out_16<=0;
else ID_out_16<=!ID_out_16;
end
assign u2_prime=ID_out_8;
endmodule
/////////////////////////

module jk(Q,J,K);
input J,K;
output Q;
reg Q;
always@(posedge J)
begin
if(K==1)
Q<=!Q;
else Q<=1;
end
always@(posedge K)
begin
if(J==1)
Q<=!Q;
else
Q<=0;
end
endmodule

OUTPUT WAVEFORM

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SMK FOMRA INSTITUTE OF TECHNOLOGY, KELAMBAKKAM

RTL SCHEMATIC:

Result: System was designed using PLL.

38