(f5J MOTOROLA

PERIPHERAL INTERFACE ADAPTER (PIA)

The MC6821 Peripheral Interface Adapter provides the universal means of interfacing peripheral equipment to the M6800 family of microprocessors. This device is capable of interfacing the MPU to peripherals through two 8-bit bidirectional peripheral data buses and four control lines. No external logic is required for interfacing to most peripheral devices.

The functional configuration of the PIA is programmed by the MPU during system initialization. Each of the peripheral data lines can be programmed to act as an input or output. and each of the four control/interrupt lines may be programmed for one of several control modes. This allows a high degree of flexibility in the overall operation of .... ~". the interface.

• 8-Bit Bidirectional Data Bus for Communication with the

MPU

• Two Bidirectional 8-Bit Buses for Interface to Peripherals

• Two Programmable Control Registers

• Two Programmable Data Direction Registers

• Four Individually-Controlled Interrupt Input Lines; Two Usable as Peripheral Control Outputs

• Handshake Control Logic for Input and Output Peripheral Operation

• High-Impedance Three-State and Direct Transistor Drive

Peripheral Lines

• Program Controlled Interrupt and Interrupt Disable Capability

• CMOS Drive Capability on Side A Peripheral Lines

• Two TTL Drive Capability on All A and B Side Buffers

• TTL-Compatible

• Static Operation

ORDERING INFORMATION

Frequency
Package Type IMHz) Temperature Order Number
Ceramic 1.0 O°C to 70°C MC6821L
L Suffix 1.0 - 40°C to 8SoC MC6821CL
1.S O°C to 70°C MC68A21L
1.S -40°C to 8SoC MC68A21CL
2.0 O°C to 70°C MC68B21L
Cerdip 1.0 O°C to 70°C MC6821S
S Suffix 1.0 -40°C to 85°C MC6821CS
1.S O°C to 70°C MC68A21S
1.S -40°C to 85°C MC68A21CS
20 o-c to 70°C MC68B21S
Plastic 1.0 o-c to 70°C MC6821P
P Suffix 1.0 - 40°C to 85°C MC6821CP
1.S O°C. to 70°C MC68A21P
1.S -40°C to 85°C MC68A21CP
2.0 o-c to 70°C MC68B21P r

3·307

MC6821

MOS

IN-CHANNEL. SILICON-GATE.

DEPLETION LOAD)

PERIPHERAL INTERFACE ADAPTER

L SUFFIX CERAMIC PACKAGE CASE 715

S SUFFIX CERDIP PACKAGE CASE 734

~PSUF~

2~LASTIC PAC","

CASE 711

PIN ASSIGNMENT
CAl
CA2
PAl IROA
PA2 4 IROB
PA3 RSO
PA4 RSl
PAS 7 RESET
PA6 DO
PA7 01
PBO 02
03
PB2 D4
PB3 OS
PB4 06
PB5 07
PB6 E
PB7 CSl
CBl CS2
CB2 CSO
VCC R/W MC6821

MAXIMUM RATINGS

Characteristics Symbol Value Unit
Supply Voltage VCC -0.3 to +7.0 V
Input Voltage Yin -0.3 to + 7.0 V
Operating Temperature Range TL to TH
MC6821, MC68A21, MC68B21 TA o to 70 °c
MC6821C: MC68A21C -40 to +85
Storage Temperature Range TStg -55 to + 150 °e This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation it is recommended that Yin and Vout be constrained to the range GNDs{Vin or Vout)SVCC·

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).

THERMAL CHARACTERISTICS

Characteristic Symbol Value Unit
Thermal Resistance
Ceramic 8JA 50 °C/W
Plastic 100
Cerdip 60 II

POWER CONSIOERATIONS

The average chip-junction temperature, TJ, in °c can be obtained from:

TJ=TA+(PO·8JA)

Where:

T A. Ambient Temperature, °c

8JA-Package Thermal Resistance, Junction-to-Ambient, °C/W PD-PINT+ PPORT

PINT-ICC x VCC, Watts - Chip Internal Power

PPORTE Port Power Dissipation, Watts - User Determined

For most applications PPORT<C PINT and can be neglected. PPORT may become significant if the device is configured to drive Darlington bases or sink LED loads.

An approximate relationship between PD and T J (if PPORT is neglected) is:

PD=K+(TJ+2730C) (2)

Solving equations 1 and 2 for K gives:

K=PO.(TA+2730C)+8JA.PD2 (3)

Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known T A. Using this value of K the values of PD and T J can be obtained by solving equations (1) and (2) iteratively for any value of T A.

(1 )

OC ELECTRICAL CHARACTERISTICS {VCC=5.0 Vdc ±5%, vSS=O, T A= TL to TH unless otherwise notec).

I Characteristic I Symbol I Min I Typ

Max

Unit

BUS CONTROL INPUTS (R/W, Enable, RESET, RSO, RS1, CSO, CS1, CS2)

Input High Voltage VIH VSS+-Z·O - Vec v
Input Low Voltage VIL VSS-0.3 - VSS+0.8 V
Input Leakage Current IVin = 0 to 5.25 V) lin - 1.0 2.5 ,.A
Capacitance (V'n=O, TA=25"C, f=1.0 MHz) Cin - - 7.5 pF INTERRUPT OUTPUTS IIRQA IROB)

.
Output Low Voltage ULoad-1.6 mAl VOL - - VSS+O.4 V
Hi-Z Output Leakage Current 10Z - 1.0 10 ,.A
Capacitance IVin =0, TA" 25"C, f= 1.0 MHz) Cout - - 5.0 pF DATA BUS ([)()"D7)

Input High Voltage VIH VSS+2.0 - VCC V
Input Low Voltage VIL VSS-0.3 - VSS+O.S V
Hi-Z Input Leakage Current IVin=O.4 to 2.4 V) liZ - 2.0 10 ,.A
Output High Voltage ULoad = - 205 ,.A) VOH VSS+2.4 - - V
Output Low Voltage II Load" 1.6 mAl VOL - - VSS + 0.4 V
Capacitance IVin= 0, T A" 25"C, f .. 1.0 MHz) Cin - - 12.5 pF DC ELECTRICAL CHARACTERISTICS IContinued)

I Characteristic

I Symbol

Min

Typ

Max

Unit

PERIPHERAL BUS (PAO-PA7 PBO-PB7 CAl CAl CBl CB2)

, , , , ,
Input Leakage Current R/W. RESET. RSO. RS1. CSO. CS1. CS2. CAL lin - 1.0 2.5 p.A
(Vin = 0 to 5.25 V) CB1. Enable
Hi-Z Input Leakage Current (Vin= 0.4 to 2.4 V) PBO-PB7.CB2 liZ - 2.0 10 p.A
Input High Current (V,H = 2.4 V) PAO-PA7, CA2 IIH -200 -400 - p.A
Darlington Drive Current (VO = 1.5 V) PBO-PB7, CB2 IOH - 1.0 - -10 mA
Input Low Current (VIL = 0.4 V) PAO-PA7, CA2 IlL - -1.3 -2.4 mA
Output High Voltage
"Load= -2oop.A) PAO-PA7, PBO-PB7, CA2, CB2 VOH VSS+2.4 - - V
"Load = - 10 p.A) PAO-PA7, CA2 VCC-l.0 - -
Output Low Voltage II Load = 3.2 mAl VOL VSS+U.4 v
Capacitance (Vin =0. TA = 25°C, f= 1.0 MHz) Cin - - 10 pF POWER REQUIREMENTS

Internal Power Dissipation (Measured at h = OOC)

I

BUS TIMING CHARACTERISTICS (See Notes 1 and 2)

ldent. Characteristic: Symbol MC6821 MC68A21 MC68B21 Unit
Number Min Max Min I Max Min I Max
1 Cycle Time' tcyc 1.0 10 0.67 10 0.5 10 p's
2 Pulse Width, E Low PWEL 430 - 28) - 210 - ns
3 Pulse Width. E High PWEH 450 - 28) - 220 - ns
4 Clock Rise and Fall Time tr, tf - 25 - 25 - 20 ns
9 Address Hold Time tAH 10 - 10 - 10 - ns
13 Address Setup Time Before E tAS 80 - 60 - 40 - ns
14 Chip Select Setup Time Before E ics 80 - 60 - 40 - ns
15 Chip Select Hold Time tCH 10 - 10 - 10 - ns
18 Read Data Hold Time tOHR 20 50· 20 50· 20 50· ns
21 Write Data Hold Time tDHW 10 - 10 - 10 - ns
30 Output Data Delay Time tDOR - 290 - 180 - 150 ns
31 Input Data Setup Time tDSW 165 - 80 - 60 - ns ·The data bus output buffers are no longer sourcing or sinking current by tDHRmax (High Impedance).

FIGURE 1 - BUS TIMING

E

R/W. Address -....:+:br"XT~r-x"'T-r----....,~-r::i::---+-+----------------+~,._~

(Non-Mux~) +~~~~~~~ ~~~F- +-+ ~ +~~~

Notes:

1. Voltage levels shown are VLsO.4 V. VH~2.4 V. unless otherwise specifi~.

2. Measurement points shown are 0.8 V and 2.0 V. unless otherwise specified.

3·309

MC6821

PERIPHERAL TIMING CHARACTERISTICS (VCC=5.0 V ±50/0. vSS=O V. TA=TL to TH unless otherwise specified)

•

Characteristic Symbol MC6821 MC68A21 MC68B21 Unit Reference
Min Max Min Max Min Max Fig. No.
Data Setup Time tpDS 200 - 135 - 100 - ns 6
Data Hold Time tpDH 0 - 0 - 0 - ns 6
Delay Time. Enable Negative Transition to CA2 Negative Transition tCA2 - 1.0 - 0.670 - 0.500 ,.s 3.7.8
Delay Time. Enable Negative Transition to CA2 Positive Transition TRSl - 1.0 - 0.670 - 0.500 ,.s 3. 7
Rise and Fall Times for CAl and CA2 Input Signals tr• tf - 1.0 - 1.0 - 1.0 ,.s 8
Delay Time from CAl Active Transition to CA2 Positive Transition tRS2 - 2.0 - 1.35 - 1.0 ,.s 3.8
Delay Time. Enable Negative Transition to Data Valid tpDW - 1.0 - 0.670 - 0.5 ,.5 3.9. 10
Delay Time. Enable Negative Transition to CMOS Data Valid tCMOS - 2.0 - 1.35 - 1.0 ,.s 4. 9
PAO-PA7. CA2
Delay Time. Enable Positive Transition to CB2 Negative Transition tCB2 - 1.0 - 0.670 - 0.5 ,.s 3.11.12
Delay Time. Data Valid to CB2 Negative Transition tDC 20 - 20 - 20 - ns 3. 10
Delay Time. Enable Positive Transition to CB2 Positive Transition tRSl - 1.0 - 0.670 - 0.5 ,.s 3.11
Control Output Pulse Width. CA2/CB2 PWCT 500 - 375 - 250 - ns 3.11
Rise and Fall Time for CBl and CB2 Input Signals tr• tf - 1.0 - 1.0 - 1.0 ,. 12
Delay Time. CBl Active Transition to CB2 Positive Transition tRS2 - 2.0 - 1.35 - 1.0 ,.s 3.12
Interrupt Release Time, IRCA and rnLiB t(R - 1.60 - 1.10 - 0.85 ,.s 5,14
Interrupt Response Time tRS3 - 1.0 - 1.0 - 1.0 "s 5,13
Interrupt Input Pulse Time PWI 500 - 500 - 500 - ns 13
RESET Low Time· tRL 1.0 - 0.66 - 0.5 - ,.s 15 "The RESET line must be high a minimum of 1.0 "s before addressing the PIA.

FIGURE 2 - BUS TIMINi3 TEST LOADS

FIGURE 3 - TTL EQUIVALENT TEST LOAD

(PAO-PA7, PBO-PB7, CA2, CB2) 5.0 V

(DO-07)

5.0 V

RL .. 1.25 kO MMD6'SO or EQuiv.

RL=2.4 kO MMD6150 or Equiv.

_II

Test Point 0- ..... _,__-+41--.

VI

C R

C 130 pF

R

11.7 kO

MM07000 or Equiv.

MMD7000 or Equiv.

C=30 pF, R= 12 k

FIGURE 4 - CMOS EQUIVALENT TEST LOAD

FIGURE 5 - NMOS EQUIVALENT TEST LOAD

(iRQOnly)

5.0 V

(PAO-PA7, CA2)

TeuPointl

r"

1.5 kO

Test Point 0-- ....

, oo " I

FIGURE 6 - PERIPHERAL DATA SETUP AND HOLD TIMES (Read Mode)

PAQ·PA7

PBQ·PB7 -'

Enable

FIGURE 8 - CA2 DELAY TIME

(Read Mode; CRA-S=1, CRA-3=CRA-4=0)

FIGURE 10 - PERIPHERAL DATA AND CB2 DELAY TIMES (Write Mode; CRB-5= CRB-3= 1, CRB-4= 0)

Enable

PBQ·PB7

CB:z*

·CB2 goes low as a result of the positive transition of Enable.

FIGURE 12 - CB2 DELAY TIME (Write Mode; CRB-5= 1, CRB-3= CRB-4= 0)

• Assumes part waS deselected during any previous E pulse.

FIGURE 7 - CA2 DELAY TIME (Read Mode; CRA-S= CRA3= 1, CRA-4=O)

Enable

~.,J ~ j ,,",,'

_PWCTY

• Assumes part was deselected during the previous E pulse.

CA2

FIGURE 9 - PERIPHERAL CMOS DATA DELAY TIMES (Write Mode; CRA-S = CRA-3 = 1, CRA-4 = 0)

Enable

I

tCMOS~t--

tpDW .r--- ----vCC -30% VCC

PAO-PA7,

CA2 ~ _

FIGURE 11 - CB2 DELAY TIME (Write Mode; CRB-5= CRB-3= 1, CRB-4= 0)

Enable

CB2

• Assumes part was deselected during the JJrevious E pulse

FIGURE 13 - INTERRUPT PULSE WIDTH AND iRQ RESPONSE

I' PWI

CA1,2

CB 1, 2 __ ~ -"t=- .;;Y"

• Assumes Interrupt Enable Bits are set .

Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

3·311

MC6821

FIGURE 15 - RESET L.OW TIME

FIGURE 14 - IRQ REL.EASE TIME

Enable __ ....J{

7

"The RESET line must be a VIH for a minimum of '.0 JI.S before addressing the PIA.

Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

PIA INTERFACE SIGNALS FOR MPU

The PIA interfaces to the M6800 bus with an 8-bit bidirectional data bus, three chip select lines, two register select lines, two interrupt request lines, a read/write line, an enable line and a reset line. To ensure proper operation with the MC6800, MC6802, or MC6808 microprocessors, VMA should be used as an active part of the address decoding.

Bidirectional Data (00-07) - The bidirectional data lines 100-07) allow the transfer of data between the MPU and the PIA. The data bus output drivers' are three-state devices that remain in the high-impedance loff) state except when the MPU performs a PIA read operation. The read/write line is in the read (high) state when the PIA is selected for a read operation.

Enable (E) - The enable pulse, E, is the only timing signal that is supplied to the PIA. Timing of all other signals is referenced to the leading and trailing edges of the E pulse.

Read/Write (R/W) - This signal is generated by the MPU to control the direction of data transfers on the data bus. A low state on the PIA read/write line enables the input buffers and data is transferred from the MPU to the PIA on the E signal if the device has been selected. A high on the read/write line sets up the PIA for a transfer of data to the bus. The PIA output buffers are enabled when the proper address and the enable pulse E are present.

RESET - The active low RESET line is used to reset all register bits in the PIA to a logical zero (low). This line can be used as a power-on reset and as a master reset during system operation.

Chip Selects (CSO, CS1, and CS2) - These three input Signals are used to select the PIA. CSO and CS 1 must be high and CS2 must be low for selection of the device. Data transfers are then performed under the control of the enable and read/write signals. The chip select lines must be stable

for the duration of the E pulse. The device is deselected when any of the chip selects are in the inactive state.

Register Selects (RSO and RS1) - The two register select lines are used to select the various registers inside the PIA. These two lines are used in conjunction with internal Control Registers to select a particular register that is to be written or read.

The register and chip select lines should be stable for the duration of the E pulse while in the read or write cycle.

Interrupt Request (IRaA and 'iRCiB) - The active low Interrupt Request lines (i'RQA and IROBI act to interrupt the MPU either directly or through interrupt priority circuitry. These lines are "open drain" (no load device on the chip). This permits all interrupt request lines to be tied together in a wire-OR configuration.

Each Interrupt Request line has two internal interrupt flag bits that can cause the Interrupt Request line to go low. Each flag bit is associated with a particular peripheral interrupt line. Also, four interrupt enable bits are provided in the PIA which may be used to inhibit a particular interrupt from a peripheral device.

Servicing an interrupt by the MPU may be accomplished by a software routine that, on a prioritized basis, sequentially reads and tests the two control registers in each PIA for interrupt flag bits that are set.

The interrupt flags are cleared (zeroed) as a result of an MPU Read Peripheral Data Operation of the corresponding data register. After being cleared, the interrupt flag bit cannot be enabled to be set until the PIA is deselected during an E pulse. The E pulse is used to condition the interrupt control lines (CA1, CA2, CB1, CB2). When these lines are used as interrupt inputs, at least one E pulse must occur from the inactive edge to the active edge of the interrupt input signal to condition the edge sense network. If the interrupt flag has been enabled and the edge sense circuit has been properly conditioned, the interrupt flag will be set on the next active transition of the interrupt input pin.

PIA PERIPHERAL INTERFACE LINES

The PIA provides two 8-bit bidirectional data buses and four interrupt/control lines for interfacing to peripheral devices.

Section A Peripheral Data (PAO-PA7) - Each of the peripheral data lines can be programmed to act as an input or output. This is accomplished by setting a "1" in the corresponding Data Direction Register bit for those lines which are to be outputs. A "0" in a bit of the Data Direction Register causes the corresponding peripheral data line to act as an input. During an MPU Read Peripheral Data Operation, the data on peripheral lines programmed to act as inputs appears directly on the corresponding MPU Data Bus lines. In the input mode, the internal pull up resistor on these lines represents a maximum of 1.5 standard TTL loads.

The data in Output Register A will appear on the data lines that are programmed to be outputs. A logical "1" written into the register will cause a "high" on the corresponding data

line while a "0" results in a "low." Data in Output Register A may be read by an MPU "Read Peripheral Data A" operation when the corresponding lines are programmed as outputs. This data will be read properly if the voltage on the peripheral data lines is greater than 2.0 volts for a logic ''1'' output-and less than 0.8 volt for a logic "0" output. Loading the output lines such that the voltage on these lines does not reach full voltage causes the data transferred into the MPU on a Read operation to differ from that contained in the respective bit of Output Register A.

Section B Peripheral Data (PBO-PB7) - The peripheral data lines in the B Section of the PIA can be programmed to act as either inputs or outputs in a similar manner to PADPA7. They have three-state capabiity, allowing them to enter a high-impedance state when the peripheral data line is used as an input. In addition, data on the peripheral data lines

3-313

MC6821

PBO-PB7 will be read properly from those lines programmed as outputs even if the voltages are below 2.0 volts for a "high" or above 0.8 V for a "low". As outputs, these lines are compatible with standard TTL and may also be used as a source of at least 1 milliampere at 1.5 volts to directly drive the base of a transistor switch.

Interrupt Input (CAl and CB11 - Peripheral input lines CA 1 and CB 1 are input only lines that set the interrupt flags of the control registers .. The active transition for these signals is also programmed by the two control registers.

Peripheral Control (CA21 - The peripheral control line CA2 can be programmed to act as an interrupt input or as a

I

peripheral control output. As an output, this line is compatible with standard TTL; as an input the internal pullup resistor on this line represents 1.5 standard TTL loads. The function of this signal line is programmed with Control Register A.

Peripheral Control (CB2) - Peripheral Controt line CB2 may also be programmed to act as an interrupt input or peripheral control output. As an input, this line has high input impedance and is compatible with standard TTL. As an output it is compatible with standard TTL and may also be used as a source of up to 1 milliampere at 1.5 volts to directly drive the base of a transistor switch. This line is programmed by Control Register 8.

INTERNAL CONTROLS

INITIALIZATION

A RESET has the effect of zeroing all PIA registers. This will set PAO-PA7, PBO-PB7, CA2 and C82 as inputs, and all interrupts disabled. The PIA must be configured during the restart program which follows the reset.

There are six locations within the PIA accessible to the MPU data bus: two Peripheral Registers, two Data Direction Registers, and two Control Registers. Selection of these locations is controlled by the RSO and RSl inputs together with bit 2 in the Control Register, as shown in Table 1.

Details of possible configurations of the Data Direction and Control Register are as follows:

TABLE 1 - INTERNAL ADDRESSING

Cont rot
Register Bit
RS' RSO CRA·2 CRB·2 Location Selected
0 0 , X Peripheral Register A
0 0 0 X Data Direction Register A
0 1 X X Contr ot Register A
1 0 X 1 Peripheral Register B
, 0 X 0 Data Direction Register B
, 1 X X Conrrot Register B x • Don't Care

PORT A-B HARDWARE CHARACTERISTICS

As shown in Figure 17, the MC6821 has a pair of I/O ports whose characteristics differ greatly. The A side is designed to drive CMOS logic to normal 30% to 70% levels, and incorporates an internal pullup device that remains connected even in the input mode. Because of this, the A side requires more drive current in the input mode than Port 8. In contrast, the B side uses a normal three-state NMOS buffer which cannot pullup to CMOS levels without external resistors. The B side can drive extra loads such as Dartingtons without problem. When the PIA comes out of reset, the A port represents inputs with pullup resistors, whereas the B side (input mode also) will float high or low, depending upon the load connected to it.

Notice the differences between a Port A and Port Bread operation when in the output mode. When reading Port A, the actual pin is read, whereas the B side read comes from an output latch, ahead of the actual pin.

CONTROL REGISTERS (CRA and CRBI

The two Control Registers (CRA and CRB) allow the MPU to control the operation of the four peripheral control lines CA 1, CA2, CB 1, and CB2. In addition they allow the MPU to enable the interrupt lines and monitor the status of the interrupt flags. Bits 0 through 5 of the two registers may be written or read by the MPU when the proper chip select and register select signals are applied. Bits 6 and 7 of the two registers are read only and are modified by external interrupts occurring on control lines CAl, CA2, CB 1, or CB2. The format of the control words is shown in Figure 18.

DATA DIRECTION ACCESS CONTROL BIT (CRA-2 and CRB-21

Bit 2, in each Control Register (CRA and CRB), determines selection of either a Peripheral Output Register or the corresponding Data Direction E Register when the proper register select Signals are applied to RSO and RS1. A "1" in bit 2 allows access of the Peripheral Interface Register, while a "0" causes the Data Direction Register to be addressed.

Interrupt Flags (CRA-6, CRA-7, CRB-S, and CRB-71 - The four interrupt flag bits are set by active transitions of signals on the four Interrupt and Peripheral Control lines when those lines are programmed to be inputs. These bits cannot be set directly from the MPU Data Bus and are reset indirectly by a Read Peripheral Data Operation on the appropriate section.

Control of CA2 and CB2 Peripheral Control Lines (CRA-3, CRA-4, CRA-5, CRB-3, CRB-4, and CRB-51 - Bits 3, 4, and 5 of the two control registers are used to control the CA2 and C82 Peripheral Control lines. These bits determine if the control lines will be an interrupt input or an output control signal. If bit CRA-5 (CRB-5) is low, CA2 (CB2) is an interrupt input line similar to CAl (CB1)' When CRA-5 (CRB-5) is high, CA2 (CB2) becomes an output signal that may be used to control peripheral data transfers. When in the output mode, CA2 and CB2 have slightly different loading characteristics.

Control of CA 1 and CB 1 Interrupt Input Lines (CRA-O, CRB-O, CRA-1, and CRB-ll - The two lowest-order bits of the control registers are used to control the interrupt input lines CA' and CB 1. Bits CRA-O and CR B-O are used to

enable the MPU interrupt signals IROA and IROB, respectively. Bits CRA-1 and CRB-' determine the active transition of the interrupt input signals CA' and CB 1.

Port A

FIGURE 17 - PORT A AND PORT B EaUIVALENT CIRCUITS

Vcc

Oata-·-... __ Direction (l-Output Pin) (O-lnput Pin)

To External Bus

Read A Data in Input or Output Mode

Port B

Vcc

Internal PIA Bus

I

Read of B Data when in Input Mode

ORDERING INFORMATION

MC68A21C!

Motorola Integrated Circuit =r... T

M6800 Family -------- ..... - Blanks = 1.0 MHz

A= 1.5 MHz

B=2.0 MHz

Device Designation

In M6800 Family

Temperature Range ---------" Blank = 0°_ + 70°C

C= _40°_ +85°C

Package

P= Plastic

5= Cerdip

L=Cera~ic

BETIER PROGRAM

Better program processing is available on all types listed. Add suffix letters to part number.

Levell add "5" Level 2 add "0" Level 3 add "OS"

Levell "5" = 10 Temp Cycles - (- 25 to 150°CI;

Hi Temp testing at T A max.

Level 2 "0" = 168 Hour Burn-in at 125°C Level 3 "OS" = Combination of Levelland 2.

3·315

II

MC6821

Determine Active CA1 (CB1) Transition for Setting Interrupt Flag IROA(B)1 - (bit 7)

bl =0: IRQAIS)l set by high-to-Iow transition on CAl ICS1)

bl = 1: IRQA(S) 1 set by low-to-high transition on CAl (CS1).

L

CA2 ICS2) Control

FIGURE 18 - CONTROL WORD FORMAT

CA1 (CB1) Interrupt Request Enable/Disable

bO= 0: Disables IRQAIS) MPU Interrupt by CAl ICS1) active transition. 1

bO= 1: Enable IRQAIS) MPU Interrupt by CAl (CS1) active transition.

1. IRQA(B) will occur on next (MPU generated) positive transition of bO if CAl (CB1) active transition occurred while interrupt was disabled.

I

b4 I

IRQA(S)2 Flag

b5 I

DDR CAl (CBl)

IROA(B)2 Interrupt Flag (bit 6)

When CA2 (CB2) isan input, IRQA(S) goes high on active transition CA2 ICB2); Automatically cleared by MPU Read of Output Register A(S). May also be cleared by hardware Reset.

CA2 (CS2) Established as Output (b5= 1): IRQAIS) 2=0, not affected by CA2 (CS2) transitions.

IROA(B) 1 Interrupt Flag (bit 7)

Goes high on active transition of CAl ICSll; Automatically cleared by MPU Read of Output Register AISI. May also be cleared by hardware Reset.

I

b3

Control

b7

b6

b2 bl I bO

Control Register IRQAIS)l

Flag

Access

I

Determines Whether Data Direction Register Or Output Register Is Addressed

b2 = 0: Data Direction Register selected. b2= 1: Output Register selected.

I

CA2 (CS2) Established as Output by b5= 1

(Note that operation of CA2 and CS2 output

b5 b4 b3 functions are not identical)

-- '::~CA2

1 0 b3=0: Read Strobe with CA1 Restore

CA2 goes low on first high-to-Iow E transition following an MPU read of Output Register A; returned high by next active CA 1 transition, as specified by bit 1.

b3 = 1: Read Strobe with E Restore

CA2 goes low on first high-to-IOw E transition following an MPU read of Output Register A; returned high by next high-to-Iow E transition during a deselect.

~ CB2

b3 = 0: Write Strobe with CB1 Restora CS2 goes low on first low-te-high E transition following an MPU write into Output Register B; returned high by the next active CB1 transition as specified by bit 1. CR S-b7 must first be cleared by a read of data.

b3 = 1: Write Strobe with E Restore

CS2 goes low on first low-to-high E transition following an MPU write into Output Register B; returned

b5 b4 b3 high by the next low-to-high E tran-

- - L sition following an E pulse which occurred while the part was deselected.

1 1 Set/Reset CA2 (CB2)

CA2 ICS2) goes low as MPU writes b3 = 0 into Control Register.

CA2 (CS2) goes high as MPU writes b3= 1 into Control Register.

___ _ __ _ _ L_

1

CA2 (CB2) Established as Input by b5 = 0

Q§ .Q4 b3

o L_. CA2 (CB2) Interrupt Request Enable/Disable b3=0: Disables IRQA(S) MPU lnterrupt by CA2 ICS2) active transition.·

b3= 1: Enables IRQAIS) MPU Interrupt by CA2 (CS2) active transition.

·'RQA(S) will occur on next (MPU generatted) positive transition of b3 if CA2 (CS2) active transition occurred while interrupt was disabled.

L..--+Determines Active CA2 (CB2) Transition for Setting Interrupt Flag IROA(B)2 - (Bit b6)

b4=0: IRQAIS)2 set by high-to-Iow transition on CA2 (CB21.

b4= 1: IRQAIS)2 set by low-to-high transition on CA2 (CS21.

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