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Experiment 6 Design of SR Latch: Spice Code

The document describes the SPICE code for designing an SR latch circuit. It includes the SPICE code listing the PMOS and NMOS transistors that make up the SR latch, along with definitions for the power supply, inputs, and output nodes. It also briefly mentions including a layout and waveform output from the simulation.

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167 views3 pages

Experiment 6 Design of SR Latch: Spice Code

The document describes the SPICE code for designing an SR latch circuit. It includes the SPICE code listing the PMOS and NMOS transistors that make up the SR latch, along with definitions for the power supply, inputs, and output nodes. It also briefly mentions including a layout and waveform output from the simulation.

Uploaded by

avinash960
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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EXPERIMENT 6

DESIGN OF SR LATCH :

SPICE CODE
.include "D:\sudama\soonu\layout\tspice\models\ml5_20.md"

M1 Vdd qnbar Qn Vdd PMOS L=2u W=6u AD=42p PD=26u AS=18p PS=12u
* M1 DRAIN GATE SOURCE BULK (122 50 124 56)
M2 Gnd qnbar 8 Gnd NMOS L=2u W=6u AD=42p PD=26u AS=18p PS=12u
* M2 DRAIN GATE SOURCE BULK (122 26 124 32)
M3 Qn R Vdd Vdd PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M3 DRAIN GATE SOURCE BULK (114 50 116 56)
M4 qnbar s Vdd Vdd PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M4 DRAIN GATE SOURCE BULK (54 50 56 56)
M5 Vdd Qn qnbar Vdd PMOS L=2u W=6u AD=42p PD=26u AS=18p PS=12u
* M5 DRAIN GATE SOURCE BULK (62 50 64 56)
M6 8 R Qn Gnd NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M6 DRAIN GATE SOURCE BULK (114 26 116 32)
M7 7 s qnbar Gnd NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M7 DRAIN GATE SOURCE BULK (54 26 56 32)
M8 Gnd Qn 7 Gnd NMOS L=2u W=6u AD=42p PD=26u AS=18p PS=12u
* M8 DRAIN GATE SOURCE BULK (62 26 64 32)
vdd vdd gnd dc 5v
.ic v(vqn,gnd)=0
Vs s gnd BIT ({1010})
VR R gnd BIT ({1100})
.tran 10n 100n
.print v(s) v(r) v(qn)
.END
LAYOUT
WAVEFORM OF SR LATCH

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