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VHDL Code For 4 Bit Comparator

This document describes an experiment to design a 4-bit comparator using VHDL. The objective is stated as designing a 4-bit comparator. The apparatus required is listed as the Xilinx ISE 10.1 synthesis and simulation tool. The VHDL program code for the 4-bit comparator is then provided, including the entity, architecture, process, and if/else statements to compare the input bits and determine if the first input is greater than, less than, or equal to the second input.

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22K views2 pages

VHDL Code For 4 Bit Comparator

This document describes an experiment to design a 4-bit comparator using VHDL. The objective is stated as designing a 4-bit comparator. The apparatus required is listed as the Xilinx ISE 10.1 synthesis and simulation tool. The VHDL program code for the 4-bit comparator is then provided, including the entity, architecture, process, and if/else statements to compare the input bits and determine if the first input is greater than, less than, or equal to the second input.

Uploaded by

nady2209
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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EXEPRIMENT NO: - 5

OBJECTIVE: -To Design 4-bit comparator using VHDL.

APPARATUS/TOOL REQUIRED: Xilinx ISE 10.1 synthesis and simulation tool.

PROGRAM:-
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity comp is
Port (a,b:in STD_LOGIC_VECTOR (3 DOWN TO 0);
agb: out STD_LOGIC;
alb:out STD_LOGIC;
aeb:out STD_LOGIC;
End comp;
Architecture arc_comp of comp is
Begin
Process (a,b)
Begin
If a>b then
Agb<=’1’;
Alb<=’0’;
Aeb<=’0’;
Elsif a<b then
Alb<=’1’;
Agb<=’0’;
Aeb<=’0’;
Elsif a=b then
Alb<=’0’;
Agb<=’0’;
Aeb<=’1’;
End if;
End process;
End arch_comp;

1
LOGIC SYMBOL OF DEVICE:-

RTL VIEW:-

WAVE FORM:-

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