1.

LOGIC GATES
---- WAP in VHDL to design all logic gates
-------------------------------1.) OR
GATE-----------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:18:55 02/01/2011
-- Design Name:
-- Module Name: or_gates - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity or_gates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end or_gates;

architecture Behavioral of or_gates is

begin
c <= a or b;

end Behavioral;
RTL SCHEMATIC SYMBOL :-

OUTPUT WAVEFORM :-
2.) AND GATE-------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:29:59 01/25/2011
-- Design Name:
-- Module Name: and_gates - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity and_gates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and_gates;

architecture Behavioral of and_gates is

begin

c <= a and b ;
end Behavioral;
RTL SCHEMATIC SYMBOL :-

OUTPUT WAVEFORM :-
3.) NOT GATE-------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:29:59 01/25/2011
-- Design Name:
-- Module Name: not_gates - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity not_gates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end not_gates;

architecture Behavioral of not_gates is

begin

b <= not a;
end Behavioral;
RTL SCHEMATIC SYMBOL :-

OUTPUT WAVEFORM :-
4.) NAND GATE-------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:29:59 01/25/2011
-- Design Name:
-- Module Name: nand_gates - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity nand_gates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nand_gates;

architecture Behavioral of nand_gates is

begin

b <= not a;
end Behavioral;
RTL SCHEMATIC SYMBOL :-

OUTPUT WAVEFORM :-
5.) NOR GATE-------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:29:59 01/25/2011
-- Design Name:
-- Module Name: nor_gates - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity nor_gates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nor_gates;

architecture Behavioral of nor_gates is

begin

c <= a nor b;
end Behavioral;
RTL SCHEMATIC SYMBOL :-

OUTPUT WAVEFORM:-
6.) XOR GATE-------------------------------------------

-- Company:
-- Engineer:
--
-- Create Date: 14:29:59 01/25/2011
-- Design Name:
-- Module Name: xor_gates - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity xor_gates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xor_gates;

architecture Behavioral of xor_gates is

begin

c <= a xor b;
end Behavioral;
RTL SCHEMATIC SYMBOL :-

OUTPUT WAVEFORM :-
7.) XNOR GATE-------------------------------------------

-- Company:
-- Engineer:
--
-- Create Date: 14:29:59 01/25/2011
-- Design Name:
-- Module Name: xnor_gates - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity xnor_gates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xnor_gates;

architecture Behavioral of xnor_gates is

begin

c <= a xnor b;
end Behavioral;
RTL SCHEMATIC SYMBOL :-

OUTPUT WAVEFORM :-
2.HALF ADDER
W.A.P IN VHDL FOR HALF ADDER-------------------------------------------

-- Company:
-- Engineer:
--
-- Create Date: 14:29:59 01/25/2011
-- Design Name:
-- Module Name: half_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity half_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC;
d : out STD_LOGIC);
end half_adder;

architecture Behavioral of half_adder is

begin

c <= a xor b;
d<= a and b;
end Behavioral;
RTL SCHEMATIC SYMBOL :-

OUTPUT WAVEFORM :-
3.FULL ADDER
W.A.P IN VHDL FOR FULL ADDER-------------------------------------------

-- Company:
-- Engineer:
--
-- Create Date: 14:29:59 01/25/2011
-- Design Name:
-- Module Name: full_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC
s : out STD_LOGIC);
end full_adder;

architecture Behavioral of full_adder is

begin

s <= x xor y xor z;

c <= (x and y) or (y and z) or (z and x)
end Behavioral;
RTL SCHEMATIC SYMBOL:-

OUTPUT WAVEFORM:-
4.HALF ADDER USING STRUCTURAL
-- Company:
-- Engineer:
-- Create Date: 14:19:48 02/09/2011
-- Design Name:
-- Module Name: halfadderstruc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity halfadderstruc is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC;
d : out STD_LOGIC);
end halfadderstruc;

architecture Behavioral of halfadderstruc is

component and_g
port ( l,m : in std_logic;
o:out std_logic);
end component;

component xor_g
port (x,y : in std_logic;
z:out std_logic);
end component;

begin
A1:and_g port map (a,b,c);
A2:xor_g port map (a,b,d);

end Behavioral;
RTL SCHEMATIC SYMBOL :-

OUTPUT WAVEFORM :-
5. FULL ADDER USING STRUCTURAL
-------------------------------------------------------------------------
--------
-- Company:
-- Engineer:
--
-- Create Date: 14:33:38 02/09/2011
-- Design Name:
-- Module Name: fulladderstruc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fulladderstruc is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end fulladderstruc;

architecture Behavioral of fulladderstruc is

component xor_gate
port (l,m : in std_logic;
o : out std_logic);
end component;

component and_gate
port (a,b:in std_logic;
d: out std_logic);
end component;

component or_gate
port (s,t,u: in std_logic;
v:out std_logic);
end component;

signal s1,f1,f2,f3: std_logic;

begin
A1:xor_gate port map(x,y,s1);
A2:xor_gate port map(s1,z,s);
A3:and_gate port map(x,y,f1);
A4:and_gate port map(y,z,f2);
A5:and_gate port map(z,x,f3);
A6:or_gate port map(f1,f2,f3,c);

end Behavioral;
RTL SCHEMATIC SYMBOL:-

OUTPUT WAVEFORM:-
6.HALF SUBTRACTOR USING BEHAVIOURAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 13:20:34 02/15/2011
-- Design Name:
-- Module Name: half_subtractor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity half_subtractor is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC;
d : out STD_LOGIC);
end half_subtractor;

architecture Behavioral of half_subtractor is

begin

c<= a xor b;
d<=not a and b;
end Behavioral;
RTL SCHEMATIC SYMBOL:-

OUTPUT WAVEFORM:-
7.HALF SUBTRACTOR USING STRUCTURAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 13:36:15 02/15/2011
-- Design Name:
-- Module Name: halfsubtracstruc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity halfsubtracstruc is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
diff : out STD_LOGIC;
borrow : out STD_LOGIC);
end halfsubtracstruc;

architecture Behavioral of halfsubtracstruc is

component xor_gate
port (l,m : in std_logic;
o : out std_logic);
end component;

component and_gate
port (x,y : in std_logic;
z:out std_logic);
end component;
component not_gate
port (s : in std_logic;
t:out std_logic);
end component;
signal s1:std_logic;

begin

A1: xor_gate port map(a,b,diff);

A2: not_gate port map(a,s1);
A3: and_gate port map(b,s1,borrow);
end Behavioral;
RTL SCHEMATIC VIEW:-

OUTPUT WAVEFORM:-
8.FULL SUBTRACTOR USING BEHAVIORAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 14:27:10 02/15/2011
-- Design Name:
-- Module Name: fullsubtrac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fullsubtrac is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
diff : out STD_LOGIC;
borrow : out STD_LOGIC);
end fullsubtrac;

architecture Behavioral of fullsubtrac is

begin

diff<=a xor b xor c;

borrow<=(a and b) or ((not c)and (b xor a));

end Behavioral;
RTL SCHEMATIC SYMBOL:-

OUTPUT WAVEFORM:-
9.FULL SUBTRACTOR USING STRUCTURAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 14:36:44 02/15/2011
-- Design Name:
-- Module Name: fullstrucsub - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fullstrucsub is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
diff : out STD_LOGIC;
borrow : out STD_LOGIC);
end fullstrucsub;

architecture Behavioral of fullstrucsub is

component xor1_gate
port(l,m,n: in std_logic;
o:out std_logic);
end component;

component xor_gate
port(g,h: in std_logic;
i:out std_logic);
end component;

component and_gate
port (x,y : in std_logic;
z:out std_logic);
end component;

component or_gate
port (s,t : in std_logic;
u: out std_logic);
end component;

component not_gate
port(p :in std_logic;
q: out std_logic);
end component;

signal s1,s2,s3,f1: std_logic;

begin
A1:xor1_gate port map(a,b,c,diff);
A2:xor_gate port map(a,b,s3);
A3:and_gate port map (a,b,s1);
A4:not_gate port map(c,s2);
A5:and_gate port map (s2,s3,f1);
A6:or_gate port map(s1,f1,borrow);

end Behavioral;
RTL SCHEMATIC SYMBOL:-

OUTPUT WAVEFORM:-
10.MULTIPLEXER USING BEHAVIORAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 13:24:18 02/22/2011
-- Design Name:
-- Module Name: mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);
end mux;

architecture Behavioral of mux is

begin
process(s)
begin

case s is
when "00"=> y <=I(0);
when "01"=> y <=I(1);
when "10"=> y <=I(2);
when others => y <=I(3);
end case;
end process;
end Behavioral;
RTL SCHEMATIC SYMBOL:-

OUTPUT WAVEFORM:-
 11.DEMUX USING BEHAVIORAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 13:52:50 02/22/2011
-- Design Name:
-- Module Name: demux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity demux is
Port ( i : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end demux;

architecture Behavioral of demux is

begin
process(s)
begin
case s is

when "00" => y <= "0001";

when "01" => y <= "0010";
when "10" => y <="0100";
when others => y <= "1000";
end case;
end process;
end Behavioral;
RTL SCHEMATIC:-

OUTPUT WAVEFORM:-
 12.MUX USING STRUCTURAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 15:04:34 02/22/2011
-- Design Name:
-- Module Name: muxstruc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity muxstruc is
Port ( i : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);
end muxstruc;

architecture Behavioral of muxstruc is

component and_g
port ( l,m,n : in std_logic;
o:out std_logic);
end component;

component or_gate
port (q,t,u,v: in std_logic;
w:out std_logic);
end component;
component not_g
port (a:in std_logic;
b: out std_logic);
end component;

signal f1,f2,f3,f4,f5,f6: std_logic;

begin

A1:not_g port map(s(1),f1);

A2:not_g port map(s(0),f2);
A3:and_g port map(i(0),f1,f2,f3);
A4:and_g port map(i(1),f1,s(0),f4);
A5:and_g port map(i(2),s(1),f2,f5);
A6:and_g port map(i(3),s(1),s(0),f6);
A7:or_gate port map (f3,f4,f5,f6,y);

end Behavioral;
RTL SCHEMATIC SYMBOL:-

OUTPUT WAVEFORM:-
 13.DEMUX USING STRUCTURAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 15:24:56 02/22/2011
-- Design Name:
-- Module Name: demuxstruct - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity demuxstruct is
Port ( d : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (1 downto 0);
i : out STD_LOGIC_VECTOR (3 downto 0));
end demuxstruct;

architecture Behavioral of demuxstruct is

component notg
port (t: in std_logic; u:out std_logic);
end component;

component andg
port (a,b,c: in std_logic; e:out std_logic);
end component;

signal f1,f2: std_logic;

begin
a1: notg port map (s(0),f1);
a2: notg port map (s(1),f2);
a3: andg port map (d,f1,f2,i(0));
a4: andg port map (d,f1,s(1),i(1));
a5: andg port map (d,s(0),f2,i(2));
a6: andg port map (d,s(0),s(1),i(3));

end Behavioral;
14.ENCODER USING BEHAVIORAL
----------------------------------------------------------------------------------

-- Company:
-- Engineer:
--
-- Create Date: 13:36:29 03/22/2011
-- Design Name:
-- Module Name: encoder1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity encoder83 is
Port ( sel : in STD_LOGIC_VECTOR (07 downto 00);
code : out STD_LOGIC_VECTOR (02 downto 00));
end encoder83;

architecture Behavioral of encoder83 is

begin
code<="000" when sel(0)='1' else
"001" when sel(1)='1' else
"010" when sel(2)='1' else
"011" when sel(3)='1' else
"100" when sel(4)='1' else
"101" when sel(5)='1' else
"110" when sel(6)='1' else
"111" when sel(7)='1' else
"---";
end Behavioral;
RTL VIEW OF ENCODER
TESTBENCH:-

SIMULATION:-
15.DECODER USING BEHAVIORAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 14:06:18 03/22/2011
-- Design Name:
-- Module Name: decoder1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder1 is
Port ( a : in STD_LOGIC_VECTOR (02 downto 0);
y : out STD_LOGIC_VECTOR (07 downto 0));
end decoder1;

architecture Behavioral of decoder1 is

begin
y<= "00000001" when a="000" else
"00000010" when a="001" else
"00000100" when a="010" else
"00001000" when a="011" else
"00010000" when a="100" else
"00100000" when a="101" else
"01000000" when a="110" else
"10000000" when a="111" else
"00000000";

end Behavioral;
RTL VIEW OF DECODER
TESTBENCH:-

SIMULATION:-
16.ENCODER USING STRUCTURAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 14:27:41 03/22/2011
-- Design Name:
-- Module Name: encoderstruc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity encoderstruc is
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0);
en: in std_logic);
end encoderstruc;

architecture structural of encoderstruc is

component or_gate
port (a,b,c,d,e: in std_logic;
f:out std_logic);
end component;

begin

a1:or_gate port map (i(4),i(5),i(6),i(7),en,y(0));

a2:or_gate port map (i(2),i(3),i(6),i(7),en,y(1));
a3:or_gate port map (i(1),i(3),i(5),i(7),en,y(2));
end structural;
RTL VIEW OF ENCODER
SIMULATION:-
17.DECODER USING STRUCTURAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 14:49:53 03/22/2011
-- Design Name:
-- Module Name: decoderstruc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoderstruc is
Port ( y : in STD_LOGIC_VECTOR (2 downto 0);
i : out STD_LOGIC_VECTOR (7 downto 0);
en : in STD_LOGIC);
end decoderstruc;

architecture Behavioral of decoderstruc is

component not_gate
port (a:in std_logic;
b: out std_logic);
end component;

component and_gate
port (c,d,e,f:in std_logic;
g: out std_logic);
end component;

signal f1,f2,f3: std_logic;

begin
A1:not_gate port map(y(2),f1);
A2:not_gate port map(y(1),f2);
A3:not_gate port map(y(0),f3);
A4:and_gate port map(y(2),y(1),y(0),en,i(0));
A5:and_gate port map(y(2),y(1),f3,en,i(1));
A6:and_gate port map(y(2),f2,y(0),en,i(2));
A7:and_gate port map(y(2),f2,f3,en,i(3));
A8:and_gate port map(f1,y(1),y(0),en,i(4));
A9:and_gate port map(f1,y(1),f3,en,i(5));
A10:and_gate port map(f1,f2,y(0),en,i(6));
A11:and_gate port map(f1,f2,f3,en,i(7));

end Behavioral;
RTL VIEW OF DECODER:-
TESTBENCH:-

SIMULATION:-
18.BINARY TO GRAY CODE CONVERTER
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 13:43:32 03/29/2011
-- Design Name:
-- Module Name: binarytogrey - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity binarytogrey is
Port ( b : in STD_LOGIC_VECTOR (2 downto 0);
g : out STD_LOGIC_VECTOR (2 downto 0));
end binarytogrey;

architecture Behavioral of binarytogrey is

begin
g(2)<=b(2);
g(1)<=b(1) xor b(2);
g(0)<=b(0) xor b(1);

end Behavioral;
RTL VIEW OF BINARY TO GRAY CONVERTER
TESTBENCH:-

SIMULATION:-
19.BINARY TO GRAY CODE CONVERTER USING STRUCTURAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 14:05:51 03/29/2011
-- Design Name:
-- Module Name: bin_grey_struc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bin_grey_struc is
Port ( b : in STD_LOGIC_VECTOR (2 downto 0);
g : out STD_LOGIC_VECTOR (2 downto 0));
end bin_grey_struc;

architecture Behavioral of bin_grey_struc is

component xor_gate
port (a,b:in std_logic;
c: out std_logic);
end component;

component ab
port (c:in std_logic;
d: out std_logic);
end component;
begin

A1:xor_gate port map(b(1),b(0),g(0));

A2:xor_gate port map(b(1),b(2),g(1));
A3:ab port map (b(2),g(2));
end Behavioral;
RTL VIEW OF BINARY TO GRAY CONVERTER
TESTBENCH:-

SIMULATION:-
20.ONE BIT COMPARATOR
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 14:29:59 03/29/2011
-- Design Name:
-- Module Name: comparator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity comparator is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
agb : out STD_LOGIC;
aeb : out STD_LOGIC;
alb : out STD_LOGIC);
end comparator;

architecture Behavioral of comparator is

begin
process (a,b)

begin
if(a>b) then
agb<='1';
aeb<='0';
alb<='0';
else if(a=b) then
agb<='0';
aeb<='1';
alb<='0';
else if(a<b) then
agb<='0';
aeb<='0';
alb<='1';
end if;
end if;
end if;
end process;

end Behavioral;
RTL VIEW OF 1-BIT COMPARATOR
TESTBENCH:-

SIMULATION:-
21.ONE BIT COMPARATOR USING STRUCTURAL
-------------------------------------------------------------------------
---------
-- Company:
-- Engineer:
--
-- Create Date: 14:43:35 03/29/2011
-- Design Name:
-- Module Name: comparator_grey - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------
---------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity comparator_grey is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
agb : out STD_LOGIC;
aeb : out STD_LOGIC;
alb : out STD_LOGIC);
end comparator_grey;

architecture Behavioral of comparator_grey is

component not_gate
port (a:in std_logic;
b: out std_logic);
end component;

component and_gate
port (c,d:in std_logic;
e: out std_logic);
end component;
component xor_gate
port (f,g:in std_logic;
h: out std_logic);
end component;

signal f1,f2: std_logic;

begin
A1:not_gate port map (a,f1);
A2:not_gate port map (b,f2);
A3:and_gate port map (f1,b,alb);
A4:and_gate port map (f2,a,agb);
A5:xor_gate port map (a,b,aeb);

end Behavioral;
RTL VIEW OF 1-BIT COMPARATOR
TESTBENCH:-

SIMULATION:-