Interrupts, Part 1 Dr. Dimitrios S. Nikolopoulos Csl/Uiuc
Interrupts, Part 1 Dr. Dimitrios S. Nikolopoulos Csl/Uiuc
Interrupts, Part 1
Dr. Dimitrios S. Nikolopoulos
CSL/UIUC
Outline
ECE291 Lecture 9 2
Why are interrupts important
ECE291 Lecture 9 3
Interrupts from a pedagogical perspective
ECE291 Lecture 9 4
Interrupts and our everyday lives
ECE291 Lecture 9 5
Interrupts…seriously defined
ECE291 Lecture 9 6
Interrupt vectors
ECE291 Lecture 9 8
The INT and IRET instructions
ECE291 Lecture 9 9
Things to notice
ECE291 Lecture 9 10
Hardware interrupts
INTR
INTA 80x86
INT#
ECE291 Lecture 9 14
Master-Slave Configuration
0 IRQ8
Base vector is 08h 1 IRQ9
Slave 2 IRQ10
0 IRQ0 8259 3 IRQ11
1 IRQ1 4 IRQ12
Master 2 INTR 5 IRQ13
8259 3 IRQ3 6 IRQ14
80x86 4 IRQ4 7 IRQ15
INTR 5 IRQ5
6 IRQ6 Base vector is 78h
7 IRQ7
ECE291 Lecture 9 15
The 8259 PIC
ECE291 Lecture 9 16
The 8259 PIC
ECE291 Lecture 9 18
The 8259 PIC
• IRQ mapping
– Interrupt vectors 8 through 0Fh map to IRQ0-IRQ7
– Interrupt vectores 70h-77h map to IRQ8-IRQ15
ECE291 Lecture 9 19
Interrupt vectors and the 8259 PIC
0 IRQ8
Base vector is 08h 1 IRQ9
Slave 2 IRQ10
0 IRQ0 8259 3 IRQ11
1 IRQ1 4 IRQ12
Master 2 INTR 5 IRQ13
8259 3 IRQ3 6 IRQ14
80x86 4 IRQ4 7 IRQ15
INTR 5 IRQ5
6 IRQ6 Base vector is 78h
7 IRQ7
ECE291 Lecture 9 20
Typical IRQ assignments
ECE291 Lecture 9 22
Priority in the 8259
ECE291 Lecture 9 23
Interrupt enabling/disabling
ECE291 Lecture 9 24
The ugly details
• ISRs for hardware interrupts clear the interrupt flag at the beginning to
disable interrupts. They may include a STI instruction if they want to
enable interrupts before they finish
– It’s all about performance! Keeping interrupts blocked for long is a BAD
IDEA
• ISRs for software interrupts do not disallow hardware interrupts
automatically at the beginning. If an ISR for a software interrupt needs
to do that it must issue a CLI instruction
– This is what most ISRs do
– Again for the sake of performance a STI instruction must be issued as soon
as possible
– Note that when interrupts are enabled the priority rule applies
• The CLI works only for maskable hardware interrupts
• Code enclosed between CLI/SCI is often called a critical section, an
uninterruptible piece of code
ECE291 Lecture 9 25
Is there a way out of this mess ?
ECE291 Lecture 9 26
Servicing a hardware interrupt
• Complete current instruction • Execute ISR
– usually the handler immediately
• Preserve current context re-enables the interrupt system
– PUSHF Store flags to stack (to allow higher priority
– Clear Trap Flag (TF) & Interrupt interrupts to occur) (STI
Flag (IF) instruction)
– Store return address to stack – process the interrupt
PUSH CS, PUSH IP • Indicate End-Of-Interrupt (EOI)
• Identify Source to 8259 PIC
– Read 8259 PIC status register mov al, 20h
– Determine which device (N) out 20h, al
triggered the interrupt
• Return (IRET)
• Activate ISR – POP IP (Far Return)
– Use N to index vector table – POP CS
– Read CS/IP from table – POPF (Restore Flags)
– Jump to instruction
ECE291 Lecture 9 27
Interrupt service routines
ECE291 Lecture 9 28
Impact of interrupts on performance
ECE291 Lecture 9 31
Interrupt Driven I/O
• Consider an I/O operation, where the CPU constantly tests a port (e.g.,
keyboard) to see if data is available
– CPU polls the port if it has data available or can accept data
• Polled I/O is inherently inefficient
• Wastes CPU cycles until event occurs
• Analogy: Checking your watch every 30 seconds until your popcorn is
done, or standing at the door until someone comes by
ECE291 Lecture 9 32