Design Methodology of CMOS Low Power

Hao Dongyan, Zhang Ming, Zheng Wei

College of Information Science and Engineering, Zhejiang University, Hangzhou
auronahdy(163 com, zhangmgzimeducn, Zhengwgisee.ziueducn

Abstract-The growing demand for portable electronic

devices has led to an increased emphasis on power
and P,,ekage is the leakage power. The most significant

consumption within the IC design industry. In this article,

according the design flow of VLSI, we present a survey of
component is pwithig
switching'
but p~short-circuul is also important

low power design methodology at fi've levels such as system, and fleakage will become more important because the low
behavioral, architectural, logic and physical levels.
threshold voltages are being proposed for future low-power
technologies.
I. INTRODUCTION Switching power for a CMOS circuit can be modeled by the
following equation:
The growing market of mobile, battery-powered electronic
N
systems demands the design of microelectronic circuits with (2)
Pswiching = VDD X fclk X E aiCLiA Vi
low power dissipation. Several years ago, circuit designers i=l
focused their concentration on density, size and complexity of
Where VDD is the power supply voltage, fe/k is the
the chips. The rapid development of very large-scale
frequency clock. If a circuit contains n nodes, 6?i is the
integrated circuits (VLSI) has resulted in the increasing power
average number of transitions per second, CL, is the load
consumption becoming a major concern of the electronic
industry. capacitance, and AJVi is the voltage swing at node i
In the past ten years, several techniques, methodologies and
Short circuit power is due to the finite rise time and fall time
tools for designing low power have been presented in specific
literatures, the purpose of this article is to discuss the main of the input signals, when the input signal is between IV and
design strategies of CMOS low power at the system,
behavioral, architectural (i.e. RTL), logic and physical levels. (VDD - V P, where IvT, is the threshold voltage of NMOS, and
II. POWER DISSIPATION IVT,I is the threshold voltage of PMOS, both the NMOS and
CMOS is, by far, the most common technology used for
PMOS are turned on, and there is a short circuit current
manufacturing digital ICs. There are three sources of power
flowing from the VDDto ground. Short circuit power can be
dissipation in a CMOS circuit[1],[2]:
expressed as:
'total Pswithing + Pshort-circuit + Pleakage (1)
Pshort - circuit VDD I short - circuit (3)
Where Ptotal is the total power dissipation of a CMOS
Where the 'short-circuit is the short circuit current. The
circuit,IPwithing is the switching power, which is due to the short circuit power can be kept less than 15% of the switching
power with careful design.
charging and discharging capacitors driven by the
circuits. ph,,t-,ircit is the short circuit power, The leakage power can be expressed as:

'leakage VDDIleakage (4)

0-7803-9484-4/05/$20.00 ©2005 IEEE 114

 choose the right algorithm for a given function[5]. In practice,
Where I'eakge is the total leakage current in a CMOS
this means rewriting the algorithm in order to reduce the
circuit. Leakage power mainly originates from substrate number of times that certain functional operations are
injection and sub-threshold effects. For deep-submicron performed. The operations chosen should be those that are
processes, it becomes more important. known to require a lot of energy per computation. According
In the rest of this paper, we will discuss design strategies of to the equation (2), reducing switching activity is an effective
reducing power dissipation at system, algorithm, architectural method to reduce power consumption, especially for those
(i.e. RTL), logic and physical levels. signal lines whose node capacitances are large, such as bus.
We adopt proper coding profile to minimize the switching
III. Low POWER DESIGN METHODOLOGY activity. Gray-code is a good choice for only one bit changes
A. System Level in two adjacent coding words. The switching activity of bus
can be reduced greatly. And finally, another method is to
Actually, addressing the power problem should be done at
reduce switching capacitance, one should fully consider the
very early stages of design flow, which will help us to reduce
operation numbers and types. For instance, power dissipation
the power budget significantly and to avoid costly redesign
of multiplication operation is larger than that of addition
steps. Therefore, designing low power at system level will be
operation. Hence, the number of operations accessing
efficient and practical[3].
memories and ALU should be as small as possible.
The key principle of power management is to design and
distinguish different working mode of CPU. The unnecessary C. Architectural Level
energy waste of normal mode or idle mode will be avoided. This level, also called the Register Transfer Level (RTL), the
Power management includes two parts: dynamic and static. main design technologies are parallel structure and pipeline
Dynamic power management is for normal mode. When a structure.
command is performed, the activity priority of different 1) Parallel Structure
modules in a circuit is different, some will be invoked while When an application has parallelism, one can build
others will not. The task of dynamic power management is to N ( N . 2) functional units instead of one, and solve
selectively hang the modules that are not invoked. The power N problems at the same time[4],[6]. Thus clock frequency can
can be reduced effectively. For example, when we do integer be cut down to 1/N, the speed of each functional unit can be
operation, the float operation which is in idle mode will not be reduced to 1/N. Due to the linear relationship between delay
invoked, therefore it will be hung to reduce the power. and voltage, the supply voltage can also be reduced to 1/N.
Correspondingly, static power management is for idle mode, it Figure 1 give an example of parallel design. (a) represents the
will detect the working mode of the whole system instead of original module whose power is:
certain sections of processor. Typically, if the system doesn't
work for a period, it will be hung and the clock will be turned Puni = cv 2f (5)
off to the whole system. There is no power consumption.
Vividly, we also call this mode sleep mode. While asleep, the
processor doesn't work. A wake-up event wakes the processor
from sleep mode[4], processors may require different amounts
of time to wake up from different sleep mode. It is only
profitable to go into deep sleep mode when the processor is
expected to sleep for a relatively long time. VoltageV

B. Behavioral Level (a)

0C4it--22C f2
VoltageO.6V
FreqL==O 5f (b)
At this higher design level, an obvious approach is to
Fig. 1. Parallel processing structure

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 The parallel design is presented in (b), the capacitance
becomes 2.2 C due to a "copy " of original unit and a MUX Begin d

are added . Clock frequency of each module becomes f /2,

correspondingly, voltage will become 60% of original voltage. (a) Original structure
Thus, the power can be re-expressed as:

Pparallel = 2.2C(0.6V) (0.5f) = 0.4Punit (6)

Through the comparison of equations (5) and (6), the

reduction of power consumption can indeed be obtained by (b) Pipeline structure
applying parallel structure. Unfortunately, this method will Fig. 2. Pipeline structure of low power microprocessor
also bring some shortcomings, such as increase of chip area, instruction, pipeline hazards will happen which is not
increase of capacitance and the degradation of delay. Owing expected in our design.
to the influences of these factors, we will give it careful The application of parallel structure and pipeline structure
consideration and make tradeoff between them to achieve is broad, especially for digital signal processing chips, for they
optimization of parallel design. need stronger data processing abilities and simple circuit
2) Pipeline Structure control units.
Another technique is pipeline design, the main idea of D. Logic Level
which is to control the instruction flow in the data path and to
Logic level low power design has been intensively studied
obtain the maximum throughput (i.e. the number of
in recent years. During the logic optimization, technology
instructions processed per second), and to improve the
parameters such as supply voltage are invariable, and the
performance of the circuit. Figure 2 shows us a pipeline
degrees of freedom are in selecting the function and sizing the
design flow of CPU[7].CPU divides the operations into five
gates implementing a given logic specification. There are
modules, each of which is in charge of an operation. A
several logic level power minimization techniques, path
register is inserted between two neighbouring modules to
equalization, re-factoring, re-mapping, phase assignment and
drive the module. This method is similar to dividing an
pin swapping [8], etc. Three typical methods at logic level are
algorithm A into n sub-algorithm A / n If the clock
listed below.
frequency f is changeless, the number of each module's
1) Logical Optimization Design Technology
operations is just Aln which can result in reduction of
The aim of logical optimization design is to decrease node
voltage by a factor of n (the need for circuit speed is I/ n ).
transition factor air. By decomposing logical function of
The capacitance will keep unaltered, supposing the registers
circuits, the transition activities can be reduced to minimum.
are ignored. Thus, the power can be reduced by a factor of n,
Then the nodes with high transition activities will be hided in
and area of chip will nearly not be increased.
the complex gates to reduce their equivalent capacitance.
Compared with parallel structure, the pipeline structure
Figure 3 shows us the processing of logical optimization
gains the same power benefits but not need to expand the chip
design. Logical function is realized by some simple gates in
areas. But it also has some limits: First, the pipeline design is
(a), the nodes with high transition activities are hided in (b).
more complex than the parallel design. The registers inserted
This method can reduce the power dissipation by 20% without
in the pipeline structure not only consume areas but also need
influence on the performance of circuits.
extra clock which will bring extra power dissipation. Second,
2) Precomputation Design Technology
pipeline is not appropriate for all algorithms, some of which
The precomputation [9] method adds a simple
may meet pipeline hazards. In ideal condition, neighbouring
combinational circuit, which is the precomputation logic to the
instructions are independent. If the data in the last instruction
original circuit. The basic idea is to selectively precompute the
doesn't refreshed in time and are invoked by the current
output logic values of the circuits one clock circle before they

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 a High switching activity node E. Physical level
1) SOI Design Technology
b SOI technology has played an important role in the low
C
voltage and low power design [1]. At low supply voltage, this
d- d- technology improves the performance and reduces cost.
(a) (b) Thanks to its good performance, film SOI CMOS technics can
be applied in deep sub-micrometer VLSI widely. SOI devices
Fig. 3. Logic optimization (a) Original function units
adopt insulated dielectric as isolation and present better
(b) Minimum power design
capability than common CMOS devices: non-self latch up,
are required, and then use the precomputed values to reduce
high integration, low parasitic capacitance and ideal
internal switching activities by stopping certain units in the
sub-threshold leakage current. In SOI devices, the capacitance
circuit in the succeeding clock cycle. This reduces the
can be reduced by 300 . Combined with low supply voltage,
capacitance and transition factor.
power dissipation will be reduced greatly.
3) Multi-threshold Voltage Design Technology
2) Layout Design Optimization
Recently, as the development of chip integration and
Parasitic capacitance and flip-flops are two main factors to
reduction of supply voltage, the design of multi-threshold
be considered, low power can be realized by arranging the
voltage logic circuit has become more and more important.
connections at different levels reasonably[1]. There are three
There are two key points in this strategy: One is to reduce the
strategies: (i) Those nodes with high activity frequency should
power consumption by reducing the internal voltage swing,
be allocated on low capacitance levels, such as the second
the other is effectively controlling the increase of leakage
metal layer and higher levels. (ii) The interconnections
current, which is caused by reduction of supply voltage and
between nodes with high frequency should be as short as
threshold voltage.
possible.(iii) High capacitance nodes and bus should be put on
There are three different types of inverters which adopt
low capacitance levels.(iv) Large scale devices should adopt
multi-threshold voltage technology. The output logical voltage
pectination structure and annularity structure to reduce drain
swings are different but all smaller than the voltage swing of
capacitance.
common circuits. In figure 4, the voltage swing of (a) is from
0 to (vD -| |), the voltage swing of (b) is from VT| to VDD IV. CONCLUSION
In conclusion, supply voltage, capacitance, switching
The voltage swing of (c) is from VT| to (VDD- | Obviously, activity and frequency are key factors of low power design
flow. Low power techniques are needed at all levels of VLSI
the voltage swing of third structure is the minimum , thus its
designs, but can perhaps have more impact if applied at a high
power dissipation is the lowest.
level of abstraction. The higher the design level is, the larger
VDD VDD VDD degrees of design improvement will be. Good design always
requires one to make careful tradeoffs. During the low-power
design, one needs to consider energy dissipation in addition to
INK W OUT IN- OUT IN- OUT normal concerns of speed, area, performance and design time.

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