FPGA Basics

z What is FPGA
9 Field Programmable Gate Array
9 An FPGA is a regular structure of logic cells (modules) and
interconnect, which is under the designer’s complete control.
FPGA and Xilinx ISE 9 An FPGA is really some programmable logic
with a whole bunch of programmable wires

z How to program
9 Volatile
— SRAM-Based, reprogrammable
9 Non volatile
— Anti-fuse, one time programmable

Page 2

Inside FPGA Virtex-II Architecture

z All Xilinx FPGAs contain some basic resources Block SelectRAM™ I/O Blocks (IOBs)
9 Slices (grouped into Configurable Logic Blocks (CLBs)) resource
— Contain combinatorial logic and register resources
9 IOBs Programmable
— Interface between the FPGA and the outside world interconnect
9 Programmable interconnect Dedicated
9 Other resources multipliers
— Memory Configurable
— Multipliers Logic Blocks
— Processors (CLBs)
— Clock management
z Virtex™-II
architecture’s core
Clock Management
voltage (DCMs, BUFGMUXes)
operates at 1.5V
Page 3 Page 4

1
 Slices and CLBs Simplified Slice Structure
z Each Virtex™-II CLB contains COUT COUT
z Each slice has
four slices BUFT
BUF T
9 Two 4-input look-up tables
9 Local routing provides feedback (LUTs)
Slice S3 Slice 0
between slices in the same — Any 4-input logic functions
CLB, and it provides routing to 9 Four outputs PRE
LUT Carry D Q
neighboring CLBs Slice S2 — Two registered outputs, LUT Carry CE

Switch SHIFT two non-registered outputs

9 A switch matrix provides access CLR
Matrix 9 Carry logic
to general routing resources
— Fast arithmetic logic
Slice S1
9 Other controls
— e.g. set/reset LUT Carry D PRE
Slice S0
LUT Carry CE Q
Local Routing

CLR
CIN CIN

Page 5 Page 6

Virtex-II Pro Features VIrtex-II-Pro Datasheet

z Up to 24 RocketIO™ Multi-Gigabit Transceiver (MGT)
blocks
9 Serializer and deserializer (SERDES)
9 Fibre Channel, Gigabit Ethernet, XAUI, Infiniband compliant
transceivers, and others
9 8-, 16-, and 32-bit selectable FPGA interface
9 8B/10B encoder and decoder
z PowerPC™ RISC processor blocks
9 Thirty-two 32-bit General Purpose Registers (GPRs)
9 Low power consumption: 0.9mW/MHz
9 IBM CoreConnect bus architecture support

Page 7 Page 8

2
 FPGA Design Flow
Design Entry
(Xilinx ISE)
z Plan and budget
Create Code/ HDL RTL
z Two design-entry methods: HDL or schematic
Plan & Budget
Schematic Simulation z Whichever method you use, you will need a tool to generate a
Implement netlist for implementation
9 Netlist: A text file that describes the actual circuit to be implemented at
Functional Synthesize
Translate very low (gate) level
Simulation to create netlist
z Simulate the design to ensure that it works as expected!
Map

Place & Route

Plan & Budget Create Code/ HDL RTL
Attain Timing Timing Create Schematic Simulation
Closure Simulation BIT File
... Functional Synthesize
Simulation to create netlist

Page 9 Page 10

Xilinx Implementation What is Implementation?

z Once you generate a netlist, z Implementation includes many phases
Implement
you can implement the design 9 Translate: Merge multiple design files into a single netlist
z There are several outputs of Translate ... 9 Map: Group logical symbols from the netlist (gates) into physical
implementation components (slices and IOBs)
Map 9 Place & Route: Place components onto the chip, connect the
9 Reports
components, and extract timing data into reports
9 Timing simulation netlists
9 Floorplan files Place & Route z Each phase generates files that allow you to use other
FPGA Editor files
Xilinx tools
9
. 9 Floorplanner, FPGA Editor, XPower
9 and more!
.
.

Page 11 Page 12

3
 Timing Closure Download
z Once a design is implemented, you must create a file
that the FPGA can understand
9 This file is called a bitstream: a BIT file (.bit extension)
z The BIT file can be downloaded directly into the FPGA,
or the BIT file can be converted into a PROM file, which
stores the programming information

Page 13 Page 14

JTAG and Boundary Scan

Boundary Scan
Technology
z In the 1980s, the Joint Test Action Group (JTAG)
developed a specification for boundary-scan testing that
was standardized in 1990 as the IEEE Std 1149.1, and
later revised in 1993 (titled 1149.1a).
z Boundary-scan architecture
9 Each boundary-scan cell including a multiplexer and latches is
assigned to each pin on the device
9 Boundary-scan cells can capture data from pin or core logic
signals, or force data onto pins.
— The captured data is serially shifted out and externally compared to
the expected results
— Forced data is serially shifted into the boundary-scan cells
9 Boundary-scan cells form a serial data path called the scan path
or scan chain.
To know more details: Boundary Scan Tutorial, http://www.asset-
intertech.com/pdfs/boundaryscan_tutorial.pdf

Page 15 Page 16