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CMOSDesign Assignment 2011

This document provides the requirements for a CMOS design assignment to design a two input NOR gate circuit. Students are required to calculate the aspect ratios of the transistors, show the layout including power and ground lines, and submit calculations with explanations. The layout will be evaluated based on the calculations, explanation, quality of drawing, and meeting the specified design constraints of minimum area, 0.3um minimum feature size, and 0.3um maximum alignment error between layers. The completed assignment is due during the first week after Easter break on May 5, 2011, with a 5% per day late penalty after the deadline.

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135 views1 page

CMOSDesign Assignment 2011

This document provides the requirements for a CMOS design assignment to design a two input NOR gate circuit. Students are required to calculate the aspect ratios of the transistors, show the layout including power and ground lines, and submit calculations with explanations. The layout will be evaluated based on the calculations, explanation, quality of drawing, and meeting the specified design constraints of minimum area, 0.3um minimum feature size, and 0.3um maximum alignment error between layers. The completed assignment is due during the first week after Easter break on May 5, 2011, with a 5% per day late penalty after the deadline.

Uploaded by

evildoctorbluetooth
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CMOS Design Assignment (2011)

You are required to design a simple CMOS circuit consisting of a two input NOR gate. You
are required the show the layout (plan view) of the circuit, after calculating the aspect ratio
(W/L) of the transistors. The layout of the circuit should include the VDD and ground lines.

Marks will be awarded for the calculations, the explanation of the calculations, the layout,
and the quality of the drawing of the layout. You must also hand in, with the layout, a
summary of your calculations with full explanation.

Specification:
VDD=3V, VT=0.3V, Co=3x10-4 Fm-2, electron mobility 0.1 m2V-1s-1,
hole mobility 0.05 m2V-1s-1, minimum feature size 0.3m, maximum alignment error 0.3m.
The area of the circuit should be a minimum.

Understanding alignment and minimum feature size:

 The minimum feature size is the smallest dimension that can be defined on a chip.
This will often be the channel length L.

 The various layers have to be aligned (registered) with each other. This involves some
error in placing any mask relative to the pattern already on the silicon. It is necessary
to know how large (in microns) the error can be. You must allow for this in the
design.

The project has to be handed in the first week after Easter


at 12.30pm on 5th of May 2011.
After this date, 5% will be deducted for each working day that it is late.

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