V Semester BTech (E&C)

EC 305 DIGITAL SYSTEM DESIGN

LABORATORY

Laboratory Manual

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

NATIONAL INSTITUTE OF TECHNOLOGY KARNATAKA, SURATHKAL
SRINIVASNAGAR 575025 KARNATAKA INDIA

July 2010
Contents

Objectives 3

1. Familiarisation to VHDL and design environment 6

2. Combinational circuit design 17

3. Sequential Circuit Design 20

4. Arithmetic Units 24

5. Using the LCD Display 25

6. Using Xilinx Core generator 31

7. Communicating to the kit using RS232 interface 36

8. Using Chipscope for verification of designs 43

9. Image Generation 46

10. Using the ADC & DAC

11. Embedded system using Microblaze

12. Complete system design 53

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 DIGITAL SYSTEM DESIGN LABORATORY

Objectives:
The objective of the course is to study advanced digital system design
techniques using a hardware description language, VHDL. Computer-aided design
(CAD) tools will be used extensively to simulate and synthesise digital systems,
which will be ultimately implemented in a Field-Programmable Gate Array (FPGA).
The relationship between the VHDL constructs and the resulting synthesised
hardware will be studied. Students are expected to complete several practical designs
in laboratory exercises, including ALU design, register file design, state machine
design and CPU design.

Choice of hardware and software

Hardware description Language – VHDL
FPGA – Xilinx Spartan-3E
EDA - Xilinx Foundation series v10.1i ISE with ModelSim SE 6.2g simulator

References
1. C. H. Roth and Lizy John, Digital System Design using VHDL, 2e, Cengage, 2008
2. Peter Ashenden, A designers guide to VHDL , 2e, Elsevier, 2008
3. Peter Ashenden, Digital Design – An embedded system approach using VHDL,
Elsevier 2008
4. J. F. Wakerley, Digital System Design: Principles and Practices, PH, 2005
5. Xilinx Foundation Series Documentation – on line
6. www.xilinx.com/university - has links to lots of resources
7. http://www.cosmiac.org/spartan3e_tutorials.html

Common instructions for the lab

1. Labs 1-11 are to be done in groups of 2. Lab 12 is a team exercise (you form
a team of 2 or 3 from your lab batch)
2. Come prepared with programs to be done in the lab
3. Submit top level schematic, VHDL code and results of simulation. Get your
simulation verified.
4. Try implementing the design with different performance constraints and observe
the differences.
5. Verify your designs using the Digilent Xilinx SPARTAN 3E 500 board

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 COURSE PLAN AND EVALUATION PLAN
1. Course Code: EC305 2. Course Title: DIGITAL SYSTEM DESIGN LAB
3. L – T – P: 0-0-3 4. Credits: 2
5. Co-requisite: EC300 6. Teaching Department: Electronics & Communication Engg.
7. Course Instructor: Dr M S Bhat
8. Objectives of the Course:
At the end of the program the student must be able to
Design, simulate & verify digital systems using VHDL, given a set of specifications
Implement & verify digital systems using Programmable ASICs (Xilinx FPGAs)
9. Course Coverage (12 – Lab Schedule ) :
Module Content After completing this chapter, the student No of weeks Evaluation
will be able to
Familiarisation to Introduction to digital system modelling Confident of using Xilinx ISE 8.2i to 1
design environment using Xilinx ISE10.1i describe a digital system using VHDL,
simulate its functionality, implement using
Xilinx FPGA, verify its performance using
simulation and test the design by
downloading to Xilinx demo board
Combinational circuit Design of decoders, priority encoders, Design, implement & test combinational 2
design multiplexers, multi-bit adders and circuits using Xilinx FPGAs
comparators
Sequential circuit Design of counters, shift registers, sequence Design, implement & test simple sequential 2 Test I
design detectors, implementation of state machines circuits using Xilinx FPGAs
for applications like traffic light control,
digital lock, vending machine etc.
DSP building blocks Design of multipliers, adders, MAC unit, and Design, implement & test arithmetic units 2
barrel shifter for signal processing using Xilinx FPGAs
Embedded system Design using Microblaze core Implement simple embedded system using 2
design Microblaze
Complete system Design of memory units, ALU, UART, Design a complete digital system and verify 4 Test II
design simple uP etc its functionality
10. EVALUATION PLAN :

Continuous Evaluation - 20% (Preparation, Class Performance, Documentation, Regularity)

Test I - 25% Test II – 25%
Term Project – 30%

Prepared by: Approved by

M S Bhat Dr. Sumam David S.

Course Instructor Head, Dept of E&C and DUGC Chairperson

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 Digital System Design Laboratory

LAB I

Familiarisation to VHDL and design environment

Objectives:
The aim of this laboratory is to introduce you to VHDL modelling using the Xilinx
Foundation v10.1i.ISE

Introduction
This lab introduces the tools used for design, simulation (functional and timing),
implementation, and testing of the digital systems. We will use the Xilinx Foundation Series
v10.1i, an extensive CAD package that allows you to do all the above functions. It
incorporates powerful display and debug tools. We will be using the full adder circuit as an
illustrative example. You are encouraged to make full use of the online help and tutorials,
Help → Tutorials, provided by the software for detailed information on various aspects of
the tools.

Getting started
To start the software, double click the Xilinx Project Navigator icon on the desktop

Starting the software will bring up the Xilinx Project Navigator window.
Create a New Project: File -> New Project in the New Project dialog box enter project
name as “lab1” and save your project in D:/student/ug/dsdlab/ur_name. Select top level
source type as HDL. Click Next

In the New Project Wizard - Device Properties dialog box select following project
device options.

Family: Spartan3E , Device: XC3S500E, Package: FG320 , Speed : -4 , Synthesis Tool

XST (VHDL/Verilog), Simulator: Modelsim-SE VHDL (You can choose the ISE
Simulator (VHDL/Verilog) also – it is a simulator with limited functionality), Preferred
Language VHDL

Click Next twice, then Click Finish

Design Entry Tools

Foundation supports the following design entry capabilities.
• Top-level schematic entry with the Xilinx Unified libraries components, CORE Generator
cores, HDL macros, and State Machine macros
• Top-level HDL design entry and synthesis
• Top-level HDL designs with schematic-based, state machine, or CORE Generator cores
• Finite state machine diagram entry

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Fig. 1 illustrates the Foundation overall design flow for FPGAs. ModelSim SE 6 is
used in the background for design verification.

Fig.1 Foundation Overall Design Flow for FPGAs

Project manager
The project manager is the base for anything you will want to do with your project.
From it you can do circuit design, simulate/test your design, prepare your circuit for
downloading to hardware, and quite a few other things which we will cover in future labs. It
consists of three main windows – Sources, Processes and Transcript window.

This week we will describe the fulladder using the HDL editor, and then simulate it
with the ModelSim Simulator.

A. Creating the Design

1. Go to the Project -> New Source menu.

2. Select VHDL Module in the dialog box , enter file name/entity name, fulladder, and
select your folder.
3. Click on Add to Project option.
- Next
- Ports Name : – a, b, cin :in ; sum, cout :out
- Click Next, Finish.
Note: Enter data in the MSB column only when describing a bus signal. Make sure you
designate ‘output’ for any output ports.

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The Wizard creates the ports and gives you a template in VHDL in which you can enter
your design.
4. Create the design in the HDL Editor. The Language Templates is available to help you
in writing the architecture. It provides a number of language templates for basic language
constructs and synthesis templates. Access the Language Assistant by selecting Edit →
Language Templates.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fulladder is
port (
a, b, cin : in STD_LOGIC;
sum, cout : out STD_LOGIC
);
end fulladder;

architecture fulladder_arch of fulladder is

begin
sum <= a xor b xor cin;
cout <= (cin and a) or (cin and b) or (a and b);
end fullader_arch;

5. Analysing design file syntax: After entering the code make sure that the module is
selected in the Sources window. Then in the Processes window Synthesize → Check
Syntax .
6. If there are any errors correct them and check syntax again.

B. Behavioral Simulation
In this section, we will introduce the concept of test bench and show how to verify the
function of our full adder by behavioral simulation.

Fig. 2 Conceptual diagram of test bench

A test bench is an entity (usually a VHDL/Verilog program) which is used to verify the
correctness of a design. The design to be verified is called Unit Under Test (UUT). The test
bench supplies stimuli to the design, observes the outputs of the design, and compares the
observed outputs with the expected values. If any mismatch happens, the test bench issues

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certain messages signifying that there are errors in the design. Fig. 2 shows the concept of test
bench.

Advanced EDA tools such as Xilinx ISE usually have the capability to automatically generate
the test bench. All the users need to do is specifying the waveforms of the stimuli and the
expected outputs; the software produces the test bench program which can be tailored later
on.

Build the test bench by specifying waveforms

1. Go to the Project ->New Source select the Test Bench Waveform and save it as
fulladder_tbw .
2. Associate Source : Select fulladder (your source file). Click Next – Finish..
3. Initialize Timing : Select Clock Information -> Combinational for combinational
design or select appropriate clock for sequential design.
In the Combinatorial Timing Information group, specify Check Outputs 25ns after
inputs are assigned, and Assign Inputs 25ns after outputs are checked.

You will see the waveform window of the test bench. The three input signals are marked
cyan while the two output signals are marked yellow. By directly clicking on the
waveform you can change the values of the signal. Just play around a little to get familiar
with it. Now specify the waveforms of the three inputs as shown in Fig 3. Notice that the
waveforms of a, b, and cin cover all possible 8 combinations. Save the waveforms after
you’re done.

Fig. 3 Test bench waveforms

.
You can also Initialize Inputs by invoking the Pattern Wizard by right-clicking a
waveform and selecting Set Value and clicking the Pattern Wizard button.

4. In the Sources Window, Select Sources for Behavioral Simulation. In the Process
window, double click on View Generated Test Bench as HDL, you’ll see the generated
test bench program. Close it.

5. Make sure that you have the test bench waveform you created selected in Sources
window. In the Process window, Expand Modelsim Simulator and double click
Simulate Behavioral Model. This will open up ModelSim simulation windows and run

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the test bench simulation. If ModelSim fails to start, you need to go back to check the
license.
6. Check the waveforms to see whether there are any errors.

Fig. 4 Waveforms of Behavioural simulation

7. Close the simulator.
Create a VHDL Testbench

Fig. 5 VHDLTestbench
1. In the Project Navigator select Project -> New source -> VHDL Testbench , File Name:
fulladd_tb.vhd and follow the design wizard.
2. Edit the code given in Fig.5 in the Test Bench user defined section.
3. Select the above file in the Sources window and in Process window select and double
click on Simulate Behavioral VHDL Model under ModelSim Simulator. This invokes
ModelSim Simulator (with four different windows). Observe the waveform in wave
default window.

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C. Synthesizing the Design

After the design files have been successfully analysed, the next step is to translate the
design into gates and optimise it for target architecture.
1. Select the top-level source ( .vhd file) in the Source window.
2. Double click on the Synthesize process in the Process window to synthesize the entire
design hierarchy.
3. View the Synthesis Report : Double click on View Synthesis Report in the Process
window. This report contains parameters and options used during synthesis, a log of the
synthesis errors and warnings, macro extraction and inference, device cell usage, and
estimated timing results.
4. View RTL schematic: Double click on View RTL Schematic in the Process window.
Click on each component to see the lower levels of design hierarchy.
5. Change Synthesis Options:
Right click on the Synthesize process and choose Properties.
Select the HDL Options tab. The HDL Options tab allows you to specify various
macro extraction techniques used by XST.
D. Design Implementation
Next we’ll map the full adder design to the FPGA device that we selected in the beginning of
this tutorial. Such a process is called implementation. Design implementation is the process
of translating, mapping, placing, routing and generating a BIT file for your design.

1. Double Click the Implement Design in the Processes window. The process goes
through the following stages Translate → Map → Place & Route.
2. View implementation results: Open Implementation report files in Design Summary and
go through all the reports –map report, post-map static timing report, and place & route
report. Note down the resource utilisation (CLBs,LUTs and IOBs) and worst case delay
(critical path) of the implementation.
3. View FPGA implementation: From the Processes -> Implement Design -> Place &
Route -> View/Edit Routed Design (FPGA Editor), invoke the design viewer and see
for yourself how the design is implemented on the FPGA.

E. Post-place & Route Simulation

Post-place & Route simulation is different from behavioral simulation in that we will see the
real signal delay in the waveforms.

1 Before we run the post-place & route simulation, double click Generate Post-Place &
Route Simulation Model under Implement Design -> Place & Route in the Processes
window.
2. Create a new test bench FullAdder_post_tbw.tbw. This time, set Check Outputs 10ns
after inputs are assigned, and Assign Inputs 40ns after outputs are checked. Specify the
waveforms as you did for FullAdder_tbw.tbw. When done, Select Sources for Post-Route
Simulation¸ FullAdder_post_tbw.tbw and double click Simulate Post-Place & Route
VHDL Model in the Processes window.
3. Again, ModelSim will launch and simulate the test bench with post-place and route
timing information. In the waveforms of Fig. 6, a path delay is explicitly shown. Compare
Fig. 6 with Fig. 4 to see how they are different.

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If you get an error message that SIMPRIMS library is missing, do the following in modelsim
window- Right click in Workspace – Library window, Click on New Æ Library. When the
Create new Library window opens, Select Map to an existing library, Library name :
simprims, Library maps to: c:/Xilinx/10.1/ISE/vhdl/mti_se/simprims

Fig. 6 Post Place & Route simulation

Final Note: You may not be able to see the worst case delay in your post-place & route
waveforms, because the worst case delay is input pattern dependant. Put another way, the
worst case delay happens only when certain transitions of the inputs take place. As an
exercise, think about what input transitions will exhibit the worst case delay of our full adder.
Modify your test bench to have the worst case delay shown in the waveforms.

F. Download design to Xilinx Spartan 3E board

We will now download the full adder design to the Spartan 3E board and test its
functionality.

Assignment of pins on Spartan 3E Board

We will use switches SW0, SW1, and SW2 as inputs “a”, “b”, “cin”, respectively. Also,
LEDs LED0 and LED1 will be used as outputs “sum” and “cout”. Table 1 provides the
mapping of the pins to the FPGA. For convenience, we list only the 5 signals used here. A
complete mapping table is given in Spartan3E Starter Kit Board Users guide
(S3EStarter_ug230.pdf). Specify the pin locations for the ports of the design so that they are
connected correctly on the Spartan-3E board.

VHDL Physical FPGA Pin

Name location
a SW0 L13
b SW1 L14
cin SW2 H18
sum LED0 F12
cout LED1 E12
Table 1

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1. To assign physical pins in Xilinx ISE, go to “Project” -> “New Source”. Click
Implementation Constraints File and type in the file name fulladder_ic. Click Next.
Associate your Implementation Constraints File with required source file fulladder.vhd
and click Next.
2. Expand “User Constraints” and then double click “Floorplan IO – Pre-Synthesis”. Xilinx
PACE will be started. Assign the pins as shown in the Fig. 7. Save the pin assignment.
You are prompted to select the bus delimiter type based on the synthesis tool you are
using. Select XST Default <> and click OK. Close PACE.

Fig. 7 Pin assignment

Generate Programming File and Download

1. Connect the power supply cord to the board.

2. Connect the USB cable to board.( Make sure that it is connected properly) and the other
end to the PC USB port.
3. Implement the design again by double clicking Implement Design in Processes window.
Then, double click Generate Programming File.
4. Expand Configure Target Device Then, double click on Manage Configuration Project
(iMPACT).The iMPACT window will show up:
4. In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG).
Verify that Automatically connect to a cable and identify Boundary-Scan chain is
selected.. Click Finish.
.
The boundary scan performed on the board finds three items on the JTAG chain. The
items are (in order from left to right): the FPGA, the PROM and the CPLD. The program
will then ask you to select a configuration file. Select fulladder.bit we created and click
Open. For the PROM and the CPLD choose “Bypass”.
The Programming Properties dialog box opens. Click OK.

Your board and chip should be automatically identified. Skip the warning messages.
Right click on the Xilinx Spartan3E FPGA in iMPACT window and select Program.
Click OK to program the device. When programming is complete, the Program
Succeeded message is displayed.
:
Try to turn on/off the switches SW0, SW1 and SW2 on the board.
Verify the correctness of the response from LEDs LED0, LED1.

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Design Entry (Top-level Schematic)

This section of the tutorial introduces you to the Xilinx tool for creating and editing
schematic diagrams and demonstrates how to create a top-level schematic that contains
instantiations of the adder module, and describes how to wire together the modules, add net
names and buses to the wires, and add I/O markers to show where signals enter or exit the
schematic.

The design used in this tutorial is a hierarchical, schematic-based design, which means that
the top-level design file is a schematic sheet that refers to several other lower-level macros.
The lower-level macros can be schematic based modules, CORE Generator modules, state
machine modules, Architecture Wizard modules, and HDL modules.

Creating a New Project

From Project Navigator, select File –> New Project. Type adder as the Project Name.
Select Schematic as the Top level Source Type. Select the FPGA in the Device
Properties Window. Click Add Source in the Add Existing Sources Window. Add
fulladder.vhd you have created in Lab1 to the project.

Creating a Schematic Symbol for the VHDL Module

In Project Navigator, in the Sources in Project window, select your fulladder module,
fulladder.vhd.
In the Processes for Current Source window, click the + sign beside Design Utilities and
double-click the Create Schematic Symbol process. This places a schematic component
entitled fulladder in the project library

Creating a New Top-Level Schematic

To create a new top-level schematic, in Project Navigator: Select Project New Source.
Select Schematic as the source type. Type in the name adder4. Click Next and then click
Finish. Schematic Editor is launched and a blank sheet opens.

Adding I/O Markers

I/O markers are used to determine the ports on a macro, or the top-level schematic. The
name of each pin on the symbol must have a corresponding connector in the underlying
schematic. Add I/O markers to the adder4 schematic to determine the macro ports.
1. Select Tools -> Create I/O Markers. The Create I/O Markers dialog box opens.
2. In the Inputs box, enter a(3:0), b(3:0), cin.
3. In the Outputs box, enter sum(3:0),cout.
4. Click OK. The five I/O markers are added to the schematic sheet.
Note: The Create I/O Marker function is available only for an empty schematic sheet.
However, I/O markers may be added to nets at any time by selecting Add > I/O Marker
and selecting the desired net.

Instantiating VHDL Modules

In the blank sheet open instantiate four fulladder module symbols in the top-level
schematic.
Select Add Symbol or click the Add Symbol icon in the Tools toolbar.

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Select fulladder from the Symbols list in the Symbol tab (to the left of the screen). Do
not select any options from the Categories list.
Place four fulladders in the schematic. Click the left mouse button to place a fulladder on
the schematic where the cursor sits.
Press Esc to exit Add Symbol mode and restore your cursor.
Adjust your view using the Zoom option (View Zoom In) and the scroll bars.

Drawing Wires
Select Add > Wire or click the Add Wires icon in the Tools toolbar to draw
wires (also called nets) to connect the components placed in the schematic.

Adding Buses
In the Schematic Editor, a bus is simply a wire that has been given a multi-bit name. To
add a bus, use the methodology for adding wires and then add a multi-bit name. Once a
bus has been created, you have the option of “tapping” this bus off to use each signal
individually.
To add the buses a(3:0), b(3:0) and sum(3:0) to the schematic perform the following
steps:
1. Select Add > Wire or click the Add Wires icon in the Tools toolbar.
2. Click in the open space just above and to the left of the top fulladder and then click
again on pin of the a(3:0) I/O marker. The wire should automatically be drawn as a bus
with the name matching that of the I/O marker.

Adding Bus Taps

Next, add nets to attach the appropriate pins from the fulladder modules to the buses. Use
Bus Taps to tap off a single bit of a bus and connect it to another component.
1. To tap off a single bit of each bus: Select Add > Bus Tap or click the Add Bus Tap
icon in the Tools toolbar.
2. From the Options tab to the left of the schematic, choose the correct orientation for the
bus tap.
3. Place the tap on one of the three busses so that the wire side of the bus tap is pointing
to an unconnected pin.
4. Repeat Steps 1 to 3 to tap off four bits from each of the three busses.

To connect each of the tap off bits

1. Select Add > Wire or click the Add Wire icon in the Tools toolbar.
2. Draw a wire from each bus tap pin to the adjacent component pin.
3. Select Add > Net Name or click the Add Net Name icon in the Tools toolbar.
4. Type a(0) in the Name field of the options tab. The net name is now at the end of your
cursor.
5. Select Increase the name in the Add Net Names Options dialog box.
6. With the Increment Name option selected, start at the top net and continue clicking
down until you have named the fourth and final net a(3).
Note: The Schematic Editor names the bus taps incrementally as they are drawn.
7. Repeat b(3:0) bus and sum(3:0).

Note: It is the name of the wire that makes the electrical connection between the bus and
the wire. The bus tap figure is for visual purposes only. Electrical connections can be
made just by named association without any physical connection also.

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Checking the Schematic

The adder4 schematic is now complete.
Verify that the schematic does not contain logical errors by running a design rule check
(DRC). To do this, select Tools > Check Schematic. The Console window should report
that no errors or warnings are detected. If an error or warning is displayed, fix the
reported problem before proceeding.

Creating a Schematic Symbol for the adder4 Module

In Project Navigator, in the Sources in Project window, select your adder4 module.
In the Processes for Current Source window, click the + sign beside Design Utilities and
double-click the Create Schematic Symbol process. This places a schematic component
entitled adder4 in the project library

Simulation

Simulate the adder4 module and check its functionality.

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