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    Esquema Placa Mae 810 Celeron

    Uploaded by

    Luciano Francisco Dos Santos

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    Esquema Placa Mae 810 Celeron

    Uploaded by

    Luciano Francisco Dos Santos
    95 views41 pages

    Original Title

    esquema placa mae 810 celeron

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    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    95 views41 pages

    Esquema Placa Mae 810 Celeron

    Uploaded by

    Luciano Francisco Dos Santos

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 41

    8 7 6 5 4 3 2 1

    INTEL(R) CELERON(TM) PROCESSOR (PPGA)/INTEL(R) 810 CHIPSET


    UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS
    REVISION 1.3
    D
    D
    TITLE PAGE
    Cover Sheet 1
    Block Diagram 2 ** PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE
    370-Pin Socket 3,4 TH ESE SC HEM AT IC S ARE PRO VIDED “AS IS” W ITH N O W ARRANT IES
    GTL Termination 5 W HATSO EVER, INCLUDIN G ANY W AR RANT Y O F M ERCH ANT ABILIT Y,
    Clock Synthesizer 6 FIT NESS FO R ANY PART ICULAR PUR PO SE, O R ANY W ARR ANT Y
    GMCH 7,8,9 O THERW ISE ARISING O UT O F PR O PO SAL, SPECIFIC AT IO N O R SAM PLES.
    Frame Buffer 10 Inform ation in this docum ent is provided in connection with Intel products. No
    C
    DIMM Sockets 11,12 license, express or im plied, by estoppel or otherwise, to any intellectual property
    C
    ICH0 13,14 rights is granted by this docum ent. Except as provided in Intel's T erm s and
    Conditions of Sale for such products, Intel assum es no liability whatsoever, and
    FWH 15
    Intel disclaim s any express or im plied warranty, relating to sale and/or use of Intel
    Super I/O 16 products including liability or warranties relating to fitness for a particular purpose,
    PCI Connectors 17,18 m erchantability, or infringem ent of any patent, copyright or other intellectual
    ATA33 IDE Connectors 19 property right. Intel products are not intended for use in m edical, life saving, or life
    sustaining applications.
    USB Connectors 20
    Parallel Port 21 Intel m ay m ake changes to specifications and product descriptions at any tim e,
    Serial/Game Ports 22 without notice.
    Keyboard/Mouse/Floppy Disk 23
    B The Intel Celeron TM processor and Intel 810 chipset m ay contain design defects B
    Digital Video Out (TBD) 24
    or errors known as errata which m ay cause the product to deviate from published
    Graphics Connectors 25 specifications. Current characterized errata are available on request.
    AC’97 Riser Connector 26
    LAN 27,28 Copyright © Intel Corporation 1998.
    System Voltage Regulators 29
    *Third-party brands and nam es are the property of their respective owners.
    Processor Voltage Regulator 30
    System 31,32
    Pullup Resistors and Unused Gates 33
    A Decoupling 34,35 A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    COVER SHEET
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 5-26-1999_17:09 1 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    Block Diagram
    D
    D Device Table
    VRM 370-Pin Socket Processor Clock
    REFERENCE SHEET
    DESIGNATOR DEVICE TYPE GATES USED NUMBER

    DATA
    CTRL
    ADDR
    U12 74lvc14a A,B,C,D 32
    Term U16,U17 gd75232 22

    ADDR

    DATA
    CTRL
    U15 lpc47b27_a 16
    U3 74lvc06a A,B,C,D 29,32
    Display Cache
    Memory U1 ck-whitney 6
    2 DIMM
    GMCH Modules U2 82810-DC100 7,8,9
    U14 82801AB 13,14
    C
    Digital Video U7 sii-dfp 24
    Out Device C
    U13 82559 27
    U8,U9 1x16sdram 10
    IDE Primary UltraDMA/33 U10 74lvc08a A,B 32
    PCI CNTRL

    PCI CONN 1

    PCI CONN 2

    PCI CONN 3
    IDE Secondary U6 qst3384 25
    ICH0
    PCI ADDR/DATA U18 93c46 27
    USB Port 1 USB U4 74ls132 A,B 29,32
    USB Port 2
    U5 74lvc07a A,B,C 29,31
    U11 74lvc07a A,B,C 19,31
    VR2,VR3 lt1587ad 29
    LPC Bus

    PCI CNTRL
    AC’97 Link
    AMC’97 VR4 lt1117_3 29
    Audio/Modem PCI ADDR/DATA LAN
    VR1 ltc1753 30
    B
    B
    SIO
    VR5 lt1585ad 29

    FirmWare Hub

    Keyboard Floppy Parallel Game Conn


    Mouse
    Serial 1

    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    BLOCK DIAGRAM
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:43 2 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1
    VCCVID
    370PGA Socket
    Part 1

    AM12

    AM16

    AM20

    AM24

    AM28

    AM32
    AH32
    AK34
    AJ13

    AJ17

    AJ21

    AJ25

    AJ29
    AM4

    AM8
    AK2

    AB2

    AE5
    AA5
    AF2

    D20

    D24

    D28

    R32
    B26

    B10

    E13
    B14

    E17
    B18

    B30

    V32
    AJ5

    AJ9

    F22

    F26

    F30

    Z32
    W5
    C3

    N5

    D6
    P2
    K2

    E5

    S5

    B6

    E9
    T2

    F4

    F2
    HD#[63:0] X2 HA#[31:3]

    J5
    5,7 5,7
    HD#0 W1

    VCC10
    VCC11
    VCC12
    VCC13
    VCC14
    VCC15
    VCC16
    VCC17
    VCC18
    VCC19
    VCC20
    VCC21
    VCC22
    VCC23
    VCC24
    VCC25
    VCC26
    VCC27
    VCC28
    VCC29
    VCC30
    VCC31
    VCC32
    VCC33
    VCC34
    VCC35
    VCC36
    VCC37
    VCC38
    VCC39
    VCC40
    VCC41
    VCC42
    VCC43
    VCC44
    VCC45
    VCC46
    VCC47
    VCC48
    VCC49
    VCC50
    VCC51
    VCC52
    VCC1
    VCC2
    VCC3
    VCC4
    VCC5
    VCC6
    VCC7
    VCC8
    VCC9
    HD#0
    HD#1 T4
    HD#1 AK8 HA#3
    HD#2 N1 HA#3
    HD#2 AH12 HA#4
    HD#3 M6 HA#4 D
    D HD#3 AH8 HA#5
    HD#4 U1 HA#5
    HD#4 AN9 HA#6
    HD#5 S3 HA#6
    HD#5 AL15 HA#7
    HD#6 T6 HA#7
    HD#6 AH10 HA#8
    HD#7 J1 HA#8
    HD#7 AL9 HA#9
    HD#8 S1 HA#9
    HD#8 AH6 HA#10
    HD#9 P6 HA#10
    HD#9 AK10 HA#11
    HD#10 Q3 HA#11
    HD#10 AN5 HA#12
    HD#11 M4 HA#12
    HD#11 AL7 HA#13
    HD#12 Q1 HA#13
    HD#12 AK14 HA#14
    HD#13 L1 HA#14
    HD#13 AL5 HA#15
    HD#14 N3 HA#15
    HD#14 AN7 HA#16
    HD#15 U3 HA#16
    HD#15 AE1 HA#17
    HD#16 H4 HA#17
    HD#16 Z6 HA#18
    HD#17 R4 HA#18
    HD#17 AG3 HA#19
    HD#18 P4 HA#19
    HD#18 AC3 HA#20
    HD#19 H6 HA#20
    HD#19 AJ1 HA#21
    HD#20 L3 HA#21
    HD#20 AE3 HA#22
    G1 HA#22

    370-Pin Socket
    HD#21
    HD#21 AB6 HA#23
    C HD#22 F8 HA#23
    HD#22 AB4 HA#24 C
    HD#23 G3 HA#24
    HD#23 AF6 HA#25
    HD#24 K6 HA#25
    HD#24 Y3 HA#26
    E3 HA#26

    Part 1
    HD#25
    HD#25 AA1 HA#27
    HD#26 E1 HA#27
    HD#26 AK6 HA#28
    HD#27 F12 HA#28
    HD#27 Z4 HA#29
    HD#28 A5 HA#29
    HD#28 AA3 HA#30
    HD#29 A3 HA#30
    HD#29 AD4 HA#31
    HD#30 J3 HA#31
    HD#30 VID[3:0]
    HD#31 C5 AL35 VID0 30
    HD#31 VID0
    HD#32 F6 AM36 VID1
    HD#32 VID1
    HD#33 C1 AL37 VID2
    HD#33 VID2
    HD#34 C7 AJ37 VID3
    HD#34 VID3
    HD#35 B2 RS#[2:0]
    HD#35 AH26 RS#0 7
    HD#36 C9 RS#0
    HD#36 AH22 RS#1
    HD#37 A9 RS#1
    HD#37 AK28 RS#2
    HD#38 D8 RS#2
    HD#38 HREQ#[4:0]
    HD#39 D10 AK18 HREQ#0 7
    HD#39 REQ#0
    HD#40 C15 AH16 HREQ#1
    HD#40 REQ#1
    HD#41 D14 AH18 HREQ#2 B
    B HD#41 REQ#2
    HD#42 D12 AL19 HREQ#3
    HD#42 REQ#3
    HD#43 A7 AL17 HREQ#4
    HD#43 REQ#4
    HD#44 A11
    HD#44 AH20
    HD#45 C11 RSRVD1
    HD#45 AH4
    HD#46 A21 RSRVD2
    HD#46 A29
    HD#47 A15 RSRVD3
    HD#47 A31
    HD#48 A17 RSRVD4
    HD#48 A33
    HD#49 C13 RSRVD5
    HD#49 AA33
    HD#50 C25 RSRVD6
    HD#50 AA35
    HD#51 A13 RSRVD7
    HD#51 AC1
    HD#52 D16 RSRVD8
    HD#52 AC37
    HD#53 A23 RSRVD9
    HD#53 AF4
    HD#54 C21 RSRVD10
    HD#54 AK16
    HD#55 C19 RSRVD11
    HD#55 AK24
    HD#56 C27 RSRVD12
    HD#56 AK30
    HD#57 A19 RSRVD13
    HD#57 AL11
    HD#58 C23 RSRVD14
    HD#58 AL13
    A HD#59 C17 RSRVD15
    HD#59 AL21 A
    HD#60 A25 RSRVD16
    HD#60 AN11
    HD#61 A27 RSRVD17
    HD#61 AN13
    HD#62 E25 RSRVD18
    GND10
    GND11
    GND12
    GND13
    GND14
    GND15
    GND16
    GND17
    GND18
    GND19
    GND20
    GND21
    GND22
    GND23
    GND24
    GND25
    GND26
    GND27
    GND28
    GND29
    GND30
    GND31
    GND32
    GND33
    GND34
    GND35
    GND36
    GND37
    GND38
    GND39
    GND40
    GND41
    GND42
    GND43
    GND44
    GND45
    GND46
    GND47
    GND48
    GND49
    GND50
    HD#62
    GND1
    GND2
    GND3
    GND4
    GND5
    GND6
    GND7
    GND8
    GND9

    HD#63 F16
    HD#63
    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    V2

    AL3

    Y5

    Q5

    G5

    B4

    E7
    B8

    E11
    B12

    E15
    B16

    E19

    B20

    B24

    B28
    M2
    D18
    H2
    D2

    AG5

    U5

    L5

    D4

    D22

    D26

    D30
    AM34

    F28

    AM30
    AM2

    AH2
    AD2
    Z2

    AK4

    AC5

    AM6
    AJ7

    AM10
    AJ11

    AM14
    AJ15

    AM18
    AJ19

    F20

    AM22
    AJ23

    F24

    AM26
    AJ27

    370-PIN SOCKET, PART 1


    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 3 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    370PGA Socket VTT1_5 VCC2_5

    Part 2 4,33
    4,33 VCC2_5

    VCMOS

    VCMOS
    4
    VTT1_5 4,33 R9
    VCCVID
    ITP Test Port Option

    GTLREF
    VCMOS
    220

    5
    RP2 D
    D R8 R7 JP1
    150

    AD36

    AH36

    AD32
    AH24
    AB36

    AK12
    AK22

    AB34

    AA37
    1K

    AF34
    AD6
    330

    M32
    J2

    H32

    R36
    H36
    D36
    D32
    E33

    X34

    P34
    K34

    B34

    B22
    V36

    K32

    Y35
    Z36

    F18

    T34

    F34

    F14
    R6
    K4

    V6
    1

    4
    R1 X2
    CPURST# ITP_RST 1 2
    4,5,7

    VCC53
    VCC54
    VCC55
    VCC56
    VCC57
    VCC58
    VCC59
    VCC60
    VCC61
    VCC62
    VCC63
    VCC64
    VCC65
    VCC66
    VCC67
    VCC68
    VCC69
    VCC70
    VCC71
    VCC72
    VCC73
    VCC74
    VCC75
    V1_5
    V2_5

    VREF0
    VREF1
    VREF2
    VREF3
    VREF4
    VREF5
    VREF6
    VREF7
    V_CMOS
    DBRESET# 240 R2 R_DBRST# 3 4 JP1 is a Test Option Only.
    32
    R_TCK 0K 5 6
    4
    R_TMS 7 8 TDI AN35 AH14 BNR#
    4 TDI BNR# 5,7
    ITP_PON9 10 TDO AN37 AN17 BPRI#
    TDO BPRI# 5,7
    11 12 TRST# AN33 AN25 HTRDY#
    TRST# TRDY# 5,7
    13 14 R_TCK R3 TCK AL33 AN19 DEFER#
    4 TCK DEFER# 5,7
    15 16 ITPREQ# R_TMS R4 47 TMS AK32 AK20 HLOCK#
    4 TMS LOCK# 5,7
    17 18 R_ITPRDY# 47 AN27 DRDY#
    J37 DRDY# 5,7
    19 20 PREQ# AL23 HITM#
    ITPRDY# A35 HITM# 5,7
    21 22 4,5 PRDY# AL25 HIT#
    HIT# 5,7
    R21 ITPRDY# G33 AL27
    23 24 DBSY#
    4,5 BP2# DBSY# 5,7
    25 26 E37 AN31 HADS#
    240 BP3# ADS# 5,7
    27 28 C35 AE37
    BPM0# FLUSH#
    ITPCLK 29 30 E35
    6 BPM1# AJ33 FREQSEL
    C BSEL# 6,9
    AN15 AN29 BR0# C
    RSRVD19 BR0# 5
    AN21
    AN23
    RSRVD20
    RSRVD21
    370-Pin Socket THRMDP
    AL31
    AL29
    B36 THRMDN
    RSRVD22 AH28
    C29 THERMTRIP#
    RSRVD23
    C31 AE33

    Part 2
    A20M#
    RSRVD24 A20M# 13,33
    C33 AG35 STPCLK#
    RSRVD25 STPCLK# 13,33
    E23 AH30 CPUSLP#
    RSRVD26 SLP# 13,33
    E29 AJ35 SMI#
    RSRVD27 SMI# 13,33
    E31 M36 INTR
    VTT1_5 RSRVD28 LINT0/INTR 13,33
    F10 L37 NMI
    RSRVD29 LINT1/NMI 13,33
    G35 AG33 INIT#
    RSRVD30 INIT# 13,15,33
    GTLREF Generation Circuit G37
    RSRVD31 FERR#
    AC35 FERR#
    13,33
    L33 AG37 IGNNE#
    RSRVD32 IGNNE# 13,33
    R102 75 N33 AE35
    RSRVD33 IERR# VCCVID
    Use 0603 Packages and distribute N35
    1% within 500 mils of Mendocino RSRVD34 W33 PLL1
    GTLREF Inputs (1 cap for every 2 inputs). N37 PLL1 L22
    RSRVD35 U33 PLL2 C123
    Q33 PLL2 +
    GTLREF RSRVD36 2 1
    4 Q35 4.7UH
    RSRVD37 33UF 20% B
    B Q37 S37
    R104 150 RSRVD38 RSRVD40
    C206 C209 C204 C207 S33 U35 VCC3_3
    RSRVD39 RSRVD41
    U37
    1% 0.1UF 0.1UF 0.1UF 0.1UF APICD0 J35 RSRVD42
    13,33 PICD0 V4
    APICD1 L35 RSRVD43
    13,33 PICD1 W3 R171
    APICCLK_CPU J33 RSRVD44
    6 PICCLK W35 220
    RSRVD45
    CPUHCLK W37 X6
    6 BCLK RSRVD46
    Y1
    VCCVID PWRGOOD AK26 RSRVD47
    32 PWRGOOD E21 VCOREDET
    CPURST# X4 RSRVD48 9
    4,5,7 RESET# E27 SLEWCTRL
    R76
    RSRVD49 33
    VCMOS Decoupling EDGCTRL AG1
    EDGCTRL RSRVD50
    R2
    51 S35 RTTCTRL
    C37 RSRVD51 33
    CPUPRES# X2
    VCMOS RSRVD52
    Place 0603 Package
    GND51
    GND52
    GND53
    GND54
    GND55
    GND56
    GND57
    GND58
    GND59
    GND60
    GND61
    GND62
    GND63
    GND64
    GND65
    GND66
    GND67
    GND68
    GND69
    GND70
    GND71
    GND72
    GND73
    GND74
    GND75
    GND76
    GND77
    GND78
    GND79
    GND80
    4,33
    Near VCMOS Processor Pin.

    C6
    X32

    P32

    B32

    V34
    R34
    M34
    H34
    D34

    X36

    P36
    K36

    A37

    AL1

    Y37

    Y33
    AF32
    AB32

    AK36
    AF36
    T32

    F32

    AH34
    AD34
    Z34

    T36

    F36

    AC33
    AJ3

    AN3

    AJ31
    R5
    0.1UF 680
    A Do Not Stuff C114 C114
    Place Site w/in 0.5" A
    of clock pin (W37).18PF

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    370-PIN SOCKET, PART 2
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 5-26-1999_17:09 4 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    GTL Termination
    VTT1_5 VTT1_5 VTT1_5
    VTT1_5

    D
    D

    RP6 RP22 RP38 HD#[63:0]


    RP19 1 8 BPRI# 1 8 HD#15 1 8 HD#54 3,7
    1 8 HA#17 HA#[31:3] 4,7
    3,7 2 7 HREQ#4 2 7 HD#1 2 7 HD#55
    2 7 HA#22 3,7
    3 6 HLOCK# 3 6 HD#0 3 6 HD#52
    3 6 HA#31 4,7
    4 5 RS#1 3,7 4 5 HD#6 4 5 HD#40
    4 5 HA#19
    56 56 56
    56
    RP9 RP23 RP33
    RP18 1 8 HTRDY# 1 8 HD#8 1 8 HD#56
    1 8 HA#18 4,7
    2 7 RS#0 3,7 2 7 HD#5 2 7 HD#61
    2 7 HA#21
    3 6 DRDY# 3 6 HD#9 3 6 HD#62
    3 6 HA#25 4,7
    4 5 DBSY# 4 5 HD#4 4 5 HD#46
    4 5 HA#10 4,7

    56 56 56
    56
    RP5 RP35 RP32
    C RP8 1 8 HITM# 1 8 HD#16 1 8 HD#60
    4,7 C
    1 8 HA#15 2 7 HIT# 2 7 HD#23 2 7 HD#50
    4,7
    2 7 HA#12 3 6 RS#2 3 6 HD#21 3 6 HD#53
    3,7
    3 6 HA#3 4 5 HADS# 4 5 HD#24 4 5 HD#58
    4,7
    4 5 HA#6
    56 56 56
    56
    RP10 RP24 RP36
    RP20 1 8 HREQ#0 1 8 HD#3 1 8 HD#57
    3,7
    1 8 HA#30 2 7 DEFER# 2 7 HD#12 2 7 HD#63
    4,7
    2 7 HA#24 3 6 HREQ#3 3 6 HD#10 3 6 HD#59
    3,7
    3 6 HA#20 4 5 HREQ#2 4 5 HD#17 4 5 HD#48
    3,7
    4 5 HA#23
    56 56 56
    56
    RP3 RP26 RP39
    RP12 1 8 ITPRDY# 1 8 HD#30 1 8 HD#47
    4
    1 8 HA#28 2 7 2 7 HD#7 2 7 HD#27
    2 7 HA#13 3 6 3 6 HD#11 3 6 HD#44
    3 6 HA#16 4 5 BR0# 4 5 HD#20 4 5 HD#45
    4
    4 5 HA#5
    56 56 56
    56
    RP25 RP37 B
    B RP7 1 8 HD#13 1 8 HD#49
    1 8 HA#9 2 7 HD#18 2 7 HD#51
    2 7 HA#11 3 6 HD#14 3 6 HD#41
    3 6 HA#7 4 5 HD#2 4 5 HD#42
    4 5 HREQ#1
    3,7
    56 56
    56
    RP43 RP40
    RP11 1 8 HD#31 1 8 HD#36
    1 8 HA#8 2 7 HD#32 2 7 HD#22
    2 7 HA#4 3 6 HD#25 3 6 HD#43
    3 6 BNR# HD#26 HD#34
    4,7 4 5 4 5
    4 5 HA#14
    56 56
    56
    RP41 RP42
    RP21 1 8 HD#29 1 8 HD#39
    1 8 CPURST# HD#19 HD#37
    4,7 2 7 2 7
    2 7 HA#26 3 6 HD#35 3 6 HD#38
    3 6 HA#29 4 5 HD#33 4 5 HD#28
    4 5 HA#27
    A 56 56 A
    56

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    GTL TERMINATION
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 5 OF 38
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    VCC3_3

    Clock Synthesizer USBV3 1


    L17
    2

    1
    C55 C50

    +
    VCC3_3 VCC3_3
    22UF 0.1UF

    2
    L13 L16
    1 2 1 2 D
    D
    PCIV3 MEMV3

    1
    C158 C38 C37 C39 C40 C386 C388 C385 C387 C60 C63 C64 C61 C48

    +
    2

    2
    22UF 0.1UF .001UF 0.1UF .001UF 0.1UF .001UF .001UF 0.1UF .001UF 0.1UF .001UF 0.1UF 22UF

    Notes:
    - Place all decoupling caps as close to VCC/GND pins as possible
    - PCI_0/ICH pin has to go to the ICH. R41
    (This clock cannot be turned off through SMBus) 8.2K

    SEL1_PU
    10
    21
    27
    33
    38
    44
    U1

    2
    9
    - CPU_ITP pin has to go to the ITP. It is the only
    CPU CLK that can be shut off through the SMBUS interface. C51

    VDD3_3[0]
    VDD3_3[1]
    VDD3_3[2]
    VDD3_3[3]
    VDD3_3[4]
    VDD3_3[5]
    VDD3_3[6]
    VDD3_3[7]
    12PF
    Y1

    2
    XTAL_IN 3 55 APIC_0 R34 APICCLK_CPU
    XTAL_IN APIC_0 4

    XTAL
    APIC 54 APIC_1 33 R25 APICCLK_ICH
    C 14.318MHZ APIC_1 13
    33 C

    1
    REF
    SIO_CLK14 R184 C49 XTAL_OUT 4 52 CPU_0_1 R32 CPUHCLK
    16 XTAL_OUT CPU_0 4
    10 12PF 50 33 R35 GMCHHCLK
    CPU CPU_1 7
    ICH_CLK14 R48 REFCLK 1 49 CPU_2 R26 33 ITPCLK
    14 REF0 CPU_2/ITP 4
    10 33
    ICH_3V66 R42 3V66_0 7 46 DRAM_0 R36 MEMCLK0 MEMCLK[7:0]
    14 3V66_0 SDRAM_0 11,12
    GMCH_3V66 R49 22 3V66_1 8 3V66 45 DRAM_1 R27 22 MEMCLK1
    8 3V66_1 SDRAM_1
    22 43 22 R37 MEMCLK2
    PCLK_0/ICH R43 PCI_0 11
    ICS9250-10 SDRAM_2
    42
    DRAM_2

    DRAM_3 R28 22 MEMCLK3


    13 PCI_0/ICH SDRAM_3
    16
    PCLK_1 R50 33 PCI_1 12 PCI_1
    CK-Whitney SDRAM_4
    40 DRAM_4 22 R38 MEMCLK4
    Memory
    PCLK_2 33 R44 PCI_2 13 39 DRAM_5 R29 22 MEMCLK5
    17 PCI_2 SDRAM_5
    PCLK_3 R52 33 PCI_3 15 37 DRAM_6 22 R39 MEMCLK6
    17 PCI_3 PCI SDRAM_6
    PCLK_4 33 R45 PCI_4 16 36 DRAM_7 R30 22 MEMCLK7
    VCC3_3 18 PCI_4 SDRAM_7
    PCLK_5 R51 33 PCI_5 18 22
    27 PCI_5
    PCLK_6 33 R46 PCI_6 19 34 DCLK R40 DCLK_WR VCC2_5
    15 PCI_6 DCLK 8
    33 20 22
    PCI_7
    32 CK_PWRDN# 32
    2

    L18 PWRDWN#
    USBCLK R53 USB_0 25 31 CK_SMBCLK
    14 USB_0 SCLK 25

    2
    DOTCLK R47 33 USB_1 26 USB 30 CK_SMBDATA L15
    9 USB_1 SDATA 25 B
    B 22 29
    SEL1
    1

    28 FREQSEL
    L_CKVDDA SEL0 4,9

    1
    22 L_VCC2_5
    C52 C53 VDD_A
    VDD2_5[0]
    51
    53
    0.1UF .001UF VDD2_5[1]
    23

    1
    VSS_A
    56 C46 C47 C56
    VSS3_3[0]
    VSS3_3[1]
    VSS3_3[2]
    VSS3_3[3]
    VSS3_3[4]
    VSS3_3[5]
    VSS3_3[6]
    VSS3_3[7]

    +
    VSS2_5[1]
    48
    VSS2_5[0]

    2
    .001UF 0.1UF 4.7UF
    Minimize Stub Length from
    5
    6
    14
    17
    24
    35
    41
    47

    CLK14 trace to JP6.

    JP6

    APIC Clk Strap JP6


    JP1

    A
    A
    16MHz in R23

    33MHz out* 10K

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    CLOCK SYNTHESIZER
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 12-8-1998_13:05 6 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1
    VCC1_8
    VTT1_5 82810-DC100, PART 1: HOST INTERFACE

    U18
    B20

    V17
    V16
    V15
    V14
    V10

    F17
    F16
    F14
    F10
    U2

    P6

    V9
    V8
    V7

    F8
    F7
    R80 75 Y5 HD#0 HD#[63:0]
    HD0# 3,5

    VCC_CORE[0]
    VCC_CORE[1]
    VCC_CORE[2]
    VCC_CORE[3]
    VCC_CORE[4]
    VCC_CORE[5]
    VCC_CORE[6]
    VCC_CORE[7]
    VCC_CORE[8]
    VCC_CORE[9]
    VCC_CORE[10]
    VCC_CORE[11]
    VCC_CORE[12]
    VCC_CORE[13]
    VCC1_8[0]
    VCC1_8[1]
    VCC1_8[2]
    1% HD1#
    W5 HD#1

    HD2#
    W8 HD#2

    HD3#
    AA6 HD#3
    GMCHGTLREF M5 D
    D GTLREFA AB6 HD#4
    W13 HD4#
    GTLREFB Y6 HD#5
    R81 150 HD5#
    C166 C167 AA5 HD#6
    GMCHHCLK V6 HD6#
    1% 6 HTCLK HD#7
    AA9
    0.1UF .001UF PCIRST# M2 HD7#
    13,17,18,24,27 RESETB V5 HD#8
    CPURST# AB4 HD8#
    4,5 CPURST# AC7 HD#9
    HLOCK# P5 HD9#
    4,5 HLOCK# AB7 HD#10
    DEFER# R3 HD10#
    4,5 DEFER# AC8 HD#11
    HADS# N3 HD11#
    4,5 ADS# AA7 HD#12
    BNR# T3 HD12#
    4,5 BNR# Y8 HD#13
    HD13#
    4,5
    4,5
    BPRI#
    DBSY#
    T1
    M4
    BPRI#
    DBSY#
    INTEL 82810-DC100 HD14#
    W7
    AC6
    HD#14
    HD#15
    DRDY# N1 HD15#
    4,5 DRDY# W9 HD#16
    HIT# P1 HD16#
    4,5
    4,5
    HITM# R1
    HIT#
    HITM#
    PART1 HD17#
    HD18#
    AC9
    Y7
    HD#17
    HD#18
    HTRDY# N4
    4,5 HTRDY# AA10 HD#19
    HD19#

    3,5
    HA#[31:3]
    HA#3
    HA#4
    U5
    U1
    HA3# HOST INTERFACE HD20#
    HD21#
    AB8
    AC10
    HD#20
    HD#21
    HA4# AB13 HD#22
    C HA#5 V4 HD22#
    HA5# AB10 HD#23 C
    HA#6 V1 HD23#
    HA6# AB9 HD#24
    HA#7 T4 HD24#
    HA7# AB11 HD#25
    HA#8 U2 HD25#
    HA8# Y10 HD#26
    HA#9 U3 HD26#
    HA9# AB16 HD#27
    HA#10 W1 HD27#
    HA10# AB12 HD#28
    HA#11 U4 HD28#
    HA11# Y11 HD#29
    HA#12 W3 HD29#
    HA12# Y9 HD#30
    HA#13 W4 HD30#
    HA13# AC12 HD#31
    HA#14 T5 HD31#
    HA14# W11 HD#32
    HA#15 W2 HD32#
    HA15# AC11 HD#33
    HA#16 V2 HD33#
    HA16# W12 HD#34
    HA#17 AC2 HD34#
    HA17# AA11 HD#35
    HA#18 AA2 HD35#
    HA18# AA13 HD#36
    HA#19 Y3 HD36#
    HA19# Y13 HD#37
    HA#20 AB3 HD37#
    HA20# Y12 HD#38
    HA#21 AA1 HD38#
    HA21# AC14 HD#39
    HA#22 AB2 HD39#
    HA22# AA15 HD#40
    HA#23 AC3 HD40#
    HA23# AC15 HD#41
    HA#24 AA3 HD41# B
    B HA24# Y14 HD#42
    HA#25 Y2 HD42#
    HA25# AC13 HD#43
    HA#26 AB5 HD43#
    HA26# AA14 HD#44
    HA#27 AC4 HD44#
    HA27# AB14 HD#45
    HA#28 Y1 HD45#
    HA28# Y17 HD#46
    HA#29 AC5 HD46#
    HA29# Y15 HD#47
    HA#30 Y4 HD47#
    HA30# AC17 HD#48
    HA#31 AB1 HD48#
    HA31# AC16 HD#49
    HD49#
    HREQ#[4:0] AA18 HD#50
    HREQ#0 R4 HD50#
    3 HREQ0# AB15 HD#51
    HREQ#1 T2 HD51#
    HREQ1# W15 HD#52
    HREQ#2 P4 HD52#
    HREQ2# AB18 HD#53
    HREQ#3 R2 HD53#
    HREQ3# W17 HD#54
    HREQ#4 R5 HD54#
    HREQ4# AA17 HD#55
    HD55#
    RS#[2:0] W18 HD#56
    RS#0 N5 HD56#
    3 RS0# W16 HD#57
    RS#1 P2 HD57#
    RS1# AC19 HD#58
    RS#2 N2 HD58#
    RS2# Y16 HD#59
    A HD59#
    AB19 HD#60 A
    HD60#
    Y18 HD#61
    HD61#
    VSS[10]
    VSS[11]
    VSS[12]
    VSS[13]
    VSS[14]
    VSS[15]
    VSS[16]
    VSS[17]
    VSS[18]
    VSS[19]
    VSS[20]
    VSS[21]
    VSS[22]
    VSS[23]
    VSS[0]
    VSS[1]
    VSS[2]
    VSS[3]
    VSS[4]
    VSS[5]
    VSS[6]
    VSS[7]
    VSS[8]
    VSS[9]

    AC18 HD#62
    HD62#
    AB17 HD#63
    Do Not Stuff C161 C161 HD63#
    Place Site w/in 0.5"
    N22

    C19

    N14
    N13
    Y22
    V18

    J22
    Y19

    E22
    K14
    K13
    K12
    K11
    K10

    M14
    M13
    M12
    M11
    M10
    L14
    L13
    L12
    L11
    L10

    REV:
    of clock ball (V6). 18PF TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    82810-DC100 : HOST INTERFACE
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 7 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    VCC1_8 VCC3SBY VCC3_3

    82810-DC100 PART 2: SYSTEM MEMORY


    AND HUB INTERFACE Place Resistor as Close
    R82

    G21
    C11

    C15

    R18
    F15

    F18
    L21

    J18
    as possible to GMCH

    G3
    D4

    C7

    K6

    B2
    F9

    F6
    L3
    40 U2
    SM_MD[63:0]
    1% E17 SM_MD0 11,12
    SMD0

    VCC3_3[0]
    VCC3_3[1]
    VCC3_3[2]
    VCC3_3[3]
    VCC3_3[4]
    VCC3_3[5]
    VCC3_3[6]
    VCC3_3[7]
    VCC3_3[8]
    VCC3_3[9]
    VCC3_3[10]

    VCC3_3[11]
    VCC3_3[12]
    VCC3_3[13]
    VCC3_3[14]
    VCC3_3[15]
    SM_MAA[11:0] C16 SM_MD1
    SM_MAA0 C9 SMD1
    11,12 SMAA0 D15 SM_MD2
    SM_MAA1 E7 SMD2
    SMAA1 D17 SM_MD3 D
    D SM_MAA2 A9 SMD3
    SMAA2 C17 SM_MD4
    SM_MAA3 D7 SMD4
    SMAA3 A17 SM_MD5
    SM_MAA4 8 1 R_MAA4 B8 SMD5
    SMAA4 A16 SM_MD6
    SM_MAA5 7 2 R_MAA5 A8 SMD6
    SMAA5 B16 SM_MD7
    SM_MAA6 6 3 R_MAA6 B7 SMD7
    SMAA6 A15 SM_MD8
    SM_MAA7 5 4 R_MAA7 A7 SMD8
    SMAA7 C14 SM_MD9
    SM_MAA8 RP70 10 OHMS D6 SMD9
    SMAA8 B14 SM_MD10
    RP70 and RP71 should be placed SM_MAA9 C6 SMD10
    within 0.5" of the GMCH balls. SMAA9 A14 SM_MD11
    SM_MAA10 D5 SMD11
    SMAA10
    SM_MAA11 A5
    SMAA11 INTEL 82810-DC100 SMD12
    SMD13
    D13
    C13
    SM_MD12
    SM_MD13
    SM_MAB[7:4]# A13 SM_MD14
    SM_MAB4# 8 1 R_MAB#4 B6 SMD14
    Place HUBREF Generation 12 SMAB4# A12 SM_MD15
    Circuit in middle of
    GMCH and ICH. VCC1_8
    SM_MAB5#
    SM_MAB6#
    7

    6
    2

    3
    R_MAB#5

    R_MAB#6
    A6
    B4
    SMAB5# PART 2 SMD15
    SMD16
    E1 SM_MD16
    SMAB6# F2 SM_MD17
    SM_MAB7# 5 4 R_MAB#7 A4 SMD17
    C300 SMAB7# G4 SM_MD18
    SYSTEM MEMORY SMD18
    RP71 10 OHMS
    SM_DQM[7:0] G1 SM_MD19
    HUBREF_CV SM_DQM0 C10 SMD19
    11,12 SDQM0 D3 SM_MD20
    470PF SM_DQM1 A10 SMD20
    SDQM1

    C R177 R130
    SM_DQM2 B1
    SDQM2 AND SMD21
    SMD22
    H2
    H1
    SM_MD21
    SM_MD22
    SM_DQM3 D1
    SDQM3
    C
    56 301 J4 SM_MD23
    1% SM_DQM4
    SM_DQM5
    B10
    D9
    SDQM4
    SDQM5
    HUB INTERFACE SMD23
    SMD24
    J1 SM_MD24
    K2 SM_MD25
    HUBREF SM_DQM6 C1 SMD25
    8,13 SDQM6 K1 SM_MD26
    SM_DQM7 D2 SMD26
    SDQM7 K3 SM_MD27
    SMD27
    R176 R131 SM_BS[1:0] L1 SM_MD28
    SM_BS0 C5 SMD28
    56 301 11,12 SBS0 L2 SM_MD29
    1% SM_BS1 E5 SMD29
    SBS1 M3 SM_MD30
    SMD30
    C299
    SM_CS#[3:0] K4 SM_MD31
    SM_CS#0 C4 SMD31
    11,12 SCS0# D16 SM_MD32
    HUBREF_CG SM_CS#1 C3 SMD32
    470PF SCS1# E15 SM_MD33
    SM_CS#2 B3 SMD33
    SCS2# D14 SM_MD34
    SM_CS#3 C2 SMD34
    SCS3# E14 SM_MD35
    SMD35
    E13 SM_MD36
    SM_RAS# D8 SMD36
    11,12 SRAS# E12 SM_MD37
    SM_CAS# A11 SMD37
    11,12 SCAS# D12 SM_MD38
    SM_WE# B11 SMD38
    11,12 SWE# B15 SM_MD39
    SMD39
    SM_CKE[1:0] B12 SM_MD40
    SM_CKE0 A3 SMD40
    11,12 SCKE0 C12 SM_MD41 B
    B SM_CKE1 A2 SMD41
    SCKE1 D11 SM_MD42
    0K SMD42
    DCLK_WR SCLK E6
    6 SCLK D10 SM_MD43
    R31 SMD43
    E10 SM_MD44
    GMCH_3V66 D19 SMD44
    C168 6,8 HLCLK E9 SM_MD45
    HL[10:0] HL0 C21 SMD45
    13 HL0 E8 SM_MD46
    HL1 B23 SMD46
    22PF HL1 C8 SM_MD47
    HL2 B22 SMD47
    HL2 F3 SM_MD48
    HL3 A23 SMD48
    HL3 F1 SM_MD49
    HL4 B19 SMD49
    HL4 G2 SM_MD50
    HL5 B18 SMD50
    HL5 H3 SM_MD51
    HL6 C18 SMD51
    HL6 HUB I/F E4 SM_MD52
    HL7 A18 SMD52
    HL7 E3 SM_MD53
    HL8 A22 SMD53
    HL8 F4 SM_MD54
    HL9 C20 SMD54
    HL9 J3 SM_MD55
    HL10 A19 SMD55
    HL10 F5 SM_MD56
    HUBREF D20 SMD56
    HUBREF G5 SM_MD57
    HLSTB A21 SMD57
    8,13 HLSTB H5 SM_MD58
    HLSTB# A20 SMD58
    A 8,13 HLSTB# H4 SM_MD59
    GHCOMP D18 SMD59 A
    HCOMP H6 SM_MD60
    SMD60
    J5 SM_MD61
    C241 SMD61
    VSS[24]
    VSS[25]
    VSS[26]
    VSS[27]
    VSS[28]
    VSS[29]
    VSS[30]
    VSS[31]
    VSS[32]
    VSS[33]
    VSS[34]
    VSS[35]
    VSS[36]
    VSS[37]
    VSS[38]
    VSS[39]
    VSS[40]
    VSS[41]
    VSS[42]
    VSS[43]
    VSS[44]
    VSS[45]

    K5 SM_MD62
    Place C241 as close SMD62
    as possible to GMCH L5 SM_MD63
    0.1UF SMD63
    C236 REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    N12
    N11
    N10

    AA12
    AA16

    V3

    P3

    J2
    P14
    P13
    P12
    P11
    P10
    AC1

    W6
    W10
    W14

    M1
    AA4
    AA8

    R6

    L4

    18PF 1.3
    82810-DC100: SYSTEM MEMORY AND HUB
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 5-26-1999_17:13 8 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1
    VCC1_8 VCC1_8

    82810-DC100, PART 3: DISPLAY CACHE L24


    AND VIDEO INTERFACE VCCDACA

    33UF 20%
    68NH-0.3A

    1
    C217 C216 C222

    +
    AC20

    AB23
    AB21
    E19
    U6
    U2 0.01UF 0.1UF

    2
    VCCBA

    VCCDACA1
    VCCDACA2
    VCCHA

    VCCDA
    DC_CS# L20
    10 LCS#
    D
    D Y21 FTD0 FTD[11:0]
    DC_DQM[3:0] DC_DQM0 P21 LTVDATA0 24
    10 LDQM0 Y20 FTD1
    DC_DQM1 R23 LTVDATA1
    LDQM1 W23 FTD2
    DC_DQM2 C23 LTVDATA2
    LDQM2 W22 FTD3
    DC_DQM3 F20 LTVDATA3
    LDQM3 W21 FTD4
    GMCH RESET STRAPS DC_RAS# K19
    LTVDATA4
    V23 FTD5
    10 LRAS# VIDEO DIGITAL OUT LTVDATA5
    DC_CAS# K20 U23 FTD6
    10 LCAS# LTVDATA6
    VCOREDET DC_WE# J19 U22 FTD7
    4 10 LWE# INTERFACE LTVDATA7
    FREQSEL U21 FTD8
    4,6 DC_MA[11:0] DC_MA0 M19 LTVDATA8
    10 LMA0 T23 FTD9
    DC_MA1 P19 LTVDATA9
    VCC3_3 LMA1 T22 FTD10
    DC_MA2 P20 LTVDATA10
    LMA2 T21 FTD11
    DC_MA3 N19 LTVDATA11
    LMA3 V19 FTBLNK#
    DC_MA4 J21 BLANK# 24
    LMA4 U20 SL_STALL
    TVCLKIN/SL_STALL 24
    DC_MA5
    DC_MA6
    H19
    H20
    LMA5
    INTEL 82810-DC100 CLKOUT0
    V21 FTCLK0
    24
    8

    RP46 RP48 LMA6 V22 FTCLK1


    DC_MA7 H18 CLKOUT1 24
    LMA7 V20 FTVSYNC
    24
    DC_MA8
    DC_MA9
    G19
    F19
    LMA8
    LMA9
    PART3 TVVSYNC
    TVHSYNC
    U19 FTHSYNC
    24
    C 10K 10K
    DC_MA10 M20
    LMA10 C
    1

    T19 3VFTSCL
    LTVCL 24,25

    DC_MD[31:0]
    DC_MA11 L19
    LMA11 DISPLAY CACHE LTVDA
    T20 3VFTSDA
    24,25
    DC_MD0 M22
    GRS_PU28

    GRS_PU26

    GRS_PU31

    GRS_PU30

    10 LMD0
    DC_MD1
    DC_MD2
    M21
    L23
    LMD1
    LMD2
    AND
    JP16 DC_MD31 DC_MD3 L22
    9,10 LMD3
    DC_MD4 K21
    JP15
    DC_MD30
    9,10 DC_MD5 K23
    LMD4
    LMD5
    VIDEO INTERFACE
    DC_MD29 DC_MD6 R19
    9,10 LMD6
    DC_MD7 R20
    LMD7
    JP14 DC_MD28
    9,10 DC_MD8 R22
    LMD8
    DC_MD9 R21
    LMD9
    DC_MD27
    9,10 DC_MD10 P23
    LMD10
    JP13 DC_MD26 DC_MD11 P22
    LMD11
    9,10
    DC_MD12 N23
    LMD12
    Function Jumper Function DC_MD13 N21
    LMD13
    DC_MD14 N20
    IN=XOR TREE DC_MD15 M23
    LMD14
    LMD15
    XOR JP16 OUT=NORMAL* DC_MD16 F23
    LMD16 B
    B DC_MD17 E20
    IN=TriState Mode LMD17
    DC_MD18 E21
    LMD18
    Tri-State JP15 OUT=NORMAL* DC_MD19 E23
    LMD19
    DISPLAY CACHE DDCDA
    W19 3VDDCDA
    25
    W20 3VDDCCL
    DC_MD20 D22
    LMD20
    INTERFACE DDCCL 25
    System Bus READS System Bus DC_MD21 D23
    LMD21 AA21 DOTCLK
    Frequency N/A Frequency DC_MD22 D21
    LMD22
    DCLKREF
    Y23
    6
    DC_MD23 C22 IWASTE
    LMD23 AA23 IREFPD
    IREF
    IN=IO Queue Depth 1 DC_MD24 H21
    LMD24
    DC_MD25 H22
    IOQD JP14 OUT=IO Queue Depth 4* DC_MD26 H23
    LMD25
    VSYNC
    AA20 CRT_VSYNC
    25
    LMD26 GRAPHICS INTERFACE AB20 CRT_HSYNC
    VCORE Detects Type of Processor DC_MD27 G20
    LMD27
    HSYNC
    AC21 VID_RED
    25
    DC_MD28 G22 RED 25
    Detect N/A I/O Buffers DC_MD29 G23
    LMD28
    GREEN
    AC22 VID_GREEN
    25
    LMD29 VID_BLUE
    RESVD JP13 TBD DC_MD30 F21
    LMD30
    BLUE
    AC23
    25
    DC_MD31 F22
    LMD31
    R127 R125 Place as close as
    DC_CLK R_LTCLK K22
    174 Possible to GMCH
    10 LTCLK
    22 1% and via straight to C379 Do Not Stuff C379
    R128 VSS plane. Place Site w/in 0.5"
    A RCLK J20
    LRCLK
    R129 18PF of clock ball (AA21). A
    OCLK_FB 0K OCLK J23
    LOCLK
    33
    Place R129 within 0.5" of the GMCH Ball.
    VSSDACA
    VSS[46]
    VSS[47]
    VSS[48]
    VSS[49]
    VSS[50]
    VSS[51]
    VSS[52]
    VSS[53]
    VSS[54]
    VSS[55]
    VSS[56]
    VSS[57]
    VSS[58]
    VSS[59]
    VSS[60]
    VSS[61]
    VSSHA

    VSSDA
    VSSBA

    C238
    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    Do Not Populate C238 1.3
    T6

    J6
    G6

    T18
    AA19

    AA22

    AB22
    E18

    E2
    A1
    B5
    B9
    E11
    B13
    E16
    B17
    B21
    G18
    K18
    P18

    22PF 82810-DC100: DISPLAY CACHE AND VIDEO


    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 5-26-1999_17:09 9 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    4MB Display Cache

    D
    D

    VCC3_3 VCC3_3

    U9

    25

    13
    38
    44
    U8

    7
    25

    13
    38
    44
    1

    7
    DC_MA[11:0] DC_MD[31:0]

    VDD_1
    VDD_2

    VDDQ_1
    VDDQ_2
    VDDQ_3
    VDDQ_4
    9 9

    VDD_1
    VDD_2

    VDDQ_1
    VDDQ_2
    VDDQ_3
    VDDQ_4
    9 DC_MA0 21 2 DC_MD16 DC_DQM[3:0]
    DC_MA0 21 2 DC_MD0 A0 DQ0
    A0 DQ0 DC_MA1 22 3 DC_MD17 9
    VCC3_3 DC_MA1 22 3 DC_MD1 9 A1 DQ1
    A1 DQ1 DC_MA2 23 5 DC_MD18
    DC_MA2 23 5 DC_MD2 9 A2 DQ2
    A2 DQ2 DC_MA3 24 6 DC_MD19
    DC_MA3 24 6 DC_MD3 9 A3 DQ3
    A3 DQ3 DC_MA4 27 8 DC_MD20
    C DC_MA4 27 8 DC_MD4 9 A4 DQ4
    A4 DQ4 DC_MA5 28 9 DC_MD21 C
    DC_MA5 28 9 DC_MD5 9 A5 DQ5
    A5 DQ5 DC_MA6 29 11 DC_MD22
    DC_MA6 29 11 DC_MD6 9 A6 DQ6
    A6 DQ6 DC_MA7 30 12 DC_MD23
    DC_MA7 30 12 DC_MD7 9 A7 DQ7
    A7 DQ7 DC_MA8 31 39 DC_MD24
    R114 DC_MA8 DC_MD8 9 A8 DQ8
    31 39
    A8 DQ8 DC_MA9 DC_MD25

    50-PIN TSOP
    4.7K 32 40
    DC_MA9 DC_MD9 9 A9 DQ9
    32
    A9 50-PIN TSOP DQ9
    40
    9 DC_MA10 20
    A10 DQ10
    42 DC_MD26
    DC_MA10 20 42 DC_MD10

    SDRAM
    A10 DQ10 DC_MA11 19 43 DC_MD27
    SDRAM

    DC_MA11 19 43 DC_MD11 9 A11 DQ11


    A11 DQ11 45 DC_MD28
    45 DC_MD12 DQ12
    DQ12 DC_CLK 35 46 DC_MD29
    DC_CLK 35 46 DC_MD13 9 CLK DQ13
    9 CLK DQ13 DC_CKE 34 48 DC_MD30
    DC_CKE 34 48 DC_MD14 10 CKE DQ14
    CKE DQ14 49 DC_MD31
    49 DC_MD15 DQ15
    DQ15 DC_CS# 18
    DC_CS# 18 9 CS#
    9 CS# DC_RAS# 17 36 DC_DQM3
    DC_RAS# 17 36 DC_DQM1 9 RAS# UDQM
    9 RAS# UDQM DC_CAS# 16 14 DC_DQM2
    DC_CAS# 16 14 DC_DQM0 9 CAS# LDQM
    9 CAS# LDQM DC_WE# 15
    DC_WE# 15 9 WE#
    9 WE#

    33
    33 NC_1
    NC_1 37
    NC_2

    VSSQ_4
    VSSQ_3
    VSSQ_2
    VSSQ_1
    37
    NC_2

    VSS_2
    VSS_1
    VSSQ_4
    VSSQ_3
    VSSQ_2
    VSSQ_1

    VSS_2
    VSS_1

    B
    B

    4
    10
    41
    47

    26
    50
    4
    10
    41
    47

    26
    50

    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    DISPLAY CACHE
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 10 OF 40
    8 7 6 5 4 3 2 1
    A
    B
    C
    D
    8

    8
    8
    8
    8
    6
    8,12

    SM_BS[1:0]
    VCC3SBY

    MEMCLK[7:0]

    SM_DQM[7:0]
    SM_MAA[11:0]
    SM_MD[63:0]

    18
    26
    40
    41
    90
    49
    59
    73
    84

    6
    102
    110
    124
    133
    143
    157
    168

    J11
    DQ0 2 SM_MD0

    VCC1
    VCC2
    VCC3
    VCC4
    VCC5
    VCC6
    VCC7
    VCC8
    VCC9
    VCC10
    VCC11
    VCC12
    VCC13
    VCC14
    VCC15
    VCC16
    VCC17
    DQ1 3 SM_MD1

    7
    7

    MEMCLK0 42 DQ2 4 SM_MD2


    CLK0
    SYSTEM MEMORY

    MEMCLK1 125 DQ3 5 SM_MD3


    CLK1
    MEMCLK2 79 DQ4 7 SM_MD4
    CLK2
    MEMCLK3 163 DQ5 8 SM_MD5
    CLK3

    DQ6 9 SM_MD6
    SM_MAA0 33 DQ7 10 SM_MD7
    A0
    SM_MAA1 117 DQ8 11 SM_MD8
    A1
    SM_MAA2 34 DQ9 13 SM_MD9
    A2
    SM_MAA3 118 DQ10 14 SM_MD10
    A3
    SM_MAA4 35 DQ11 15 SM_MD11
    A4

    DIMM0
    SM_MAA5 119 DQ12 16 SM_MD12
    A5
    SM_MAA6 36 DQ13 17 SM_MD13
    A6
    SM_MAA7 120 DQ14 19 SM_MD14
    A7
    SM_MAA8 37 DQ15 20 SM_MD15
    A8

    6
    6

    SM_MAA9 121 DQ16 55 SM_MD16


    A9
    SM_MAA10 38 DQ17 56 SM_MD17
    A10
    SM_MAA11 123 DQ18 57 SM_MD18
    A11
    126 DQ19 58 SM_MD19
    A12
    SLAVE ADDRESS = 1010000B

    132 60 SM_MD20

    8
    8
    8
    8
    8
    DQ20

    12,14,25,28,33
    12,14,25,28,33
    A13

    DQ21 65 SM_MD21
    SM_BS0 122 DQ22 66 SM_MD22
    BA0
    SM_BS1 39 DQ23 67 SM_MD23
    BA1

    DQ24 69 SM_MD24
    SM_DQM0 28 70 SM_MD25

    SMBCLK
    SM_WE#
    DQMB0 DQ25

    SM_RAS#
    SM_CAS#

    SMBDATA
    SM_DQM1 29 DQ26 71 SM_MD26

    SM_CS#[3:0]
    DQMB1

    SM_CKE[1:0]
    SM_DQM2 46 DQ27 72 SM_MD27
    DQMB2
    SM_DQM3 47
    DQMB3 DQ28 74 SM_MD28
    SM_DQM4 112
    DQMB4 DQ29 75 SM_MD29
    5

    5
    SM_DQM5 113
    DQMB5 DQ30 76 SM_MD30
    SM_DQM6 130
    DQMB6 DQ31 77 SM_MD31
    SM_DQM7 131
    DQMB7 DQ32 86 SM_MD32

    DQ33 87 SM_MD33
    SM_CS#0 30
    S0# DQ34 88 SM_MD34
    SM_CS#1 114
    S1# DQ35 89 SM_MD35
    45
    S2# DQ36 91 SM_MD36
    129
    S3# DQ37 92 SM_MD37
    27
    WE# DQ38 93 SM_MD38
    111
    CAS# DQ39 94 SM_MD39
    115
    RAS# DQ40 95 SM_MD40
    DQ41 97 SM_MD41
    SM_CKE0 128
    CKE0 DQ42 98 SM_MD42
    SM_CKE1 63
    CKE1 DQ43 99 SM_MD43

    4
    4

    DQ44 100 SM_MD44


    82
    SMBDATA DQ45 101 SM_MD45
    83
    SMBCLK DQ46 103 SM_MD46

    DQ47 104 SM_MD47


    147
    REGE DQ48 139 SM_MD48
    165
    SA0 DQ49 140 SM_MD49
    166
    SA1 DQ50 141 SM_MD50
    167
    SA2 DQ51 142 SM_MD51
    DQ52 144 SM_MD52
    81
    WP SM_MD53
    DQ53 149

    24
    NC1 DQ54 150 SM_MD54
    25
    NC2 DQ55 151 SM_MD55
    SAO_PU

    31
    NC3 DQ56 153 SM_MD56
    44
    NC4 DQ57 154 SM_MD57

    3
    3

    48
    NC5 DQ58 155 SM_MD58
    12

    50
    NC6 DQ59 156 SM_MD59
    51
    NC7 DQ60 158 SM_MD60
    61
    NC8 DQ61 159 SM_MD61
    62
    NC9 DQ62 160 SM_MD62
    80
    NC10 DQ63 161 SM_MD63
    108 ECC0 21
    NC11
    R

    109 ECC1 22
    NC12
    134 ECC2 52
    NC13
    135 ECC3 53
    NC14
    145 ECC4 105
    NC15
    146 ECC5 106
    NC16
    164 ECC6 136
    NC17
    2
    2

    PCD PLATFORM DESIGN

    137
    1900 PRAIRIE CITY ROAD

    ECC7
    VSS10
    VSS11
    VSS12
    VSS13
    VSS14
    VSS15
    VSS16
    VSS17
    VSS18

    VSS1
    VSS2
    VSS3
    VSS4
    VSS5
    VSS6
    VSS7
    VSS8
    VSS9

    FOLSOM, CALIFORNIA 95630


    1
    12
    23
    32
    43
    54
    64
    68
    78
    85
    96
    107
    116
    127
    138
    148
    152
    162

    SYSTEM MEMORY: DIMM0


    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

    DRAWN BY:

    LAST REVISED:
    INTEL CORPORATION

    12-8-1998_13:14
    PLATFORM COMPONENTS DIVISION

    1
    1

    11
    SHEET:
    PROJECT:

    OF
    CHIPSET
    1.3
    REV:

    INTEL(R) 810

    40
    A
    B
    C
    D
    A
    B
    C
    D
    8

    8
    8
    8
    8
    8
    6
    8,11
    SYSTEM MEMORY

    7
    7

    VCC3SBY

    SM_BS[1:0]
    MEMCLK[7:0]

    SM_DQM[7:0]
    SM_MAB[7:4]#
    SM_MAA[11:0]
    SM_MD[63:0]

    18
    26
    40
    41
    90
    49
    59
    73
    84

    6
    102
    110
    124
    133
    143
    157
    168

    J13
    DQ0 2 SM_MD0

    VCC1
    VCC2
    VCC3
    VCC4
    VCC5
    VCC6
    VCC7
    VCC8
    VCC9
    VCC10
    VCC11
    VCC12
    VCC13
    VCC14
    VCC15
    VCC16
    VCC17
    DQ1 3 SM_MD1
    MEMCLK4 42 DQ2 4 SM_MD2
    CLK0
    MEMCLK5 125 DQ3 5 SM_MD3
    CLK1
    MEMCLK6 79 DQ4 7 SM_MD4
    CLK2
    MEMCLK7 163 DQ5 8 SM_MD5
    CLK3

    DQ6 9 SM_MD6
    SM_MAA0 33 DQ7 10 SM_MD7
    A0
    SM_MAA1 117 DQ8 11 SM_MD8
    A1
    SM_MAA2 34 DQ9 13 SM_MD9
    A2
    SM_MAA3 118 DQ10 14 SM_MD10
    A3

    6
    6

    SM_MAB4# 35 DQ11 15 SM_MD11


    A4
    DIMM1

    SM_MAB5# 119 DQ12 16 SM_MD12


    A5
    SM_MAB6# 36 DQ13 17 SM_MD13
    A6
    SM_MAB7# 120 DQ14 19 SM_MD14
    A7
    SM_MAA8 37 DQ15 20 SM_MD15
    A8
    SM_MAA9 121 DQ16 55 SM_MD16
    A9
    SM_MAA10 38 DQ17 56 SM_MD17
    A10
    SM_MAA11 123
    A11 DQ18 57 SM_MD18
    126 DQ19 58 SM_MD19
    A12
    SLAVE ADDRESS = 1010001B

    132 DQ20 60 SM_MD20


    A13

    DQ21 65 SM_MD21
    SM_BS0 122 DQ22 66 SM_MD22
    BA0

    8
    8
    8
    8

    11,14,25,28,33
    11,14,25,28,33
    SM_BS1 39 DQ23 67 SM_MD23
    BA1

    DQ24 69 SM_MD24
    5

    5
    SM_DQM0 28 DQ25 70 SM_MD25
    DQMB0
    SM_DQM1 29 DQ26 71 SM_MD26
    DQMB1
    SM_DQM2 46 DQ27 72 SM_MD27
    DQMB2

    SMBCLK
    SM_WE#

    SM_RAS#
    SM_CAS#
    SM_DQM3 47 74 SM_MD28

    SMBDATA
    DQMB3 DQ28

    SM_CS#[3:0]

    SM_CKE[1:0]
    SM_DQM4 112
    DQMB4 DQ29 75 SM_MD29
    SM_DQM5 113
    DQMB5 DQ30 76 SM_MD30
    SM_DQM6 130
    DQMB6 DQ31 77 SM_MD31
    SM_DQM7 131
    DQMB7 DQ32 86 SM_MD32
    DQ33 87 SM_MD33
    30 DQ34 88 SM_MD34
    S0#
    114 DQ35 89 SM_MD35
    S1#
    SM_CS#2 45
    S2# DQ36 91 SM_MD36
    SM_CS#3 129
    S3# DQ37 92 SM_MD37
    27 DQ38 93 SM_MD38
    WE#

    4
    4

    111 DQ39 94 SM_MD39


    CAS#
    115 DQ40 95 SM_MD40
    RAS#

    DQ41 97 SM_MD41
    SM_CKE0 128
    CKE0 DQ42 98 SM_MD42
    SM_CKE1 63
    CKE1 DQ43 99 SM_MD43

    DQ44 100 SM_MD44


    82 DQ45 101 SM_MD45
    SMBDATA
    83 DQ46 103 SM_MD46
    SMBCLK

    DQ47 104 SM_MD47


    147
    REGE DQ48 139 SM_MD48
    165
    SA0 DQ49 140 SM_MD49
    166
    SA1 DQ50 141 SM_MD50
    167
    SA2 DQ51 142 SM_MD51
    SAO_PU

    DQ52 144 SM_MD52

    3
    3

    81
    WP SM_MD53
    DQ53 149

    24
    NC1 DQ54 150 SM_MD54
    25
    NC2 DQ55 151 SM_MD55
    31
    NC3 DQ56 153 SM_MD56
    44
    NC4 DQ57 154 SM_MD57
    48
    NC5 DQ58 155 SM_MD58
    50
    NC6 DQ59 156 SM_MD59
    R

    51
    NC7 DQ60 158 SM_MD60
    61
    NC8 DQ61 159 SM_MD61
    62
    NC9 DQ62 160 SM_MD62
    80
    NC10 DQ63 161 SM_MD63
    108 ECC0 21
    NC11
    109 ECC1 22
    NC12
    2
    2

    PCD PLATFORM DESIGN

    134 52
    1900 PRAIRIE CITY ROAD

    NC13 ECC2
    FOLSOM, CALIFORNIA 95630

    135 ECC3 53
    NC14
    145 ECC4 105
    NC15
    146 ECC5 106
    NC16
    164 ECC6 136
    NC17

    ECC7 137
    SYSTEM MEMORY: DIMM1
    VSS10
    VSS11
    VSS12
    VSS13
    VSS14
    VSS15
    VSS16
    VSS17
    VSS18

    VSS1
    VSS2
    VSS3
    VSS4
    VSS5
    VSS6
    VSS7
    VSS8
    VSS9

    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD


    1
    12
    23
    32
    43
    54
    64
    68
    78
    85
    96
    107
    116
    127
    138
    148
    152
    162

    DRAWN BY:

    LAST REVISED:
    R60

    2.2K

    INTEL CORPORATION

    12-8-1998_13:14
    PLATFORM COMPONENTS DIVISION

    1
    1

    VCC3SBY

    12
    SHEET:
    PROJECT:

    OF
    CHIPSET
    1.3
    REV:

    INTEL(R) 810

    40
    A
    B
    C
    D
    8 7 6 5 4 3 2 1

    VCC3_3 VCC1_8
    ICH0, Part 1

    M14

    G13

    G15
    U10
    R13

    C11

    D16

    N13

    H14

    H16
    E13

    K14
    T16

    L15

    J16
    G5

    C8

    N5
    E3

    P6

    A5
    E6
    E5
    T7
    U14

    VCC3_3_1
    VCC3_3_2
    VCC3_3_3
    VCC3_3_4
    VCC3_3_5
    VCC3_3_6
    VCC3_3_7
    VCC3_3_8
    VCC3_3_9
    VCC3_3_10
    VCC3_3_11
    VCC3_3_12
    VCC3_3_13
    VCC3_3_14
    VCC3_3_15
    VCC3_3_16
    VCC3_3_17

    VCC1_8_1
    VCC1_8_2
    VCC1_8_3
    VCC1_8_4
    VCC1_8_5
    VCC1_8_6
    VCC1_8_7
    D
    D
    AD[31:0] AD0 G2 F13 A20M#
    17,18,27 AD0 A20M# 4,33
    AD1 G4
    AD1 CPUSLP# E12 CPUSLP# 4,33
    AD2 F2 F15 FERR#
    AD2 FERR# 4,33
    AD3 F3 B17 IGNNE#
    AD3 IGNNE# 4,33
    AD4 F4 E15 INIT#
    AD4 INIT# 4,15,33
    AD5 F5 E14 INTR
    AD5 CPU INTR 4,33
    AD6 E1
    AD6 NMI B16 NMI
    4,33
    AD7 E2 F14 SMI#
    AD7 SMI# 4,33
    AD8 D1 A17 STPCLK#
    AD8 STPCLK# 4,33
    AD9 D3 A15 RCIN#
    AD9 RCIN# 16,33
    AD10 E4
    AD10 A20GATE B15 A20GATE 16,33
    AD11 C2
    AD11 HL[10:0]
    AD12 C1 D17 HL0 8
    AD12 HL0
    AD13
    AD14
    B1
    D4
    AD13
    AD14
    INTEL 82801AB HL1
    HL2
    E17
    F17
    HL1
    HL2 VCC1_8

    AD15
    AD16
    C3
    A4
    AD15
    AD16
    PART 1 HL3
    HL4
    G16
    J15
    HL3
    HL4
    C AD17 B4
    AD17 HL5 K16 HL5
    C
    AD18 C5 K17 HL6 R182
    AD18
    PCI HUB I/F HL6
    AD19 C6 L17 HL7 40, 1%
    AD19 HL7
    AD20 B5 H15 HL8
    AD20 HL8
    AD21 HL9 Place R182
    E7 J17
    AD21 HL9 as close as
    AD22 A6
    AD22 HL10 J14 HL10 possible to ICH0.
    AD23 B6 G17 HLSTB
    AD23 HLSTB 8
    AD24 D7 H17 HLSTB#
    AD24 HLSTB# 8
    AD25 B8 M17 IHCOMP_PU
    AD25 HCOMP
    AD26 A7 J13 HUBREF
    AD26 HUBREF 8
    AD27 A8
    AD27
    AD28 B7 D10 PIRQ#A
    AD28 PIRQ#A 17,18,27,33 C302
    AD29 C9 A10 PIRQ#B
    AD29 PIRQ#B 17,18,33 0.1UF
    AD30 D8 B10 PIRQ#C
    AD30 PIRQ#C 17,18,33
    AD31 C7 C10 PIRQ#D Place C302 as close
    AD31 PIRQ#D 17,18,33 as possible to ICH0.

    C_BE#[3:0] C_BE#0 D2 P11 IRQ14


    17,18,27 C_BE#0 IRQ IRQ14 19,33
    C_BE#1 B2 N14 IRQ15
    C_BE#1 IRQ15 19,33
    C_BE#2 A3 C16 APICCLK_ICH
    C_BE#2 APICCLK 6
    C_BE#3 D6 C17 APICD1 B
    B C_BE#3 APICD1 4,33
    E16 APICD0
    APICD0 4,33
    PCLK_0/ICH C14 R4 SERIRQ
    6 PCICLK SERIRQ 16,18,33
    FRAME# B3
    17,18,27,33 FRAME#
    DEVSEL# D9 A14 PREQ#0
    17,18,27,33 DEVSEL# REQ#0 17,33
    IRDY# A2 B13 PREQ#1
    17,18,27,33 IRDY# REQ#1 17,33
    TRDY# C4 B12 PREQ#2
    17,18,27,33 TRDY# REQ#2 18,33
    STOP# D5 D12 PREQ#3
    17,18,27,33 STOP# REQ#3 27,33
    PCIRST# J5 PCI
    7,15,16,17,18,19,24,27 PCIRST# A13 PGNT#0
    PLOCK# B9 GNT#0 17,33
    17,18,33 PLOCK# C13 PGNT#1
    PAR A9 GNT#1 17,33 VCC3_3
    17,18,27 PAR A12 PGNT#2
    SERR# A1 GNT#2 18,33
    17,18,27,33 SERR# C12 PGNT#3
    PCI_PME# K1 GNT#3 27,33
    17,18,27 PME#
    R174
    GNT4# A11 RESV0PU
    PCPCI_REQ#A N6 R175
    18,33 REQ#A/GPIO0 B11 RESV1PU 8.2K
    PCPCI_GNT#A P5 REQ4#
    18 GNT#A/GPIO16 R181
    PC/PCI HL11 F16 RESV2PD 8.2K
    REQ#B/GPIO1 P4
    33 REQ#B/GPIO1/REQ5# 0K
    GNT#B/GPIO17 R5
    33 GNT#B/GPIO17/GNT5# Don’t Stuff R181
    A For Test/Debug
    A
    VSS10
    VSS11
    VSS12
    VSS13
    VSS1
    VSS2
    VSS3
    VSS4
    VSS5
    VSS6
    VSS7
    VSS8
    VSS9
    J8

    J9

    H10
    G3

    K8

    K9

    J10
    K10
    G14
    K15
    R2

    H8

    H9

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    ICH0, PART 1
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 2-22-1999_10:37 13 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1
    VCC3SBY VCC3_3 VCC5

    ICH0 VCC3SBY VRTC


    VCC3SBY

    ICH5VREF CR11
    PART 2

    BAT17
    A

    C290 C294 R173


    CR13 R85 and R203 for Test/Debug
    10K 10K U14 C
    1.0UF 0.1UF

    C15
    1K

    G1

    N1

    L1
    A

    C
    BAT17 R85 R203
    R206

    VCCSUS2

    VCCSUS1
    VCCRTC

    5VREF
    1K
    THERM# D14 D
    D C349 33 THRM#
    SLP_S3# K3
    29,32 SLP_S3/GPIO24
    1.0UF JP20 Config SLP_S5# K2 SLP_S5 N12 PDCS#1
    PWROK PDCS#1 19
    1-2 Normal 28,32 J3 PWROK L14 SDCS#1
    PWRBTN# M2 SDCS#1 19
    2-3 Clear CMOS 31
    ICH_RI#
    PWRBTN#
    PDCS#3 U13 PDCS#3
    19
    L3
    VBATC 22 RI# L16 SDCS#3
    JP20 RSMRST# F1 SDCS#3 19
    R219 28,32 RSMRST#
    VBATC_DLY 1 SUS_STAT# L4 PDA[2:0]
    28 SUSSTAT#/GPIO25 R12 PDA0
    8.2K 2 RTCRST# PDA0 19
    1

    CR14 C364 T12 PDA1


    C 3 SMBDATA PDA1
    +

    J1
    JP24_PD

    11,12,25,28,33 SMBDATA P12 PDA2


    SYSTEM PDA2
    BAT17

    SMBCLK J2 SDA[2:0]
    2.2UF 11,12,25,28,33 SMBCLK M16 SDA0
    2

    A
    SMBALERT# M1 SDA0 19
    R216 33 SMBALERT#/GPIO11 M15 SDA1
    SDA1
    1K L13 SDA2
    R202 1K INTRUDER# J4 SDA2
    33 INTRUDER#/GPIO10
    VBAT

    R_VBIAS
    ICH_CLK14 U6 U11 PDREQ
    C347 6 CLK14 PDDREQ 19
    USBCLK U2 P17 SDREQ
    6 CLK48 SDDREQ 19
    ICH_3V66 A16 U12 PDDACK#
    2200PF 6 CLK66 PDDACK# 19
    M13 SDDACK#
    VBIAS H2 SDDACK# 19
    VBIAS R11 PDIOR#
    C RTCX1 H3 PDIOR# 19
    RTCX1 N16 SDIOR# C
    RTCX2 H4 SDIOR# 19
    RTCX2 T11 PDIOW#
    R197 H1 PDIOW# 19
    RTCRST# N15 SDIOW#
    10M SDIOW# 19

    26
    AC_RST# T1 AC_RST#
    INTEL 82801AB PIORDY N11
    N17
    PIORDY
    SIORDY
    19
    AC_SYNC T3 SIORDY 19
    R220 26 AC_SYNC

    X3
    10M
    26
    AC_BITCLK
    AC_SDOUT
    R3
    T2
    AC_BITCLK
    AC97
    PART 2 PDD0 R10 PDD0
    PDD[15:0]
    19
    Socketed 14,26 AC_SDOUT PDD1
    +

    Y3 N9
    2

    AC_SDIN0 U1 PDD1
    CR2032 1 2 26,33 AC_SDIN0 R9 PDD2
    AC_SDIN1 P3 PDD2
    26,33 AC_SDIN1/GPIO9 IDE PDD3 U9 PDD3
    ICH_SPKR U3
    32.768KHZ 14,31 SPKR R8 PDD4
    PDD4
    C346 C366
    3

    U8 PDD5
    LPC_SMI# PDD5
    12PF 12PF 16,33 D11 GPIO5 R7 PDD6
    LPC_PME# E11 PDD6
    16,33 GPIO6 U7 PDD7
    GPIO7 E9 PDD7
    18,33 GPIO7/PERR# P7 PDD8
    GPIO12 N4 PDD8
    33 GPIO12 N7 PDD9
    GPIO13 L2 PDD9
    33 GPIO13 T8 PDD10
    GPIO21 B14 PDD10
    18,33 GPIO21 GPIO P8 PDD11
    GPIO22 D13 PDD11
    33 GPIO22 T9 PDD12
    GPIO23_FPLED D15 PDD12 B
    B 31 GPIO23 P9 PDD13
    GPIO26_FPLED K4 PDD13
    31 GPIO26/SUSCLK T10 PDD14
    GPIO27 M5 PDD14
    28 GPIO27 P10 PDD15
    GPIO28 L5 PDD15
    28 GPIO28
    JP17 S TRA P (S PK R) SDD[15:0]
    P15 SDD0 19
    LAD0/FWH0 SDD0
    IN No Reboot on 2nd watc hdog tim eout 15,16 R6 LAD0/FWH0 SDD1
    SDD1 R16
    OUT Reboot on 2nd watc hdog tim eout LAD1/FWH1 U5
    15,16 LAD1/FWH1 T17 SDD2
    LAD2/FWH2 T5 SDD2
    15,16 LAD2/FWH2 U16 SDD3
    JP18 (A C_S DOUT) 15,16
    LAD3/FWH3 T4 LAD3/FWH3
    LPC SDD3
    U15 SDD4
    LFRAME#/FWH4 SDD4
    IN Forc e CP U freq strap to safe m ode (1111) 15,16 U4 LFRAME#/FWH4 R14 SDD5
    SDD5
    OUT Use CPU freq s trap in ICH regis ter 16
    LDRQ#0 T6 LDRQ#0 P13 SDD6
    LDRQ#1 N3 SDD6
    ICH_SPKR 33 LDRQ#1/GPIO8 T13 SDD7
    14,31 VCC3_3 SDD7
    U14 SDD8
    USBP1P R1 SDD8
    20 USBP1P T14 SDD9
    JP17 USBP1N SDD9
    P2
    20 USBP1N P14 SDD10
    USBP0P P1 SDD10
    20 USBP0P USB SDD11 T15 SDD11
    USBP0N N2
    10K 20 USBP0N U17 SDD12
    M4 SDD12
    JP13_PD

    OC#1 R15 SDD13


    A R187 SDD13
    OC#0 M3
    20 OC#0 R17 SDD14 A
    JP14_PU

    SDD14
    Minimize Stub Length P16 SDD15
    R209 SDD15
    to Jumpers
    10K JP18
    C293
    18PF REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    ICH0, PART 2
    AC_SDOUT DRAWN BY: PROJECT:
    14,26 R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 5-26-1999_17:09 14 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    FirmWare Hub (FWH) Socket


    NOTE: This is a Socketed Implementation

    D
    D

    VCC3_3
    VCC3_3

    C211 C355 C361 C259

    0.1UF 0.1UF 0.1UF 0.1UF


    VCC3_3
    Distribute close to each power pin.
    X4 40PIN_TSOP_SKT
    1 40
    NC1 GNDA
    2 39
    IC VCCA
    3 38 LFRAME#/FWH4
    C353 C36 NC3 FWH4 14
    C 4 37 INIT#
    NC4 INIT# 4,13,33 C
    0.1UF 0.1UF 5
    NC5 RFU36
    36

    6 35
    NC6 RFU35
    7 34
    FGPI4 RFU34
    8 33
    NC8 RFU33
    PCLK_6 9 32
    6 CLK RFU32
    10 31
    VCC10 VCC31
    R218 0K
    R_VPP 11 30
    VPP GND30
    PCIRST# 12 29
    13,17,18,24,27 RST# GND29
    13 28 LAD3/FWH3
    NC13 FWH3 14,16
    14 27 LAD2/FWH2
    NC14 FWH2 14,16
    VCC3_3 VCC3_3 15 26 LAD1/FWH1
    FGPI3 FWH1 14,16
    16 25 LAD0/FWH0
    FGPI2 FWH0 14,16
    S66DETECT 17 24 FWH_ID0
    19 FGPI1 ID0
    P66DETECT 18 23 FWH_ID1
    19 FGPI0 ID1
    19 22 FWH_ID2
    JP21 CONFIG JP21 20
    WP#

    TBL#
    ID2

    ID3
    21 FWH_ID3

    IN Unlocked
    FGPI4_PD

    FGPI3_PD

    FGPI2_PD
    R222 B
    IC_PD

    B OUT Locked Default 4.7K


    WPROT
    4

    1
    TBLK_LCK

    8.2K RP63 0K RP64

    R223 RP64 for Test/Debug


    5

    8
    4.7K

    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    FIRMWARE HUB (FWH)
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 2-22-1999_10:37 15 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1
    VCC3_3 VCC5 VCC3_3

    Super I/O
    R183
    4.7K
    U15

    44

    18

    53

    65

    93
    VREF

    VCC1

    VCC2

    VCC3
    VTR
    VCC3_3 Decoupling VCC5 LFRAME#/FWH4 24
    14 LFRAME# D
    D LAD3/FWH3 23 66 PAR_INIT#
    14,15 LAD3 INIT# 21
    LAD2/FWH2 22 67 SLCTIN#
    Place near 14,15 LAD2 SLCTIN# 21
    LAD1/FWH1 21 75 PDR7 PDR[7:0]
    VREF pin 14,15 LAD1 PD7 21
    LAD0/FWH0 20 74 PDR6
    1

    C323 14,15 LAD0 PD6


    C99 C287 C246 C297 C229 LDRQ#0 LPC I/F PDR5
    +

    25 73
    14 LDRQ# PD5
    0.1UF PCIRST# 26 72 PDR4
    2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 13,17,18,24,27 LRESET# PD4
    2

    SUSSTAT_PU 27
    LPCPD#
    PARALLEL PORT I/F PD3
    71 PDR3
    LPC_PME# 17 70 PDR2
    14,33 PME# PD2
    Place 1 0.1UF cap near each power pin SERIRQ 30 69 PDR1
    13,18,33 SERIRQ PD1
    PCLK_1 29 68 PDR0
    6 PCI_CLK
    SIO PD0

    SLCT#
    77 SLCT#
    21
    KDAT 56 78 PE
    23 KDAT LPC47B27X PE 21
    KCLK 57 79 BUSY
    23 KCLK BUSY 21
    MDAT 58 80 ACK#
    23 MDAT ACK# 21
    MCLK 59 81 ERROR#
    23 MCLK KYBD/MSE I/F ERROR#
    21
    RCIN# 63 82 ALF#
    13,33 KBDRST ALF#
    21
    A20GATE 64 83 STROBE#
    13,33 A20GATE STROBE#
    21

    C
    IRRX 61 54 PWM2 C
    31 IRRX2/GP34 FAN2/GP32
    31
    IRTX 62 INFRARED I/F 55 PWM1
    31 IRTX2/GP35 FAN1/GP33
    31

    RXD#0 84 28 SIO_GP43
    C356 C371 22 RXD1 FDC_PP/DDRC/GP43
    TXD0 85
    22 TXD1
    470PF 470PF DSR#0 86
    DSR1#
    22
    RTS#0 87
    RTS1#
    22 Test/Debug Header
    CTS#0 88 SERIAL PORT 1
    22 CTS1# Unused GPIOs
    DTR#0 89
    22 DTR1# J23
    RI#0 90 1 2
    22 RI1#
    DCD#0 91
    DCD1#
    3 4
    22
    5 6

    RXD#1 95
    22 RXD2_IRRX
    TXD1 96
    22 TXD2_IRTX
    DSR#1 97
    22 DSR2#
    RTS#1 98
    22 RTS2# SERIAL PORT 2
    CTS#1 99 48 SIO_GP60
    22 CTS2# GP60/LED1
    DTR#1 100 49 SIO_GP61
    22 DTR2# GP61/LED2 B
    B RI#1 92 50 LPC_SMI#
    22 RI2# GP27/IO_SMI# 14,33
    DCD#1 94 51 TACH2
    22 DCD2# GP30/FAN_TACH2 31
    52 TACH1
    GP31/FAN_TACH1 31
    DRVDEN#1 2 46 MIDI_IN
    23 DRVDEN1 GP25/MIDI_IN 23
    DRVDEN#0 1 47 MIDI_OUT
    23 DRVDEN0 GP26/MIDI_OUT 23
    MTR#0 3
    MTR0#
    23
    DS#0 5 32 J1BUTTON1
    23 DS0# GP10/J1B1 23
    DIR# 8 33 J1BUTTON2
    23 DIR# GP11/J1B2 23
    STEP# 9 34 J2BUTTON1
    23 STEP# GP12/J2B1 23
    WDATA# 10 35 J2BUTTON2
    23 WDATA# GP13/J2B2 23
    WGATE# 11 FDC I/F 36 JOY1X
    23 WGATE# GP14/J1X 23
    HDSEL# 12 37 JOY1Y
    23 HDSEL# GP15/J1Y 23
    INDEX# 13 38 JOY2X
    23 INDEX# GP16/J2X 23
    TRK#0 14 39 JOY2Y
    23 TRK0# GP17/J2Y 23
    WRTPRT# 15 41 KEYLOCK#
    23 WRTPRT# GP20/P17 31
    RDATA# 16 42 SIO_GP21
    23 RDATA# GP21/P16
    DSKCHG# 4 43 SIO_GP22
    23 DSKCHG# GP22/P12

    A
    6 45 SYSOPT A
    CLKI32 CLOCKS GP24/SYSOPT
    Pulldown on SYSOPT for IO address of 0x02E
    SIO_CLK14 19
    6 CLOCKI
    GND1

    GND2

    GND3

    GND4

    AVSS

    R180
    4.7K
    7

    31

    60

    76

    40

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    SUPER I/O
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 16 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1
    VCC3SBY

    PCI Connector 0 VCC3SBY


    PCI Connector 1 VCC12M
    VCC5
    VCC5
    VCC3_3

    (DEV Ah) VCC12M


    VCC5
    VCC3_3 (DEV Bh) VCC3_3 J16
    VCC12

    VCC5 PCI3_CON
    VCC12
    VCC3_3 J17 B1 A1 PTRST#
    17,18
    PTCK B2 A2
    PCI3_CON 17,18
    B3 A3 PTMS
    B1 A1 PTRST# 17,18,33
    17,18 B4 A4 PTDI D
    D PTCK B2 A2 17,18,33
    17,18 B5 A5
    B3 A3 PTMS
    17,18,33 B6 A6 PIRQ#B
    B4 A4 PTDI 13,17,18,33
    17,18,33 PIRQ#C B7 A7 PIRQ#D
    B5 A5 13,17,18,33 13,17,18,33
    PIRQ#A B8 A8
    B6 A6 PIRQ#A 13,17,18,27,33
    13,17,18,27,33 PRSNT#21 B9 A9
    PIRQ#B B7 A7 PIRQ#C 18
    13,17,18,33 13,17,18,33 B10 A10
    PIRQ#D B8 A8
    13,17,18,33 PRSNT#22 B11 A11
    PRSNT#11 B9 A9 18
    18 B12 A12
    B10 A10
    B13 A13
    PRSNT#12 B11 A11
    18 B14 A14
    B12 A12
    B15 A15 PCIRST#
    B13 A13 7,13,15,16,17,18,19,24,27
    PCLK_3 B16 A16
    B14 A14 6
    B17 A17 PGNT#1
    B15 A15 PCIRST# 13,33
    7,13,15,16,17,18,19,24,27 PREQ#1 B18 A18
    PCLK_2 B16 A16 13,33
    6 B19 A19 PCI_PME#
    B17 A17 PGNT#0 AD[31:0] 13,17,18,27
    13,33 AD31 B20 A20 AD30 AD[31:0]
    PREQ#0 B18 A18 13,17,18,27 13,17,18,27
    13,33 AD29 B21 A21
    B19 A19 PCI_PME#
    AD[31:0] 13,17,18,27 B22 A22 AD28
    AD31 B20 A20 AD30 AD[31:0]
    C 13,17,18,27 13,17,18,27 AD27 B23 A23 AD26
    AD29 B21 A21 C
    AD25 B24 A24
    B22 A22 AD28
    B25 A25 AD24
    AD27 B23 A23 AD26 C_BE#[3:0] R191
    C_BE#3 B26 A26 R_AD17 AD17
    AD25 B24 A24 13,17,18,27 13,17,18,27
    AD23 B27 A27 100
    B25 A25 AD24
    C_BE#[3:0] R168 B28 A28 AD22
    C_BE#3 B26 A26 R_AD16 AD16
    13,17,18,27 13,17,18,27 AD21 B29 A29 AD20
    AD23 B27 A27 100
    AD19 B30 A30
    B28 A28 AD22
    B31 A31 AD18
    AD21 B29 A29 AD20
    AD17 B32 A32 AD16
    AD19 B30 A30
    C_BE#2 B33 A33
    B31 A31 AD18
    B34 A34 FRAME#
    AD17 B32 A32 AD16 13,17,18,27,33
    IRDY# B35 A35
    C_BE#2 B33 A33 13,17,18,27,33
    B36 A36 TRDY#
    B34 A34 FRAME# 13,17,18,27,33
    13,17,18,27,33 DEVSEL# B37 A37
    IRDY# B35 A35 13,17,18,27,33
    13,17,18,27,33 B38 A38 STOP#
    B36 A36 TRDY# 13,17,18,27,33
    13,17,18,27,33 PLOCK# B39 A39
    DEVSEL# B37 A37 13,17,18,33
    13,17,18,27,33 PERR# B40 A40 SDONEP2
    B38 A38 STOP# 17,18,27 33
    13,17,18,27,33 B41 A41 SBOP2
    PLOCK# B39 A39 33
    13,17,18,33 SERR# B42 A42 B
    B PERR# B40 A40 SDONEP1 13,17,18,27,33
    17,18,27 33 B43 A43 PAR
    B41 A41 SBOP1 13,17,18,27
    33 C_BE#1 B44 A44 AD15
    SERR# B42 A42
    13,17,18,27,33 AD14 B45 A45
    B43 A43 PAR
    13,17,18,27 B46 A46 AD13
    C_BE#1 B44 A44 AD15
    AD12 B47 A47 AD11
    AD14 B45 A45
    AD10 B48 A48
    B46 A46 AD13
    B49 A49 AD9
    AD12 B47 A47 AD11

    key
    AD10 B48 A48
    B49 A49 AD9
    AD8 B52 A52 C_BE#0
    13,17,18,27
    key

    AD7 B53 A53


    B54 A54 AD6
    AD8 B52 A52 C_BE#0
    13,17,18,27 AD5 B55 A55 AD4
    AD7 B53 A53
    AD3 B56 A56
    B54 A54 AD6
    B57 A57 AD2
    AD5 B55 A55 AD4
    AD1 B58 A58 AD0
    AD3 B56 A56
    B59 A59
    B57 A57 AD2
    A PU2_ACK64# B60 A60 PU2_REQ64#
    AD1 B58 A58 AD0 33 33 A
    B61 A61
    B59 A59
    B62 A62
    PU1_ACK64# B60 A60 PU1_REQ64#
    33 33
    B61 A61
    B62 A62
    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    PCI CONNECTORS 1 AND 2
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 17 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    PCI Connector 2 (DEV 6h) Layout Note: Should be in Slot 0 Position (Outside Edge of Board Furthest from CPU)
    VCC3_3
    VCC12M
    VCC5
    VCC5
    VCC12
    VCC3_3 J22
    PCI3_CON R189
    PTRST#
    B1 A1 PTRST# 17,18
    17,18 5.6K
    PTCK B2 A2
    17,18 R190 D
    D B3 A3 PTMS PTCK
    17,33 17,18
    B4 A4 PTDI 5.6K
    17,33
    B5 A5
    B6 A6 PIRQ#C
    13,17,33
    PIRQ#D B7 A7 PIRQ#A
    13,17,33 13,17,27,33
    PIRQ#B B8 A8
    13,17,33
    PRSNT#31 B9 A9 PRSNT#32
    18 18
    GPIO21 R194 R_GPO21 B10 A10 PRSNT#31
    14,33 VCC3SBY 18
    PRSNT#32 0K For Debug Only B11 A11 R_GNT#A R185
    PCPCI_GNT#A PRSNT#22
    18 13 17
    0K
    B12 A12 For Debug Only PRSNT#21
    17
    B13 A13 PRSNT#12
    R195 R193 17
    SERIRQ R_SERIRQ B14 A14 VAUX3 PRSNT#11
    13,16,33 17
    0K For Debug Only B15 A15 PCIRST# 0K
    7,13,15,16,17,19,24,27
    PCLK_4 B16 A16
    6 R192
    B17 A17 PGNT#2 PCPCI_REQ#A
    13,33 13,33 C336 C337 C267 C284 C335 C342
    PREQ#2 B18 A18 0K For Debug Only
    13,33
    B19 A19 PCI_PME# Do Not Stuff R192 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
    AD[31:0] 13,17,27
    AD31 B20 A20 AD30 AD[31:0]
    13,17,18,27 13,17,18,27
    AD29 B21 A21
    C
    B22 A22 AD28 C
    AD27 B23 A23 AD26
    AD25 B24 A24
    B25 A25 AD24
    C_BE#[3:0] R167
    C_BE#3 B26 A26 R_AD22 AD22
    13,17,27 13,17,18,27
    AD23 B27 A27 100
    B28 A28 AD22
    AD21 B29 A29 AD20
    AD19 B30 A30
    B31 A31 AD18
    AD17 B32 A32 AD16
    C_BE#2 B33 A33
    B34 A34 FRAME#
    13,17,27,33
    IRDY# B35 A35
    13,17,27,33
    B36 A36 TRDY#
    13,17,27,33
    DEVSEL# B37 A37
    13,17,27,33
    B38 A38 STOP#
    13,17,27,33 JP19
    PLOCK# B39 A39
    13,17,33 1 PERR#_PU
    PERR# B40 A40 SDONEP3 33
    17,18,27 33 PERR# 2 B
    B B41 A41 SBOP3 17,18,27
    33 3 GPIO7
    SERR# B42 A42 14,33
    13,17,27,33
    B43 A43 PAR
    13,17,27
    C_BE#1 B44 A44 AD15
    AD14 B45 A45 JP19 - ICH/ICH0 Compatibility
    B46 A46 AD13
    AD12 B47 A47 AD11 1-2 ICH0 Default
    AD10 B48
    B49
    A48
    A49 AD9
    2-3 ICH
    key

    AD8 B52 A52 C_BE#0


    13,17,27
    AD7 B53 A53
    B54 A54 AD6
    AD5 B55 A55 AD4
    AD3 B56 A56
    B57 A57 AD2
    AD1 B58 A58 AD0
    A
    B59 A59 A
    PU3_ACK64# B60 A60 PU3_REQ64#
    33 33
    B61 A61
    B62 A62

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    PCI CONNECTOR 3
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 18 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    ULTRAATA/33 IDE CONNECTORS

    VCC5
    VCC5 PRIMARY SECONDARY
    IDE CONN. IDE CONN. D
    D
    PDD[15:0] SDD[15:0]
    14 14
    R133 R100
    1K J15 1K J12
    R140 R139
    PCIRST_BUF# R_RSTP# 1 2 PCIRST_BUF# R_RSTS# 1 2
    19 19
    33 PDD7 3 4 PDD8 33 SDD7 3 4 SDD8
    PDD6 5 6 PDD9 SDD6 5 6 SDD9
    PDD5 7 8 PDD10 SDD5 7 8 SDD10
    PDD4 9 10 PDD11 SDD4 9 10 SDD11
    PDD3 11 12 PDD12 SDD3 11 12 SDD12
    PDD2 13 14 PDD13 SDD2 13 14 SDD13
    PDD1 15 16 PDD14 SDD1 15 16 SDD14
    PDD0 17 18 PDD15 SDD0 17 18 SDD15
    19 20 19 20

    PDREQ 21 22 SDREQ 21 22
    14 14
    PDIOW# 23 24
    For Host-Side 80-Conductor Cable Detection: SDIOW# 23 24
    14 14
    PDIOR# 25 26 Populate R96 and R221, DePopulate C187 SDIOR# 25 26 For Host-Side 80-Conductor Cable Detection:
    14 14
    PIORDY 27 28 PRI_PD1 For Drive-Side 80-Conductor Cable Detection: SIORDY 27 28 PRI_SD1 Populate R94 and R95, DePopulate C186
    C 14 Populate C187, DePopulate R96 and R221 14 For Drive-Side 80-Conductor Cable Detection:
    PDDACK# 29 30 SDDACK# 29 30
    Populate C186, DePopulate R94 and R95 C
    14 14
    IRQ14 31 32 IRQ15 31 32
    13,33 R96 13,33 R95
    PDA1 33 34 R_P66DET P66DETECT SDA1 33 34 R_S66DET S66DETECT
    15 15
    PDA0 35 36 0K SDA0 35 36 0K
    PDCS#1 37 38 PDCS#3 SDCS#1 37 38 SDCS#3
    14 14 14 14
    IDEACTP# 39 40 IDEACTS# 39 40
    31 31
    PDA[2:0]
    PDA2 SDA[2:0] SDA2
    14 14

    R135 R138 R101 C187 R134 R137 R132 C186


    5.6K 10K 470 R221 5.6K 10K 470 R94
    0.047UF 0.047UF
    15K 15K

    VCC3_3

    B
    B
    VCC3_3

    R141
    U11
    VCC
    14 8.2K
    PCIRST# 5 6 PCIRST_BUF#
    13,17,18,24,27 19
    7

    GND
    SN74LVC07A

    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    ULTRAATA/33 CONNECTORS
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 2-22-1999_10:37 19 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    USB Connectors VCC5

    VCC3_3 Do Not Stuff

    AC97_USB- R149
    26

    2
    0K
    POLYSWITCH RUSB250 R148
    AC97_USB+
    F3 26
    2.5A 0K
    R147 D
    D

    1
    330K L23
    USBV5 1 2

    1
    AC97_OC# C202 C12

    +
    26
    68UF 0.1UF

    2
    R146 R72
    0K 470K
    Do Not Stuff USBV0

    USBP0N R204 R13 USBD0N


    R_USBP0N
    OC#0 14
    14 15 0K
    USBP0P R205 R15 USBD0P
    R_USBP0P
    14
    C124 15 0K
    R201
    560K USBG0
    .001UF
    R11 R14
    C348 C359
    15K 15K
    47PF 47PF

    2
    C C15
    L11 C
    J3
    470PF USB-CON2
    1
    VCC1

    1
    2
    Place R204, R205, C348, and C359 within 1" of ICH0 DATA1-
    3
    DATA1+
    4
    GND1
    5
    VCC2
    L9 6
    DATA2-
    1 2 7
    DATA2+
    8
    GND2
    1

    C201 C9 2 - USB Stacked


    +

    68UF 0.1UF
    2

    USBV1

    R214
    USBP1N USBD1N
    14
    15
    USBP1P R211 USBD1P
    14 B
    B 15
    USBG1

    C358 C357 R12 R63 C13 C8

    47PF 47PF 15K 15K 47PF C16 47PF C98


    Place CAPs as close as
    possible to connector.

    2
    47PF 47PF
    C14 L10

    470PF
    Place R214, R211, C357, and C358 within 1" of ICH0

    1
    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    USB CONNECTORS
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 20 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    Parallel Port Header

    D
    D

    VCC5

    CR1
    A C PARV5

    1N4148

    5
    RP28 RP17 RP13 RP14
    R224 2.2K 2.2K 2.2K 2.2K
    2.2K
    C

    4
    C

    ERROR#
    16

    RP16
    SLCTIN# 1 8 R_SLCTIN#
    16
    PAR_INIT# 2 7 R_PARINIT#
    16
    ALF# 3 6 R_ALF#
    16
    STROBE# 4 5 R_STROBE#
    16
    33
    RP15 J5
    PDR[7:0] PDR0 1 8 R_PDR0
    16 1 2
    PDR1 2 7 R_PDR1
    3 4
    PDR2 3 6 R_PDR2
    5 6
    PDR3 4 5
    7 8
    33 R_PDR3 9 10
    RP27
    PDR4 1 8 R_PDR4 11 12

    PDR5 2 7 R_PDR5 13 14

    PDR6 3 6 R_PDR6 15 16

    PDR7 4 5 R_PDR7 17 18 B
    B
    19 20
    33
    21 22

    ACK# 23 24
    16
    25 26

    BUSY
    16
    C197 C194 C192 C189 C96 C92 C88 C93 C91
    PE
    16
    180PF

    180PF

    180PF

    180PF

    180PF

    180PF

    180PF

    180PF

    180PF
    SLCT# J5 Pinned Out for IDC (Flow Through) Ribbon Cable Connector
    16

    C196 C193 C190 C97 C94 C90 C89 C95


    180PF

    180PF

    180PF

    180PF

    180PF

    180PF

    180PF

    180PF
    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    PARALLEL PORT
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 2-22-1999_11:02 21 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    Serial Port/COM Headers


    VCC12-
    VCC5 VCC12
    J19 and J21 pinned out for IDC (Flow Through) Ribbon Cable Connector

    U17
    D
    D
    20 1
    VCC VCC12
    DCD#0 19 2 DCD#0_C
    16 RY0 RA0

    GD75232
    RXD#0 18 3 RXD#0_C
    16 RY1 RA1 J21
    DSR#0 17 4 DSR#0_C 1 2
    16 RY2 RA2
    DTR#0 16 5 DTR#0_C 3 4
    16 DA0 DY0
    TXD0 15 6 TXD#0_C 5 6
    16 DA1 DY1
    CTS#0 14 7 CTS#0_C 7 8
    16 RY3 RA3
    RTS#0 13 8 RTS#0_C 9 10
    16 DA2 DY2
    RI#0 12 9 RI#0_C
    16 RY4 RA4
    11 10
    GND VCC-12

    C325 C327 C329 C368


    COM1 and COM2 are 2x5 pin Headers for a cabled port.
    100PF 100PF 100PF 100PF
    VCC3SBY Place Close to Header
    C326 C328 C330 C369

    100PF 100PF 100PF 100PF

    C
    C
    R230
    10K CR15
    BAT54C
    RI#_CR_C 3 1

    2
    ICH_RI#
    14

    D
    Q10 R227
    47K
    3
    2N7002LT1

    1 G ICHRI#_C
    2
    VCC12- 2nd COM Header Option
    If not populated at all, remove CR14
    S and short RI#0_C to RI#CR
    VCC5 VCC12

    C374
    R229
    47K U16
    1.0UF

    20 1
    VCC VCC12
    DCD#1 19 2 DCD#1_C
    16 RY0 RA0
    GD75232

    NOTE: If Wake from S3 on RXD#1 18 3 RXD#1_C


    16 RY1 RA1 J19 B
    B Serial Modem is not supported DSR#1 17 4 DSR#1_C 1 2
    do not stuff CR15 and Q10. 16 RY2 RA2
    DTR#1 16 5 DTR#1_C 3 4
    16 DA0 DY0
    TXD1 15 6 TXD#1_C 5 6
    16 DA1 DY1
    CTS#1 14 7 CTS#1_C 7 8
    16 RY3 RA3
    RTS#1 13 8 RTS#1_C 9 10
    16 DA2 DY2
    RI#1 12 9 RI#1_C
    16 RY4 RA4
    11 10
    GND VCC-12

    C316 C314 C315 C311

    100PF 100PF 100PF 100PF


    Place Close to Header
    C312 C313 C309 C310

    100PF 100PF 100PF 100PF

    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    SERIAL AND GAME PORTS
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 2-22-1999_11:02 22 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    KEYBOARD/MOUSE PORTS FLOPPY DISK HEADER


    VCC5

    VCC5
    L3
    F2
    PS2V5
    1 2 1 2
    PS2V5_F
    1.25A
    D
    D
    RP31
    1 8

    5
    2 7
    RP1 3 6
    4.7K
    4 5

    STACKED PS2 CONNECTOR 1K


    1

    L5 J1
    KDAT 1 2 L_KDAT 1
    16 R143
    2

    PS/2 Kybd
    3 1K
    L4 4
    KCLK 1 2 L_KCLK 5 J14
    2
    16 DRVDEN#0 1
    6 16
    4 3
    L7 6
    DRVDEN#1 5
    MDAT 1 2 L_MDAT 7 16
    16 8
    INDEX# 7
    8 17 PS2GND 16
    10
    MTR#0 9

    PS/2 Mse
    9 16 16
    12 11
    L6 10 15 14
    C DS#0 13
    MCLK 1 2 L_MCLK 11 14 16
    16 16 15 C
    12 13 18
    DIR# 17
    16
    20
    STEP# 19
    C3 C4 C5 C2 C1 16
    22
    L1 WDATA# 21

    2
    16
    470PF 470PF 470PF 470PF 0.1UF WGATE# 24 23
    16
    TRK#0 26 25
    16
    28
    PS2_PD WRTPRT# 27
    16

    1
    30
    L2 RDATA# 29
    2
    16
    32
    HDSEL# 31
    16
    34
    DSKCHG# 33
    16
    1

    GAME PORT HEADER


    J7 Pinned Out for IDC (Flow Through) Ribbon Cable Connector
    RP29
    VCC5 R_JOY1X 1 8 JOY1X
    16
    JOY1Y B
    B R_JOY1Y 2 7
    16
    R_JOY2Y 3 6 JOY2Y
    16
    R_JOY2X 4 5 JOY2X
    16
    2.2K
    C199 C198 C191 C195
    VCC5
    0.01UF 0.01UF 0.01UF 0.01UF
    VCC5
    11

    13

    15
    1

    J7
    8

    5
    2

    10

    12

    14

    16

    RP30
    1K
    R89 R178
    1

    4.7K 4.7K
    J1BUTTON1
    16
    J1BUTTON2
    16
    J2BUTTON2
    16
    A J2BUTTON1
    R88 16
    MIDI_OUT R_MIDIOUT
    A
    16
    47 C179 C178 C79 C182
    R179
    MIDI_IN R_MIDIIN
    16
    47 47PF 47PF 47PF 47PF
    C177 C176
    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    470PF 470PF 1.3
    KEYBOARD/MOUSE/FLOPPYGAME PORTS
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 2-22-1999_11:02 23 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    Digital Video Out VCC3_3

    L26
    2 1
    FPP1V3

    1
    C281
    C275 C280

    +
    100PF

    100PF
    VCC3_3 VCC3_3

    10UF
    D

    2
    D

    L25
    FPDV3 24 2 1
    2 1 FPAV3
    1

    1
    L27
    C282

    C276 C277 C231 C271 C272 C230


    +

    +
    100PF

    100PF

    100PF

    100PF

    100PF
    10UF

    10UF
    2

    2
    VCC1_8

    1K VCC1_8
    R116

    24 FTVREF

    Place C226 near R126


    U28, pin 3
    C228

    R165
    1K U7 400 4.7K
    49

    18

    33

    12
    29

    23
    3

    1
    C226
    R122

    C 1% Do Not Stuff R126


    0.01UF

    VREF

    PVCC1

    PVCC0

    VCC2

    VCC1

    VCC0
    AVCC1

    AVCC0

    C
    100PF

    36
    D23
    37 21 TXC-
    D22 TXC- 25
    38 22 TXC+
    D21 TXC+ 25
    39
    D20
    40
    D19
    41 24 TX0-
    42
    D18
    FLAT PANEL TX0-
    25 TX0+
    25
    D17 TX0+ 25
    43
    D16/PFEN TRANSMITTER
    44

    45
    D15
    SII154 27 TX1-
    D14 TX1- 25
    46 28 TX1+
    FTD[11:0] D13 TX1+ 25
    47
    9 D12
    FTD11 50
    D11
    FTD10 51 30 TX2-
    D10 TX2- 25
    FTD9 52 31 TX2+
    D9 TX2+ 25
    FTD8 53
    D8
    FTD7 54
    D7 EXT_RS
    19

    FTD6 EXTRS_PU
    55
    D6
    FTD5 PCIRST# B
    B 58
    D5 DKEN/RST
    35
    13,17,18,24,27
    FTD4 59
    D4 TEST
    34 TEST_PD

    FTD3 60 15 3VFTSCL
    D3 BSEL/SCL 9,24,25
    FTD2 61 14 3VFTSDA
    D2 DSEL/SDA 9,24,25
    FTD1 62
    D1 ISEL
    13

    FTD0 63 11 SL_STALL
    D0 MSEN 9,24
    10
    PD
    FTCLK0 56 9 3VHTPLG
    9,24 IDCLK- EDGE/CHG 25
    FTCLK1 57
    9,24 IDCLK+
    8 A1_PD
    CTL1/A1/DK1
    FTBLNK# 2
    9,24 DE
    7 A2_PD
    FTHSYNC CTL2/A2/DK2
    4
    9,24 HS
    6 A3_PD
    CTL3/A3/DK3
    FTVSYNC 5
    9,24 VS
    AGND2

    AGND1

    AGND0

    PGND

    GND2

    GND1

    GND0

    R113 R118 R121


    32

    26

    20

    17

    64

    48

    16

    1K 1K 1K

    A Do Not Stuff
    R124 A
    4.7K
    R124 is for Test Only
    FPDV3
    TEST pin may be 24
    tied direct to GND

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    DIGITAL VIDEO OUT
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 5-26-1999_17:13 24 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    Video Connectors

    20 Pin Flat Panel Connector VGA Connector VCC5


    D
    D

    VCC5 BLM11B750S is rated at 75Ohms at 100MHz

    2
    L21
    VID_RED 1 2 F1
    9
    VCC5 VCC1_8 2.5A
    J8
    BLM11B750S R65 R74
    C109 C111

    CRT5V_F
    TX1+ 1 11 TX2+ R69

    1
    24 24
    TX1- 2 12 TX2- 75 3.3PF 3.3PF 1K 1K
    24 24
    3 13
    Protection Circuit 2 1% L12

    2
    for 20V Tolerance
    C J6
    -

    1N5821
    4 14

    CR7
    1 3
    BAT54S
    TXC+ 5 15 TX0+
    24 24 A
    +
    TXC- TX0- CR10
    6 16 6 6
    24 24

    1
    7 17 L_RED 1 1 11
    R75
    8 18 CON_HTPLG 5VHTPLG Place R66,R67,&R69 Close to VGA Connector MONOPU 11
    25
    9 19 2.2K 7
    L20
    De-Bounce Circuit
    VID_GREEN L_GREEN
    1
    10 20 1 2 2
    C203 9
    CON_FTSDA
    CON_FTSCL

    C200
    +
    VCC1_8 BLM11B750S
    12
    0.01UF

    C 10UF C105 C106 8


    R67 C
    2

    L_BLUE 3
    75 3.3PF 3.3PF
    2 1% L_HSYNC 13
    Populate if DFP Device
    is also populated.
    FUSE_5 9
    1 3
    R105 BAT54S MON2PU 4
    5VFTSDA
    24,25 CR9 L_VSYNC 14
    0K
    R103
    5VFTSCL 5VDDCDA 10 10
    24,25 25
    0K 5 15
    5
    R71
    5VHSYNC 15
    25
    VCC5 0K
    C122 C119
    VCC5
    3.3PF 3.3PF
    2

    CR4 1 3
    BAT54S
    QS4_3V C A Do Not Stuff C119 and C122
    CR5
    1N4148 5VDDCCL
    8

    5V to 3.3V Translation/Isolation 25
    R115

    4.7K
    C227

    0.1UF

    R64
    5VVSYNC
    RP34

    25
    2.2K 0K
    VCC5 B
    B C102 C100
    1

    U6
    3.3PF 3.3PF
    QST3384
    24 2
    VCC C112 C208
    3VDDCDA 3 2 5VDDCDA
    9 1A1 1B1 25 1 3
    3VDDCCL 4 5 5VDDCCL BAT54S 10PF 10PF
    9 1A2 1B2 25 Do Not Stuff C100 and C102 C116 C101
    CRT_HSYNC 7 6 5VHSYNC CR6
    9 1A3 1B3 25
    CRT_VSYNC 8 9 5VVSYNC L19 10PF 10PF
    9 1A4 1B4 25 VID_BLUE 1 2
    3VHTPLG 11 10 5VHTPLG 9
    24 1A5 1B5 25
    BLM11B750S
    3VFTSDA 14 15 5VFTSDA VCC1_8
    9,24 2A1 2B1 24,25 C104 C103
    3VFTSCL 17 16 5VFTSCL R66
    9,24 2A2 2B2 24,25
    CK_SMBDATA 18 19 QSSDA R119 SMBDATA 75 3.3PF 3.3PF
    6 2A3 2B3 11,12,14,28,33 1%
    20 QSSCLR120
    CK_SMBCLK 0K SMBCLK
    21 2
    6 2A4 2B4 11,12,14,28,33
    0K
    22 23
    2A5 2B5
    1 3
    1 BAT54S
    BEA# GND
    12
    13 CR8
    BEB#

    A
    A

    2.2K

    R59
    2.2K
    REV:
    R58 TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    Do Not Populate VIDEO CONNECTORS
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 25 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    AUDIO/MODEM RISER

    D
    D

    VCC12
    VCC5 VCC12-
    VCC3_3 VCC5 VCC3SBY

    J18

    B1 A1
    AUDIO_MUTE# AUDIO_PWRDWN
    B2 A2
    GND[0] (ISOLATED) MONO_PHONE
    AC97SPKR B3
    MONO_OUT/PC_BEEP RESV[5]
    A3
    31
    B4 A4
    RESV[1] RESV[6]
    B5 A5
    RESV[2] RESV[7]
    B6 A6
    C PRIMARY_DN# GND[7]
    B7
    -12V +5VDUAL/5VSBY
    A7 C
    B8 A8 AC97_OC#
    GND[1] USB_OC 20
    B9 A9
    +12V GND[8]
    B10 A10 AC97_USB+
    GND[2] USB+ 20
    B11 A11 AC97_USB-
    +5VD USB- 20
    AC’97_RISER
    KEY KEY
    AMR_CONNECTOR
    KEY KEY
    B12 A12
    GND[3] GND[9]
    B13 A13
    RESV[3] S/P_DIF_IN
    B14 A14
    RESV[4] GND[10]
    B15 A15
    +3.3VD +3VDUAL/3VSBY
    B16 A16
    GND[4] GND[11]
    AC_SDOUT B17 A17 AC_SYNC
    14 AC97_SDATA_OUT AC97_SYNC 14
    AC_RST# B18 A18
    14 AC97_RESET# GND[12]
    B19 A19 AC_SDIN1
    AC97_SDATA_IN3 AC97_SDATA_IN1 14,33
    B20 A20
    GND[5] GND[13]
    B21 A21 AC_SDIN0
    AC97_SDATA_IN2 AC97_SDATA_IN0 14,33
    B22 A22
    GND[6] GND[14]
    B23 A23 AC_BITCLK
    AC97_MSTRCLK AC97_BITCLK 14 B
    B

    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    AUDIO/MODEM RISER
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 26 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1
    VCC5 VCC3SBY VCC3SBY VCC3SBY VCC3SBY
    LAN VCC3SBY

    R159 U13

    G13
    K13

    P12

    A11

    E12

    K10
    K11

    L10
    J10
    J11
    G5
    G6
    N8

    N6

    H5
    H6
    H7
    H8
    A3
    A7
    E1
    K3

    P2

    K4
    K5
    K6
    K7
    K8
    K9

    L4
    L5
    L9
    J5
    J6
    J7
    J8
    J9
    4.7K
    AD[31:0] AD0 5%

    VCC[0]
    VCC[1]
    VCC[2]
    VCC[3]
    VCC[4]
    VCC[5]
    VCC[6]
    VCC[7]
    VCC[8]
    VCC[9]

    VCC[20]
    VCCPP[0]
    VCCPP[1]
    VCCPP[2]
    VCCPP[3]
    VCCPP[4]
    VCCPP[5]

    VCC[10]
    VCC[11]
    VCC[12]
    VCC[13]
    VCC[14]
    VCC[15]
    VCC[16]
    VCC[17]
    VCC[18]
    VCC[19]

    VCC[21]
    VCC[22]
    VCC[23]
    VCC[24]
    VCC[25]
    VCCPL[0]
    VCCPL[1]
    VCCPL[2]
    VCCPL[3]

    VCCPT
    13,17,18 N7 AD0
    AD1 M7 AD1
    AD2 P6 A12 LILED
    AD2 LILED 28
    AD3 P5 C11 ACTLED
    LAN Decoupling AD3 ACTLED 28
    AD4 N5 B11 SPEEDLED D
    D Distribute aroung Power AD4 SPEEDLED 28
    Pins Close to 82559. AD5 M5 C13 TDP
    AD5 TDP 28
    VCC3SBY AD6 P4 C14 TDN
    AD6 TDN 28
    AD7 N4 E13 RDP
    AD7 RDP 28
    AD8 P3 E14 RDN
    AD8 RDN 28
    AD9 N3 B10
    AD9 SMBALRT#
    C261 C184 C165 AD10 N2 C5
    AD10 CSTSCHG
    AD11 M1 A6 PCI_PME#
    AD11 PME# 13,17,18
    0.1UF 0.1UF 0.1UF AD12 M2 J13
    AD12 FLA0/PCIMODE#
    R164
    AD13 M3 J12 LANAPWR
    AD13 FLA1/AUXPWR
    VCC3SBY AD14 L1 K14 3K
    AD14 FLA2
    AD15 L2 L14
    AD15 FLA3
    AD16 K1 L13
    AD16 FLA4
    AD17 E3 L12
    AD17 FLA5
    C334 C180 C257 AD18 D1 M14
    AD18 FLA6
    AD19 D2 M13
    AD19 FLA7
    0.1UF 0.1UF 0.1UF

    VCC3SBY
    AD20
    AD21
    D3
    C1
    AD20
    AD21
    82559 FLA8/IOCHRDY
    FLA9/MRST
    N14
    P13
    VCC3SBY

    AD22 B1 N13
    AD22 FLA10/MRING#
    C AD23 B2 AD23 FLA11/MINT M12 U18
    8
    C
    AD24 B4 M11 93C46
    AD24 FLA12/MCNTSM#
    1

    C68 C255 VCC


    Place C68/C255 AD25 A5 P10 EEDI 3
    AD25 FLA13/EEDI EEDI
    +

    Close to Ball A10 AD26 B5 N10 EEDO 4 7


    AD26 FLA14/EEDO EEDO NC2
    4.7UF 4.7UF AD27 B6 M10 EESK 2 6
    2

    AD27 FLA15/EESK EESK NC1


    AD28 C6 P9 1
    AD28 FLA16 EECS
    GND
    AD29 C7 F14
    AD29 FLD0
    AD30 5
    A8 AD30 FLD1 F13
    AD31 B8 F12
    AD31 FLD2
    FLD3 G12
    13,17,18 C_BE#[3:0] C_BE#0 M4 H14 Do Not Stuff
    C/BE0# FLD4
    R162
    C_BE#1 L3 H13 FLD5_PD
    C/BE1# FLD5
    R163
    C_BE#2 F3 H12 FLD6_PD 619
    C/BE2# FLD6
    C_BE#3 C4 J14 619
    C/BE3# FLD7
    P7 EECS
    EECS
    FRAME# F2 N9
    13,17,18,33 FRAME# FLCS#
    IRDY# F1 M8
    13,17,18,33 IRDY# FLOE#
    TRDY# G3 M9
    13,17,18,33 TRDY# FLWE#
    DEVSEL# H3 C8 LANCLKRUN R154
    13,17,18,33 DEVSEL# CLKRUN#
    STOP# H1 A13 LAN_TEST 62K R152 B
    B 13,17,18,33 STOP# TEST
    PAR J1 D13 4.7K
    13,17,18 PAR TEXEC
    PIRQ#A H2 D14
    13,17,18,33 INTA# TCK
    PERR# J2 D12
    17,18 PERR# TI
    SERR# A2 B12
    13,17,18,33 SERR# TO
    R153 R156
    AD20 R_LANIDS A4 B14 RBIAS10
    13,17,18,27 IDSEL RBIAS10
    R155
    PREQ#3 100 C3 B13 RBIAS100 549
    13,33 REQ# RBIAS100
    PGNT#3 J3 C12 619
    13,33 GNT# VREF
    PCIRST# C2 D10
    7,13,15,16,17,18,19,24 RST# NC11
    PCLK_5 G1 G4
    6 CLK NC10
    A14
    NC9
    LAN_ISOLATE# B9 J4
    28 ISOLATE# NC8
    LAN_RST# A9 L7
    28 ALTRST# NC7
    P1
    NC6
    L_SMBCLK A10 D9
    28 SMBCLK NC5
    L_SMBD C9 L8
    28 SMBD NC4
    P14
    NC3
    VIO G2 H4
    VIO NC2
    A NC1
    A1
    A
    LAN_XTAL1 N11 X1
    VSSPP[0]
    VSSPP[1]
    VSSPP[2]
    VSSPP[3]
    VSSPP[4]
    VSSPP[5]
    VSSPL[0]
    VSSPL[1]
    VSSPL[2]
    VSSPL[3]

    VSS[10]
    VSS[11]
    VSS[12]
    VSS[13]
    VSS[14]
    VSS[15]
    VSS[16]
    VSS[17]
    VSS[18]
    VSS[19]
    VSS[20]
    VSS[21]
    VSS[22]
    VSS[23]
    VSS[24]
    VSS[25]
    VSS[26]
    VSS[27]
    VSS[28]
    VSS[29]
    VSS[30]
    VSS[31]
    VSSPT

    VSS[0]
    VSS[1]
    VSS[2]
    VSS[3]
    VSS[4]
    VSS[5]
    VSS[6]
    VSS[7]
    VSS[8]
    VSS[9]

    Y2 LAN_XTAL2 P11 X2
    C331 C269 C265
    N12

    C10

    D11

    F4
    F5
    F6
    F7
    F8
    F9
    F10
    F11
    G7
    G8
    G9

    H10
    H11
    G14
    K12
    P8

    B3
    B7
    E2
    K2
    M6

    E4
    E5
    E6
    E7
    E8
    E9
    E10
    E11

    G10
    G11
    N1

    D4
    D5
    D6
    D7
    D8

    H9

    L6
    L11
    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    25MHZ 22PF 22PF 0.1UF LAN
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 OF 40
    8 7 6 5 4 3 11-23-1998_13:44 1 27
    2
    8 7 6 5 4 3 2 1

    VCC3SBY
    LAN
    VCC3SBY

    R111
    330
    D
    D
    R108 R144 R145
    330 330 330

    ACT_CR
    J9

    JP7_PU

    JP18_PU

    JP23_PU
    TDP 10 RJMAG R112
    27 TD+
    15 LI_CR ACTLED
    TDN 12 27,28
    27 TD-
    330 JP7 JP11 JP12
    RDP 9 16 LILED
    27 RD+ 27,28
    RDN 7
    27 RD-

    RJ-45
    13
    5
    RJ-4
    Place Termination near 82559 R157 R158 R160 R161 14
    50 50 50 50 6 SPEEDLED
    RJ-5 27,28
    3
    RJ-7
    LILED
    TD_PD RD_PD 4 27,28
    RJ-8
    ACTLED
    27,28

    SHLD1

    SHLD2

    RDC
    RXC

    TDC
    TXC
    SPEEDLED
    C266 C268 27,28

    RJ45_PD

    RJ78_PD
    Do Not Stuff 0.1UF 0.1UF

    11

    8
    17

    18
    1

    RDC
    TDC
    C
    C

    RXC_PD
    TXC_PD
    R107 R110 R106 R109 C213 C212
    75 75 75 75
    0.1UF 0.1UF
    Do Not Stuff
    RJMAG_CONN

    VCC3SBY
    C210
    Default Config:
    Do Not Stuff 470PF-1500V
    For EST Testing Note: Chassis Ground,
    use plane for this signal

    R215
    4.7K JP8

    Note: Chassis Ground, SMBCLK 1


    11,12,14,25,33
    use plane for this signal 2 JP8_SMBC
    R151
    L_SMBCLK
    27
    GPIO27 3 0K
    14
    B
    B

    VCC3SBY

    Select JP8/JP9
    ICH0 1-2 Default
    ICH 2-3

    R210 R186
    SUS_STAT#
    14 4.7K
    0K JP9
    LAN_ISOLATE#
    27
    R198 SMBDATA 1
    11,12,14,25,33
    PWROK R150 L_SMBD
    14,29,32 2 JP9_SMBD
    27
    0K GPIO28 3 0K
    14
    Do Not Stuff R198
    LAN DISABLE - JP10
    Normal 1-2 Default
    JP10
    Disable 2-3
    RSMRST# 1
    14,32
    A 2 LAN_RST#
    27
    3 A

    Note: This circuit is for debug purpose only.

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    LAN
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 28 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    Voltage Regulators VCC3_3 V3SB VCC3SBY

    1N5822

    C
    1

    1
    C174 C75 CR2

    +
    +
    VCC 3.3V Standby VOLTAGE SWITCH
    NDS356AP
    This generates 3.3V Standby Power which is D

    2
    47UF 47UF
    D
    on in S0,S1,S3,S4,&S5. It passes 3.3V from

    D
    S

    D
    S
    the ATX supply in S0/S1, and 3.3VSB (generated
    by VR2 below) in S3/S4/S5.

    G
    Q5

    G
    Do Not Populate

    C173 C375

    1
    NDS356AP

    +
    VCC12

    D
    S

    D
    S

    2
    1200UF 1200UF

    G
    R61 Q6
    VCC5SBY

    G
    4.7K
    SN74LVC07A has 5V input and output tolerance.

    VCC5SBY VCC3SBY Q9
    SI4410DY
    R87
    PLANE_CTL1 4 5
    10K 3 6
    C
    U4 U5 Q7 2 7 VTT 1.5V VOLTAGE REGULATOR
    74LS132 VCC VCC
    14
    SLP_S3# 1

    MMBT3904LT1
    14

    C 14,32 3 1 2
    R83 3 1 8
    PCTL_IN PLANE_CTL0 V_GQ6 B 1 C
    PWROK 2 VCC3_3 VTT1_5
    28,32 0K
    7

    2
    7
    GND GND
    SN74LVC07A VR5
    E
    Q8 LT1587-1_5
    SI4410DY
    2
    VOUT
    4 5
    3
    VIN
    3 6
    1
    ADJ
    2 7

    1
    1 8

    100UF-TANT

    100UF-TANT
    C43 C270 C225

    +
    1.0UF

    2
    B
    B
    VCC 3.3VSB Regulator VCC 1.8 VOLTAGE REGULATOR VCC 2.5 VOLTAGE REGULATOR

    VCC5SBY V3SB VCC1_8


    VCC3_3 VCC5 VCC2_5

    VR2
    LT1587ADJ
    VR3
    LT1587ADJ
    VR4
    LT1117-3_3 R55
    2 R56
    VOUT
    1% 2
    3 301 VOUT 1% 240
    3 2 VIN
    IN OUT 3
    VIN
    1 VR1_ADJ
    C159

    1
    ADJ
    1 VR5_ADJ
    C74
    1

    1
    GND ADJ

    +
    100UF-TANT

    C59
    1

    C57
    100UF-TANT
    1

    1
    100UF-TANT

    22UF-TANT
    C76
    22UF-TANT

    C71
    +

    R54
    +

    C65 R57

    2
    1.0UF 1%
    2

    130 1% 240
    2

    Place C76 at 0.1UF


    2

    the Regulator Place C159 at the Regulator

    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    VOLTAGE REGULATORS
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 29 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    Processor Voltage Regulator VCC3_3 VCC5

    VCC12

    VCC5
    R33 R18

    R22 220 5.6K


    D
    D

    1.0UH-6.8A
    5.1 VRM_PWRGD
    32

    L8
    C21
    5VIN

    1.0UF
    C27 C30 C26 C29 C7

    1
    R17 C22

    +
    2

    2
    10K 0.1UF 10UF 1200UF 1200UF 1200UF 1200UF

    R20
    C20

    8
    PV12

    D4

    D3

    D2

    D1

    D4

    D3

    D2

    D1
    2.7K
    0.01UF
    VR1 Place CAPs

    SI4410DY

    SI4410DY
    5

    2
    Close to FETs
    VID[3:0] C24 C25

    Q2

    Q1
    3 RP4 OUTEN 19
    OUTEN IMAX
    7 IMAX VCCVID

    G1

    G1
    S3

    S2

    S1

    S3

    S2

    S1
    VCC

    PVCC
    VID0 R_VID0 18
    VID0 PWRGD
    13
    C 4 5

    1
    VID1 R_VID1 17 12 FAULT#_PU C
    3 6
    VID1 FAULT# 1.0UF 1.0UF
    VID2 R_VID2 16 20 G1
    2 7
    VID2 G1 L14
    R19
    VID3 R_VID3 15
    VID3 IFB
    8 R_VCCVID L_VCCVID
    1 8
    14 1 G2 20 0.8UH-20A
    VID4 G2

    SENSE
    0K

    COMP

    SGND

    GND
    11 VFB_PD

    8
    VFB

    SS
    The LTC1753 incorporates internal pull-ups on VID[4:0].

    D4

    D3

    D2

    D1

    D4

    D3

    D2

    D1
    If your VR IC does not incorporate these, they must

    10
    LTC1753

    6
    go on the motherboard.

    SI4410DY

    SI4410DY
    VRCOMP_PD
    SS_PD

    Q4

    Q3
    G1

    G1
    S3

    S2

    S1

    S3

    S2

    S1
    4

    1
    R16
    JP2 JP3 JP4 JP5
    R_VRCOMP

    C18 8.2K

    150PF C17 C19


    C35
    0.01UF 0.1UF
    220PF
    B
    B
    VID Override Jumpers

    C147 C31 C58 C28 C128 C54

    1
    +

    +
    Do Not Stuff C147

    2700UF

    2700UF

    2700UF

    2700UF

    2700UF
    0.1UF

    2
    Refer to VR Supplier for Layout Guidelines

    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    VRM 8.4
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 2-22-1999_11:02 30 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    VCC3_3 VCC5
    VCC3SBY

    SYSTEM

    16V
    1
    R217
    No stuff.

    100K

    +
    C292
    ICH has internal pullup and debounce on PWRBTN# For test only

    10UF
    2
    R226
    D

    C279
    D 1M
    R225
    PWRBTN# 0.1UF
    14 J20
    0K IRRX
    16 1
    C370
    No stuff. R212
    2
    16 IRTX R_IRTX
    For test only 1.0UF
    R213 82
    3
    SW2 INFRARED
    4
    1 2
    4.7K
    5 KEY

    VCC5 VCC5 VCC3_3 VCC3_3 VCC3_3 3 4


    6
    PBSWITCH
    7
    PBTN_IN
    8
    POWER SW.
    9
    R228
    10

    470 11
    R136 R93 R231
    U11 12
    10K VCC
    10K 10K

    14
    13 KEY
    IDEACTP# 3 4 IDE_ACTIVE H.D. LED
    19 14

    7
    GND U11 15
    VCC
    VCC5

    FP_PD
    SN74LVC07A

    14
    KEY
    C 16
    IDEACTS# 1 2
    19 C
    17

    7
    GND
    R232 18 KEY
    POWER LED
    SN74LVC07A
    PWRLED
    19
    220 KEY
    20
    KEYLOCK#
    16 21
    KEYLOCK
    22

    23

    24 KEY
    AC97SPKR SPEAKER
    26 R233 25
    SPKR_IN R_SPKRIN
    JP22 26 VCC5
    68
    VCC3_3 1 Q11 C FNT_PNL_CONN
    R234
    ICH_SPKR 2
    14 R235 3 SP1
    3 SPKR SPKR_Q1G B 1 68 +
    1
    C378 C373 C258 POS

    2N3904
    2.2K 2
    RP62

    SPKR_NEG 2
    NEG
    5

    E
    0.1UF 470PF 470PF

    4.7K
    FAN Headers Speaker Circuit
    B
    4

    VCC12 VCC3SBY VCC3SBY


    VCC12

    VCC3SBY
    VCC3SBY VCC3SBY

    R97

    R98
    C23

    330

    330
    C363
    0.1UF
    J26 0.1UF J24
    1 1 U5 U5
    VCC VCC
    R188

    14
    14
    2 2 GPIO23_FPLED 3 4 1 2 6 5 GPIO26_FPLED 14
    14
    2 V3SBLED

    3 3 330 On-Board LED indicates the GP23LED GP26LED

    7
    7
    Standby Well is on to prevent
    GND GND
    Hot-Swapping Memory.
    TACH1 TACH2 SN74LVC07A SN74LVC07A
    CR12

    16 16 CR3

    R172

    4.7K
    VCC12 VCC12
    1

    A
    A

    C362 C365

    J27 0.1UF J25 0.1UF


    1 1
    REV:
    2 2 TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    3 3
    1.3
    SYSTEM, PART 1
    DRAWN BY: PROJECT:
    PWM1 PWM2 R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION
    16 16 CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:44 31 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    SYSTEM
    ITP RESET CIRCUIT - FOR DEBUG ONLY

    Power Connector and Reset Control VCC3SBY VCC3SBY

    R99 D
    D
    240

    Power Good Circuit 4


    DBRESET#
    U10
    1 14
    3 DBRST VCC2_5
    VCC5SBY VCC5 APOK_ST 2
    VCC5SBY 7
    VCC_5- SN74LVC08A
    VCC12 U12
    14 U12
    14
    VCC3SBY
    VCC12- VCC3_3 1 2 ST23 3 4

    7 7 R10
    74LVC14A 74LVC14A R90
    SN74LVC06A has 5V input tolerance
    330
    0K
    VCC5SBY U3
    14
    74LVC14A is 5V input tolerant VCC
    R62 J4 1 2 PWRGOOD
    VCC3SBY 4
    4.7K 7 GND
    11 1 DBRPOK 32 SN74LVC06A
    3_3V11 3_3V1
    12 2
    -12V 3_3V2
    U3
    14
    13
    GND13 GND3
    3 VCC3SBY
    VCC U4
    SLP_S3# 5 6 5VPSON 14 4 R91 R92 74LS132 VCC
    14,32 PS_0N
    ATX
    5V4
    ATX_PWOK DBRPOK_DLY 4 14
    6 PWROK#
    7 GND 15 5
    GND15 GND5 5
    SN74LVC06A
    SN74LVC06A is 5V output tolerance 16 6 0K 0K VCC3SBY
    C GND16 5V6 7
    GND
    17
    GND17 GND7
    7 C
    C183 R200
    18 8
    -5V PW_OK
    19 9
    Do Not Stuff C183 4.7K
    5V19 5VSB
    1.0UF U3
    14
    20 10 VCC
    5V20 12V
    3 4 PWROK
    14,28,29
    7 GND
    SN74LVC06A

    R199 Do Not Stuff


    For Debug Only
    1M

    220 Ohm Pull-up to 3.3V is on VRM Sheet


    VRM_PWRGD
    30

    Reset Button
    SW1
    1 2

    R24
    B
    B 3 4 RST_PD

    PBSWITCH 22
    Resume Reset Circuitry
    1

    C45 C185
    +

    JP23 Schmitt Trigger Logic


    0.01UF 10UF using a 22msec delay
    2

    Place JP23 Near Front Panel Header (J20)

    VCC3SBY VCC3SBY

    VCC3SBY

    U12 14 U12 14
    CLOCK POWERDOWN CONTROL 22K V3RSMRST 5 6 ST69 9 8 RSMRST#
    14,28
    R142 7 7
    74LVC14A 74LVC14A
    SLP_S3# R86
    14,29,32
    8.2K
    Do Not Stuff
    C264 For Debug Only
    VCC3SBY R196

    1.0UF 1M
    A
    A
    U10
    14
    32 DBRPOK 4 R84
    6 CK_PWRD CK_PWRDN# 6
    5
    7
    SN74LVC08A 0K

    Do Not Stuff R84 - For Test Only: TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    REV:
    If R84 is Populated, R86 Must Be De-Populated 1.3
    SYSTEM, PART 2
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 12-6-1998_12:54 32 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    PULL-UP RESISTORS AND UNUSED GATES


    PCI BUS VCC5
    ICH0 CPU
    RP59 VCC5 4,33
    PERR#_PU 2 VCC3SBY
    18 RP47
    SERR# 3 SDONEP1 1 8 D
    D 13,17,18,27 17
    PLOCK# 4 SDONEP2 2 7

    VCMOS
    13,17,18 17 RP61
    STOP# 5 SBOP1 3 6 SMBALERT# 1 8
    13,17,18,27 17 14
    DEVSEL# 6 1 SBOP2 4 5 LDRQ#1 2 7
    13,17,18,27 2.7K 17 14 R73
    TRDY# GPIO12 APICD0
    13,17,18,27
    7
    5.6K 14
    3 6 4,13
    IRDY# 8 VCC5 GPIO13 4 5
    150
    13,17,18,27 14 R6
    FRAME# APICD1
    13,17,18,27
    9
    4.7K 4,13
    10
    150
    RP58 RP60
    SDONEP3 SMBDATA 1 8
    9 PULLUP/DOWN
    18
    1 8 11,12,14,25,28
    RESISTOR PAK
    2 7
    SBOP3 2 7
    18
    PTDI SMBCLK 3 6
    RP45 VCC5 17,18
    3 6 11,12,14,25,28 RP50
    PIRQ#D 2
    PTMS INTRUDER# 4 5 NMI 1 8
    13,17,18 17,18
    4 5 14 4,13
    PIRQ#C 3 CPUSLP# 2 7
    13,17,18 5.6K 4.7K 4,13
    PIRQ#B 4
    VCC5 STPCLK# 3 6
    13,17,18 4,13
    PIRQ#A 5
    VCC3_3 SMI# 4 5
    13,17,18,27 4,13
    PREQ#3 6 1
    13,27 2.7K 150
    PREQ#2 7 RP51 RP56
    13,18 RP49
    PREQ#1 PU1_ACK64# 1 8 REQ#B/GPIO1 1 8
    INTR
    13,17
    8 17 13 4,13
    1 8

    PREQ#0 PU1_REQ64# 2 7 2 7
    INIT#
    13,17
    9 17 4,13,15
    2 7
    C PU2_ACK64# 3 6 GNT#B/GPIO17 3 6
    IGNNE#
    10 17 13 4,13
    3 6 C
    PU2_REQ64# 4 5 SERIRQ 4 5
    A20M#
    17 13,16,18 4,13
    4 5
    9 PULLUP/DOWN VCC3_3
    RESISTOR PAK 2.7K 8.2K 150
    RP52
    RP57 R208 PCPCI_REQ#A 1 8
    PGNT#0 PU3_ACK64# 13,18
    13,17
    1 8 18
    2.7K THERM# 2 7
    PGNT#1 2 7 R207 14 R169
    13,17 PU3_REQ64# RCIN# FERR#
    18 13,16
    3 6
    4,13
    PGNT#2 3 6
    2.7K
    13,18 A20GATE 4 5 150
    PGNT#3 4 5 13,16
    13,27
    8.2K
    8.2K
    RP53
    LPC_SMI# 1 8
    14,16
    GPIO7 2 7
    14,18 For Future Compatibility Upgrade
    3 6

    4 5
    R68
    VCC3SBY RTTCTRL
    8.2K 4

    UNUSED GATES VCC3SBY


    1
    RP54
    8
    4
    SLEWCTRL
    R70
    110, 1%

    GPIO22 2 7 110, 1%
    14
    U10 LPC_PME# 3 6
    14,16
    9 14
    GPIO21 B
    B VCC3_3 VCC3SBY
    8 14,18
    4 5
    10
    U12 14 8.2K
    7
    11 10 SN74LVC08A
    VCC5
    7
    74LVC14A

    RP55
    U11 VCC
    U5 VCC 14
    U10
    1 8
    12
    14

    14

    11
    9 8 9 8 U12 14 13 2 7
    13 12
    IRQ14
    7

    7 3 6
    GND GND
    SN74LVC08A 13,19
    SN74LVC07A SN74LVC07A 7 IRQ15 4 5
    74LVC14A 13,19
    8.2K
    U11 VCC
    U5 VCC VCC3SBY VCC5SBY
    14

    14

    11 10 11 10
    R166
    AC_SDIN0
    7

    14,26
    GND GND
    SN74LVC07A SN74LVC07A
    10K R170
    U4 AC_SDIN1
    14,26
    74LS132 VCC
    9 14 10K
    U11 U5 U3 8
    14
    VCC VCC VCC 10
    14

    14

    11 10
    13 12 13 12 7
    GND
    7 GND
    7

    A SN74LVC06A

    SN74LVC07A
    GND
    SN74LVC07A
    GND A
    U4
    U3 74LS132 VCC
    14 12 14
    VCC
    13 12 11
    13
    7 GND
    7
    SN74LVC06A GND
    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    PULLUP/PULLDOWN RESISTORS
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 5-26-1999_17:09 33 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    370-pin Socket Decoupling


    VCCVID Decoupling
    Place in 370 PGA Socket Cavity D
    D

    VCCVID
    Bulk Decoupling
    1206 Packages

    C125 C152 C136 C117 C110 C115 C153 C146 C126 C139 C155 C140

    4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF

    VCCVID

    High Frequency Decoupling


    0805 Package

    C
    C

    C121 C142 C118 C113 C120 C149 C145 C107 C154 C156 C148 C135 C132 C137 C138 C151 C108 C141 C143 C134

    1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF

    VTT Decoupling
    0603 Package placed within 200mils of VTT Termination R-packs
    One Capacitor for every 2 R-Packs
    B
    B

    VTT1_5
    1

    C384
    C33 C34 C129 C11 C32 C133 C144 C150 C157 C218 C220 C219 C205 C221 C42
    +

    22UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
    2

    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    VRM DECOUPLING
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 12-8-1998_14:04 34 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    DRAM, CHIPSET, and BULK POWER DECOUPLING

    GMCH Decoupling Display Cache Decoupling ICH0 Decoupling


    Distribute near the 1.8V Distribute near the VCCSUS D
    D power pins of the ICH0. power pins of the ICH0.
    ICH0 3.3V Plane Decoupling:
    VCC3_3 VCC3_3 VCC1_8 VCC3SBY
    VCC1_8 Place 1 .1uF/.01uF pair in each corner,
    Distribute near the power pins
    and 2 on opposite sides close to component
    of both SDRAM components. if they fit.

    10UF
    1

    C372

    1
    1

    1
    C130 C239 C382 C215 C163 C381 C273 C286 C244 C243 C247 C232 C251 C252 C223 C249 C319 C307 C295 C296 C10 C345 C332 C308 C304 C41 C305 C289 C263 C303 C171 C67
    C44
    +

    +
    +

    +
    0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF
    10UF 10UF
    2

    2
    2

    2
    2.2UF

    GMCH Core Plane Decoupling:


    Place 1 .1uF/.01uF pair in each corner,
    and 2 on opposite sides close
    VCC1_8 to component if they fit.

    C
    C

    C131 C164 C242 C237 C214 C233 C380 C383


    System Memory Decoupling Bulk Power Decoupling
    0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF

    VCC5 VCC_5- VCC12 VCC12-


    VCC3_3

    VCC3SBY
    VCC3_3
    DIMM0 Decoupling:
    GMCH 3.3V IO Decoupling: Distribute near DIMM0 Power Pins.

    1
    C62

    1
    22UF

    2
    C70

    1
    22UF C360 C333 C367 C321 C81 C80 C324 C317

    2
    Place near GMCH Display Cache Quadrant C85

    +
    C86 C87 C66 C72

    +
    C82 C83

    +
    0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

    +
    0.1UF 0.1UF 0.1UF 0.1UF

    +
    0.1UF 0.1UF 22UF

    2
    22UF C84

    2
    C69

    1
    22UF 22UF

    1
    1

    C260 C245 C248 C254 C181 C175


    C162
    +

    C234 C343 C341 C350 C278 C288 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
    2

    0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

    3 VOLT Decoupling B
    B
    VCC3_3
    VCC3SBY
    VCC3SBY
    DIMM1 Decoupling:
    Distribute as close as possible to Distribute near DIMM1 Power Pins.
    GMCH System Memory Quadrant

    22UF C352 C298 C283 C291 C354 C285 C339 C160 C250 C78 C340 C318 C172 C376 C320 C240 C256 C127 C338 C322
    1

    C77 C253 C73


    C188
    +

    C170 C169 C262 C377 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
    0.1UF 0.1UF 0.1UF
    0.01UF 0.01UF 0.01UF
    2

    0.01UF

    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    DRAM, ICH, AND GMCH DECOUPLING
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 5-26-1999_17:09 35 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    Revision History (Changes from Rev 0.7)


    She e t De s cription She e t De s cription
    A LL Cosmetic changes to all pages (Re-names nets, re-organized symbol arrangement, etc.) 10 Ganged the tw o CKEs of f of one 4.7K Pull-Up to 3.3V .
    4 Changed FB1 (f errite bead f or PLL analog isolation) to Inductor L2. 11 Fixed Symbol Pinout
    Changed value of R36 to 10 ohms. 12 Fixed Symbol Pinout
    D
    D Replaced R21-R23 w ith 1K R-pack (RP50). Replaced R24-26 and R34 w ith RP44. Removed SMBUS pullups f rom this page. There are pullups on page 32.
    Changed R184 value to 220 ohms Removed Reset Straps f rom MD lines.
    Changed Pull-Up/Dow n Resistor V alues on signals to ITP interf ace and grouped into
    Rpacks/Discretes to make true populate/de-populate Mf g. Option. 13 Updated Ballout
    Floated THERMTRIP# Signal Changed C172 to 0.1UF Cap (HUBREF decoupling)
    Generate GTLREF w ith 1% resistors. Move f rom page 5 to page 4. A dded Resistor Site to Pull F16 to GND f or test/debug.
    Changed BR0# Pull-Dow n to 56Ohm to use existing GTL Term Rpack Slot on sheet 5 14 Updated Ballout
    A dded Jumper Test Option to GND BSEL line. Routed PME# and SMI# to GPIO[13:12] respectively to support w ake events f rom S1.
    Change R35 f rom 51Ohm, 1% to 51Ohm, 5% Pull RTCRST# signal f rom input node of f irst RC delay rather than output node (just other
    side of diode).
    A dded V CMOS Decoupling Moved Clear CMOS to RTCRST# signal and A dded 1K resistor to GND on pin 3 of jumper.
    C
    C
    6 Changed V DDA (pin22) of CK-Whitney to 3.3V Supply pet 0.5 Spec. Change RTC Circuit to pow er V bias straight f rom positive terminal of battery (BA T1).
    Was charged f rom V CCRTC input.
    A dded/Modif ied Decoupling and Pow er Isolation Changed A C_SY NC pull-dow n strap (CPU Saf e Mode Jumper JP14) to A C_SDOUT pull-
    up strap.
    Ganged CPU and GMCH Clock Lines Change C8 and C9 to 12pF caps.
    Isolated USB/DotCLK pow er (pin 27) f rom SDRA M pow er Tied OC#0 and OC#1 together.
    Changed Pow erDow n control signal to NA ND of SLP_S3# and PWR_OK A dd jumper straps to SPKR and A C_SY NC
    Change C146 and C147 f rom 10pF to 12pF Remove Pull-up f rom SLP_S3# signal
    7 Updated GMCH BallOut 15 Updated FWH pinout and labelled symbol as a TSOP Socket.
    Changed GTLREF divider to 1% resistors and GTLREF Decoupling to a 0.1uF (C2) and Updated FWH (Socket) Symbol to include FGPI[4:0], routed A TA 66 cable detect to
    0.001UF (C72) in parallel GPI[1:0] and pulled rest dow n through 8.2K.
    B
    B 8 Updated GMCH BallOut Cominbed Decoupling Caps and reduced to appropriate amount.
    HUBREF Generated f rom tw o 1% resistors w ith 0.1uF (C171) at GMCH HUBREF pin. Changed JP4 to a 2 pole instead of 3 pole jumper.
    Changed C3 to 20pF Cap Replace discrete resistors w ith R-packs. Replaced R84-87 w ith RP42.
    Decoupled System Memory 3.3V balls f rom Local Memory 3.3V balls. System Memory 16 Updated Pinout. Connected new V REF pin to 5V .
    quadrant connects to 3.3V sb plane and Local Memory connects to 3.3V plane. A dded Decoupling to IRRX/IRTX lines.
    9 Updated GMCH BallOut Routed PME# and SMI# to GPIO[13:12] respectively to support w ake events f rom S1.
    Connected V CCDA CA and V CCDA signals to 1.8V through f iltering circuitry. Connected Routed Game Port to game port header, 2nd Serial Port to serial header, PWM/Tach
    V SSDA CA and V SSDA to Digital GND. signals to f an headers, and unused signals to test header.
    A dded Reset Strap jumpers to LMD[31:26]. Routed Unused GPIOs signals to test header.
    Added Oscillator to DotCLK for Test/Debug option Removed JP6 and Grounded CLOCKI.
    A
    Connected Digital V ideo Out signals Connected V TR to V CC3.3 (removed f rom V CC3SB w ell) and added pow er decoupling.
    A
    Changed R70 to 33Ohm and C4 to 20pF. Pulled SY SOPT pin dow n to GND through 4.7K resistor.
    Moved Keylock pull-up sheet 31.

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    REVISION HISTORY, PART 1
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:43 36 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    Revision History (Changes from Rev 0.7)


    Sheet Description Sheet Description
    17 C hanged device num ers (ID SEL w iring) for s lots to AD 16, AD 17, and AD 22. 27 C hanged 93C 46 Pinout.
    R outed additional s ignals required to AD 22 s lot to s upport ISA bridge tes t card.
    18 C hanged device num ers (ID SEL w iring) for s lots to AD 16, AD 17, and AD 22. 28 R eplaced R J45 connector and dis crete m agnetics w ith integrated R J45/m agnetics
    D
    D R outed additional s ignals through 0K res is tors to AD 22 s lot to s upport ISA bridge part and connected accordingly.
    tes t card.
    Added Jum per to route PER R # to IC H /IC H 0 if IC H is populated. Added LAN D is able Jum per.
    19 C onnected pin 34 of each connector to P66D ETEC T and S66D ETEC T(FWH _GPI0 Added IC H /IC H 0 s calability jum pers .
    and FWH _GPI1 res pectively).
    Buffered PC IR ST# s ignal going to pin 1 of ID E connectors to is olate cable loading. 29 Moved Pow er C onnector to Sheet 32
    R em oved Series Term inations from IR Q lines (pulled into IC H 0). R eplaced old VC C 5dual circuit, w ith VC C 3Sby C ircuit w hich generates s upply for
    devices w hich m us t s tay pow ered in S3. R em oved LT1585-3.3 (U 36 on rev0.7).
    20 Is olated each VC C input to U SB s tacked connector through dedicated filtering C hanged U 27 from LT1585-1.5 to LT1587-1.5 and changed dis cretes .
    circuitry.
    Added 47pF EMI caps on U SB data lines . Added V3SB regulator (generated V3SB from V5SB from ATX pow er s upply).
    C onnect U SB through Audio/Modem R is er through 0K res is tors . C hanged 1.8V R egulator des ign from LT1585AD J to LT1587AD J and change d
    C dis cretes . C
    Make OC detect circuitry unique to each port and update polyfus e value. C hanged 2.5V R egulator des ign from LT1585AD J to LT1587AD J and changed
    dis cretes .
    21 R eplaced D B25 connector w ith 2x13 header s o w e can cable out. SMB 30 Added VR M Override Jum pers to VID bus .
    R em oved Series Term ination R es is tors from Ack# and Bus y# s ignals . C hange VR D es ign to VR M8.4 com pliant des ign. U s e LTC 1753 per Linear App
    N ote.
    C hanged Pull-ups to 2.2K 31 Moved R es et and Pow er circuitry to s heet 32
    22 Added 2nd s erial port and connected both through 2x5 headers to cable out Added Infrared, Pow er Sw itch, H ard D rive/Pow er LED s , Keylock, and Speaker
    (R em oved 1 D B9 C onnector). C ircuitry to C om m on Sys tem H eader.
    Added dis crete s olution to level trans late and route R ing Indicate from Serial ports Added 12V Fan H eaders (2 s upporting TAC H outputs , and 2 s upport PWM inputs ).
    to IC H for Wake from S3 on s erial m odem .
    23 Added MID I/Gam e Port circuitry connected through 2x8 header to cable out. Added D ebug LED to m onitor 3.3VSBY Plane
    B
    Increas ed C ap values on Keybd/Mous e lines from 100pF to 470pF. 32 Moved Pull-ups to s heet 33. B

    C hanged the keyboard and m ous e s ym bols to a PS/2 s tacked connector. 32 U pdated new PWR OK/PWR GOOD Generation, R ESET, R SMR ST# circtuitry.
    25 C hanged R GB PI filter caps from 22pF to 3.3pF. 33 Pulled-U p SMBU S interface to 3.3VSby ins tead of 3.3V.
    Added Quick Sw itch to level trans late the C R T Sync, C R T D D C , and Flat Panel R em oved R 164 (FLU SH #) and R 168 (TH ER MTR IP#) pull-ups . R em oved pull-up
    D D C Signals . on PWR GOOD (pulled up on s heet 32). Grouped rem aining pull-ups to 1 1K
    R pack.
    Is olated C K-Whitney from SMBU S in Pow er D ow n through Voltage trans lation C hanged all PC I 3.3V pull-ups to 8.2K per PC I s pec.
    Quick Sw itch.
    C hanged VGA C onnector s ym bol. C om bined like pullups into R -packs w here pos s ible.
    Added EMI C aps on SYN C and D D C Signals . Added 8.2K pull-ups to SER IR Q and IC H 0 unus ed GPIOs .
    26 R outed U SB up the AMR C onnector. Added Pull-U p Sites for FLU SH # and 370PGA Socket Pin W35 to VC MOS for future
    A
    com patibility upgrade.
    A
    R an 5V (ins tead of 5VSB) to Audio Modem R is er. 34 U pdated Proces s or D ecoupling per lates t Guidelines for 370PGA s ocket.
    Added s tuffing option AC ’97 debug port 35 Added Sys tem D ecoupling

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    REVISION HISTORY, PART 2
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:43 37 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    Revision History (Changes from Rev0.9 to Rev0.95)


    Sh e e t De s c r ip t io n Sh e e t De s c r ip t io n
    2 Ch a n g e d "V id e o En c o d e r " b o x o n B lo c k Dia g r a m to " Dig ita l V id e o O u t De v ic e " B o x . 20 Ch a n g e d R1 1 7 ,R1 1 8 ,R1 2 1 ,R1 2 2 f r o m 2 7 o h m to 1 5 o h m- 1 % Re s is to r s
    A d d e d De v ic e Ta b le 22 Ch a n g e R2 0 7 f r o m 4 7 K to 1 0 K
    3 Ch a n g e d Re f e r e n c e De s ig n a to r o n 3 7 0 - p in S o c ke t f r o m J2 0 to X 1 23 Mo v e d RP3 1 f r o m p g . 1 6 to p u ll- u p Ke y /Mo u s e lin e s to f ilte r e d V CC5 .
    4 Ch a n g e d Re f e r e n c e De s ig n a to r o n 3 7 0 - p in S o c ke t f r o m J2 0 to X 1 A d d e d 4 7 0 p F Ca p s o n MIDI lin e s ( C3 2 7 ,C3 2 8 ) .
    D
    D Ch a n g e d C1 f r o m 2 2 u F,3 0 % to 4 7 u F,1 0 % 25 Mo v e d R6 7 ,R6 8 ,R6 9 f r o m S h e e t 9 .
    6 Ch a n g e d S e r ie s Te r min a tio n Re s is to r V a lu e s f r o m 2 2 O h ms to : Cle a n e d Up V G A Co n n e c to r S c h e ma tic
    R3 7 ,R3 8 ,R5 5 ,R5 6 ,R5 7 =4 3 o h m,2 % ;
    R3 9 ,R4 0 ,R4 1 ,R4 2 ,R4 3 ,R4 6 ,R4 7 ,R5 8 ,R5 9 ,R6 0 ,R6 1 =3 3 o h m,2 % ;
    R4 5 ,R4 8 ,R4 9 ,R5 0 ,R5 1 ,R5 2 ,R5 3 ,R5 4 ,R6 3 =3 3 o h m,5 % ; R4 4 ,R2 2 6 =1 0 o h m,5 %
    T’e d REFCL K a n d a d d e d R2 2 6 ( to s e p a r a te te r min a tio n to ICH a n d S IO) . Re n a me d CL K 1 4 to A d d e d Pr o v is io n s to a d d PI Filte r s o n V S Y NC a n d HSY NC L in e s
    S IO_ CL K 1 4 a n d ICH_ CL K 1 4 f o r e a c h n e w NET o u t o f th e T.
    Ch a n g e d C1 4 4 a n d C1 8 5 f r o m 4 .7 u F to 2 2 u F. Ch a n g e d 5 V S u p p ly to Q u ic k S w itc h to p u ll- d o w n o n DIO DE o u tp u t. A ls o p u lle d DDC lin e s u p
    to th e s a me s u p p ly p o w e r in g th e Qu ic k S w itc h .
    8 A d d e d Ca p S ite to G MCH Hu b Clk Ch a n g e R1 3 2 ,R1 3 3 f r o m 8 .2 K to 1 K Pu ll- Up s
    A d d e d 0 K Re s is to r ( R2 3 1 ) in s e r ie s w ith DCL K _ W R 26 Re mo v e d A C9 7 De b u g Co n n e c to r ( J5 )
    9 Ch a n g e d Re f e r e n c e De s ig n a to r o n O s c illa to r S o c ke t f r o m U3 4 to X 2 27 Ch a n g e d R4 p u ll- u p f r o m 6 2 K to 4 .7 K a n d a d d e d 0 .1 u F De c o u p lin g to V IO p in ( C2 6 2 ) .
    Co r r e c te d Co n n e c tio n o f De b u g O s c illa to r f r o m DDCS DA to DOTCL K NET. A d d e d De c o u p lin g f o r L A N Po w e r ( C3 3 6 - C3 4 1 )
    C
    Up d a te d Pin Nu mb e r s to ma tc h G MCH 0 .7 EDS B a llo u t 28 Ch a n g e R1 4 0 /R1 4 1 to 4 .7 K Re s is to r s
    C
    A d d e d 0 K Re s is to r ( R2 3 2 ) in s e r ie s w ith L RCL K 29 Mo d if ie d CK _ PW RDW N# G e n e r a tio n Cir c u itr y to p u ll o f f U3 3 NA ND g a te a n d in v e r t th r o u g h
    U1 3 to g e t c o r r e c t lo g ic le v e l. Pr e v io u s ly it w a s ta p p e d o f f th e b a s e o f B JT Q 6 . Th is w o u ld
    h a v e ke p t CK _ PW RDW N# f r o m c h a r g in g h ig h e r th a n 0 .7 V ( d r o p a c r o s s B E ju n c tio
    A d d e d Ca p S ite to ICH Hu b Clk Ch a n g e d R1 9 1 to 1 0 K , R1 9 2 to 0 K , a n d R1 9 3 to 4 .7 K
    Re p la c e Be a d FB 2 1 w ith In d u c to r ( L 4 ) - 6 8 n H to c r e a te L C f ilte r ( <1 3 0 kHz ) 30 Ch a n g e d Re f e r e n c e De s ig n a to r o n U1 5 a n d U2 5 to Q9 a n d Q 1 0 r e s p e c tiv e ly .
    A d d e d L C f ilte r to 1 .8 V p la n e c o n n e c te d to b a lls U6 a n d E1 9 . Ch a n g e d Re f e r e n c e De s ig n a to r o n U8 to V R5 , U1 1 to V R3 , a n d U2 7 to V R4
    Ch a n g e d Te s t O s c illa to r Cir c u it ( U3 4 ) to r e mo v e s h o r te d ju mp e r a n d a d d d e c o u p lin g . Ch a n g e d C2 6 8 a n d C2 5 9 to 1 .0 u F,X 7 R c a p s
    Ch a n g e d p in n a me s o n 4 8 MHz o s c illa to r s y mb o l.
    Mo v e d R6 7 ,R6 8 ,R6 9 to S h e e t 2 5 . A d d e d 2 mo r e S i4 4 1 0 DY FETs in p a r a lle l w ith tw o th e r e ( Q 7 /Q 8 )
    14 Re n a me NET CL K 1 4 to ICH_ CL K 1 4 Ch a n g e d C1 6 0 - C1 6 3 to 2 7 0 0 u F a n d a d d e d o n e mo r e ( C3 4 2 ) in p a r a lle l.
    Re n a me Pin L 1 to V CCSUS 1 a n d Pin N1 to V CCS US2 Ch a n g e C1 5 3 to 2 2 0 p F
    Re n a me NET G PIO 2 3 to G PIO 2 3 _ FPL ED, a n d NET G PIO2 6 to G PIO 2 6 _ FPL ED Ch a n g e d c o n n e c tio n s o f COMP a n d S S to s h o w th e m r e tu r n in g d ir e c tly to S G ND p in .
    Ro u te d L PC_ SMI# a n d L PC_ PME# to G PIO [5 :6 ] r e s p e c tiv e ly f r o m G PIO[1 2 :1 3 ] r e s p e c tiv e ly . A d d e d In d u c to r ( L 1 3 ) to f ilte r 5 V in p u t to V RM
    B
    B Ch a n g e d V a lu e o f C1 1 f r o m 0 .1 u F to 1 .0 u F 31 Ch a n g e r e f e r e n c e d e s ig n a to r S 1 to S W 1
    15 Ch a n g e d Re f e r e n c e De s ig n a to r o n U9 to X 3 Ch a n g e C7 9 to 1 .0 u F
    15 A d d e d 0 K RPA CK ( RP6 8 ) in s e r ie s to G ROUND o n FW H ID lin e s f o r Te s t/De b u g . A d d Fr o n t Pa n e l Du a l L ED Cir c u it c o n tr o lle d b y ICH G PIO s
    16 Ch a n g e d Pin 8 7 Na me f r o m RTS 1 # _ S Y S OP to RTS 1 # a n d Pin 5 0 n a me f r o m 32 Ch a n g e A TX c o n n e c to r Re f e r e n c e De s ig n a to r f r o m U6 to J2 9 .
    G P2 7 /IO _ S MI# /TES T to S P2 7 /IO_ S MI#
    16 Re n a me NET CL K 1 4 to S IO _ CL K 1 4 Ch a n g e r e f e r e n c e d e s ig n a to r S 2 to S W 2
    33 Re mo v e d Pu ll- Up s f r o m GPIO 2 3 /GPIO 2 6
    16 Mo v e d RP3 1 to p g . 2 3 to p u ll- u p K e y /Mo u s e lin e s to f ilte r e d V CC5 . Pu lle d L DRQ # 1 Up to 3 .3 V S b y ( in s te a d o f 3 .3 V ) .
    17 S w a p p e d A CK 6 4 # a n d REQ6 4 # to r o u te to c o r r e c t p in s p e r PCI s p e c . Ch a n g e d PCI Pu ll- Up Re s is to r ( R9 9 ,R1 0 0 ,RP5 3 ,RP4 6 ,RP4 7 ) v a lu e s f r o m 8 .2 K to 2 .7 K a n d
    c o n n e c te d to 5 V . A ls o c o n n e c te d RP4 0 a n d RP4 3 to 5 V ( f r o m 3 .3 V ) to ma in ta in c o mp a tib ility
    w ith mo r e 5 V PCI c a r d s .
    18 S w a p p e d A CK 6 4 # a n d REQ6 4 # to r o u te to c o r r e c t p in s p e r PCI s p e c . Re mo v e d RP4 9 ( V ID Pu ll- Up s ) S in c e in te r n a l to L TC1 7 5 3
    A Re p la c e d JP6 Ju mp e r w ith 0 K Re s is to r S tu f f in g O p tio n ( R2 3 3 , R2 3 4 ) 35 A d d e d a d d itio n a l De c o u p lin g f o r V a r io u s Co mp o n e n ts ( C3 4 3 - C3 8 9 )
    A
    19 In s e r te d 0 K S tu f f in g Re s is to r s in S e r ie s w ith A TA 6 6 Ca b le De te c t ( R2 3 5 ,R2 3 6 ) Ch a n g e d C2 1 7 - C2 2 0 f r o m 0 .1 u F to 0 .0 1 u F
    19 S w a p p e d 7 4 L S 0 7 o u t f o r 7 4 L V C0 7 A a n d c o n n e c te d to 3 .3 V . A LL Ch a n g e d Re f e r e n c e De s ig n a to r s o n A ll Fe r r ite B e a d s f r o m FB * to L *.

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    REVISION HISTORY, PART 3
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:43 38 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    Revision History (Changes from Rev0.95 to Rev0.99)


    S he e t De scrip tio n S he e t De scrip tio n
    4 Changed C1 to 33uF and L2 to 4.7uH. 24 Change C330 to a 100pF c ap and S c aled B ac k Dec oupling on power planes
    to U28..
    Connec ted E 21 to V CC_DE T P ull-Up S wapped Connec tivity of F TCLK 0 and F TCLK 1.
    D
    D A dded 0603 Cap S ite on CP UHCLK 25 F ix ed Connec tivity of CR2, CR4, CR5, CR6 and CR7. In all c as es P ins 1 and
    2 were s wapped.
    Rem oved RP 50 and routed TCK and TM S to 330ohm pull-ups in RP 44. Change L8,L9,L10 P art Num ber to B LM 11B 750S
    5 Changed Rpac k c onnec tions per Lay out B ac k A nnotation Changed F 3 from 2.0A F us e to 2.5A F us e.
    6 Changed R39-R43,R46,R47,R58-R61 to 33ohm , 5% (from 2% ) 27 Rem oved P ull-up from LA NTCK (U29.D14) and m ade No Connec t. R136
    m oved to S heet 16 to P ull-up LP CP D (U16.27).
    Routed CK _P W RDN# to Cloc k Chip (S LP _S 3# thru 8.2K res is tor by default). Rem oved C338,C339,C340,C341 and Changed C336,C337 to 4.7uF P olariz ed
    Capac itors .
    7 A dded 0603 Cap S ite on G M CHHCLK Changed INTA # (U29.H2) from P IRQ #D to P IRQ #A and Changed LA N IDS E L
    (R142.1) from A D19 to A D20.
    8 Changed HUB RE F V oltage Divider Res is tor V alues (R182 and R185) from 1K - 28 M ade C74 a 470pF -1500V c ap and added "F or E S T Tes ting" Note.
    1% to 301ohm -1% and added A C Dec ouping Dis c rete S ites
    C (C394,C395,R245, R246)
    C
    9 A dded 22ohm s eries term (R242) to LTCLK Net (U22.K 22). Changed J28.14 c onnec tion from A CTLE D to S P E E DLE D and Changed
    R219.1 c onnec tion from V CC3S B Y to A CTLE D
    M oved C323, C324 to page 34 and m ade C324 0.01uF . A dded P rovis ion for Is olating 82559 either on S US _S TA T# or P W RO K
    Rem oved L5 and C325. Change C5 to 33uF . Connec t U22.U6 and U22.E 19 29 Changed Referenc e Des ignator U14 to Q 10 and U16 to Q 11.
    direc t to V CC1_8 P lane. Change U22.A B 21 and U22.A B 23 to c onnec t to
    V CC1_8.
    Rem oved S eries Term s on Digital V ideo O ut P ort Renam ed NE T CK _P W RD to IN_U5, and Deleted c onnec tion to U13 pin 9
    A dded 0K (R31) in s eries with Debug O s c illator Rem oved CK _P W RDW N# NE T, R240
    Routed DC_M D27 (c ore detec t S trap) to 10K to 220 pull-up on V CCDE T net. 30 Connec ted Q 4.{5-8}/Q 7.{5-8}, C193, R150 to Net 5V IN ins tead of direc t to
    V CC5.
    14 Changed C148 from 2.2uF M onolithic to 2.2uF P olariz ed A dded 0K Rpac k (RP 69) in S eries to V ID[3:0] pins of V R3.
    Changed Referenc e Des ignator on B A T1 to X4 (it is a s oc k et footprint ). 31 Changed S wit c h S y m bol to 4-pin devic e to m atc h phy s ic al devic e.
    B
    B 16 P ulled Up S US S TA T to 3.3V through 4.7K (R136, whic h was rem oved from 32 Changed RefDes U6 to J29.
    LA N page) res is tor and dis c onnec ted from ICH0.
    19 Changes to P 66DE TE CT and S 66DE TE CT NE Ts to s upport both Drive and Changed S wit c h S y m bol to 4-pin devic e to m atc h phy s ic al devic e.
    Hos t S ided 80 c onduc tor c able detec tion: A dded C392 and C393 (0.047uF ,
    X7R, 16V , 10% ) to G ND, 0ohm Res is tors in S eries (R235,R236), and 15K P ull-
    downs (R243,R244) to G ND.
    20 F ix ed Connec t ivity of Res is tor R124. US B V 5 Net now Connec t s direc tly to A dded provis ion for s ending early powerok to Cloc k P D# pin for c lean P ower-
    L26 term inal 1, and R124 dis c onnec ted from L26 t erm inal 1. E lim inated up
    unwanted res is tor divider on 5V power pins at US B port.
    A dded S eries Res is tors (0K ) to dec ouple ICH US B s ignals from s tac k ed 33 S wapped S IP Rpac k s on CP U and ICH pull-ups to 4-E lem ent Rpac k s per
    c onnec tor if rout ed up A M R c onnec tor. Lay out B ac k A nnot ation
    A
    22 Changed Net Nam e G _ICHRI# to ICHRI#_C Change RP 48 from 1K Rpac k to 330ohm Rpac k , and R202, and R203 from 1K
    A
    res is tors to 330ohm res is t ors for future upgrade c om patibility .
    35 A dded A ddit ional Dec oupling on V CC12- and V CC12

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    1.3
    REVISION HISTORY, PART 4
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 11-23-1998_13:43 39 OF 40
    8 7 6 5 4 3 2 1
    8 7 6 5 4 3 2 1

    Revision History:Changes from Rev0.99 and On


    Changes from Rev0.99 to Rev1.0
    D
    D
    - Back Annotated from Layout (Reference Designator Changes/Rpack Routing Swaps)
    - Changed Series Term Values on CPU and APIC Clocks to 33ohm (Sheet 6)
    - Changed Series Term Values on Memory, Hub, and DOT Clocks to 22ohm (Sheet 6)
    - Added 10K Pull-Ups on SLP_S3# and SLP_S5# (Sheet 14)
    - Added 2 1200uF Caps on VCC3_3SBY Plane (Sheet 29)

    Changes from Rev1.0 to Rev1.1


    - Removed X1, R77, R78, R79 (Debug Oscillator Socket) from Sheet 9
    - Connected C377 to VCC3_3SBY Plane
    - Corrected Pinout of 2x5 Com Port Headers (Sheet 22)
    C - Added 2x1 Header (JP23) to sheet 32 for Chasses Reset Button C

    Changes from Rev1.1 to Rev1.2


    - Added RP70 and RP71 to Sheet 8 (SM_MA Series Terms)
    - Removed 330Ohm Pull-Ups from FLUSH# and TestHi (W35 on 370-Pin Socket)
    - Added 110Ohm, 1% Pull-Downs to pins S35 and E27 of 370-pin Socket (RTTCTRL and SLEWCTRL)
    - Changed C347 from a 2200pF Cap to a 0.047uF Cap

    Changes from Rev1.2 to Rev1.3


    B
    - Changed VCCDET Net name to VCOREDET B

    - Changed Value of R125 to 174ohm, 1% (from 178ohm, 1%)


    - Changed value of C347 back to 2200pF Cap (from 0.047uF Cap)
    - Designated R126 as No Stuff per SiI 154 Specification
    - Removed R123 pull-up and connected SiI154 pin 13 to reset.
    - Changed RP50, RP49, and R169 from 330ohm to 150ohm

    A
    A

    REV:
    TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
    REVISION HISTORY, PART 5 1.3
    DRAWN BY: PROJECT:
    R PCD PLATFORM DESIGN INTEL(R) 810
    INTEL CORPORATION CHIPSET
    1900 PRAIRIE CITY ROAD PLATFORM COMPONENTS DIVISION SHEET:
    LAST REVISED:
    FOLSOM, CALIFORNIA 95630 5-26-1999_17:09 40 OF 38
    8 7 6 5 4 3 2 1

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