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VHDL Code For 4-Bit Updown Counter

This VHDL code implements a 4-bit up-down counter with an enable signal. The counter uses two processes - one to increment or decrement the counter signal cnt on each rising clock edge depending on the values of enable en and up-down control signal u_d. The second process sets the enable signal high when cnt is 0 and low when cnt is 15 to allow the counter to toggle between the maximum and minimum count values.

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0% found this document useful (0 votes)
130 views4 pages

VHDL Code For 4-Bit Updown Counter

This VHDL code implements a 4-bit up-down counter with an enable signal. The counter uses two processes - one to increment or decrement the counter signal cnt on each rising clock edge depending on the values of enable en and up-down control signal u_d. The second process sets the enable signal high when cnt is 0 and low when cnt is 15 to allow the counter to toggle between the maximum and minimum count values.

Uploaded by

Vinod Parab
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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VHDL CODE FOR 4-BIT UPDOWN COUNTER :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity up_dn_beh4 is
Port ( clk,rst : in STD_LOGIC;
u_d : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (3 downto 0));

end up_dn_beh4;

architecture Behavioral of up_dn_beh4 is

signal cnt: std_logic_vector (3 downto 0);

signal en : std_logic;

begin

q <= cnt;

P1:process(clk)

begin

if(clk ' event and clk = '1') then


if (rst = '1') then cnt <= "0000";
elsif (u_d = '1' and en = '1') then cnt <= cnt + 1;
elsif (en = '0') then cnt <= cnt - 1;

end if;

end if;

end process P1;


P2: process(cnt)

begin

if (cnt = "0000") then en <= '1';


elsif (cnt = "1111") then en <= '0';

end if;
end process P2;
end Behavioral;
FIG3.2 WAVEFORM FOR UP DOWN COUNTER
FIG 3.3 RTL SCHEMATIC VIEW OF UPDOWN COUNTER

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