High Performance Switches and Routers:

TheorySigcomm
and99Practice
August 30, 1999
Harvard University
H ig h Perfo rmance
Swi tc hi ng and Rout in g
Te le com Ce nte rWor ksho p: Se pt 4,1 9 7.

Nick McKeown Balaji Prabhakar

Departments of Electrical Engineering and Computer Science

[email protected] [email protected]
 Tutorial Outline
• Introduction:
What is a Packet Switch?
• Packet Lookup and Classification:
Where does a packet go next?
• Switching Fabrics:
How does the packet get there?
• Output Scheduling:
When should the packet leave?

Copyright 1999. All Rights Reserved 2

 Introduction
What is a Packet Switch?

• Basic Architectural Components

• Some Example Packet Switches
• The Evolution of IP Routers

Copyright 1999. All Rights Reserved 3

 Basic Architectural Components

Congestion
Admission Control Control
Reservation
Control Routing
Output Datapath:
Policing Switching Scheduling per-packet
processing

Copyright 1999. All Rights Reserved 4

 Basic Architectural Components
Datapath: per-packet processing 3.
1.
Output
Forwarding 2. Scheduling
Table
Interconnect
Forwarding
Decision

Forwarding
Table

Forwarding
Decision

Forwarding
Table

Forwarding
Decision

Copyright 1999. All Rights Reserved 5

 Where high performance packet
switches are used
- Carrier Class Core Router
- ATM Switch
- Frame Relay Switch

The Internet Core

Edge Router Enterprise WAN access

& Enterprise Campus Switch

Copyright 1999. All Rights Reserved 6

 Introduction
What is a Packet Switch?

• Basic Architectural Components

• Some Example Packet Switches
• The Evolution of IP Routers

Copyright 1999. All Rights Reserved 7

 ATM Switch
• Lookup cell VCI/VPI in VC table.
• Replace old VCI/VPI with new.
• Forward cell to outgoing interface.
• Transmit cell onto link.

Copyright 1999. All Rights Reserved 8

 Ethernet Switch
• Lookup frame DA in forwarding table.
– If known, forward to correct port.
– If unknown, broadcast to all ports.
• Learn SA of incoming frame.
• Forward frame to outgoing interface.
• Transmit frame onto link.

Copyright 1999. All Rights Reserved 9

 IP Router
• Lookup packet DA in forwarding table.
– If known, forward to correct port.
– If unknown, drop packet.
• Decrement TTL, update header Cksum.
• Forward packet to outgoing interface.
• Transmit packet onto link.

Copyright 1999. All Rights Reserved 10

 Introduction
What is a Packet Switch?

• Basic Architectural Components

• Some Example Packet Switches
• The Evolution of IP Routers

Copyright 1999. All Rights Reserved 11

 First-Generation IP Routers

Shared Backplane Buffer

CPU
Memory

CP Li
U In ne
t er
M fa DMA DMA DMA
em ce
or Line Line Line
y Interface Interface Interface
MAC MAC MAC

Copyright 1999. All Rights Reserved 12

 Second-Generation IP Routers

CPU Buffer
Memory

DMA DMA DMA

Line Line Line
Card Card Card
Local Local Local
Buffer Buffer Buffer
Memory Memory Memory

MAC MAC MAC

Copyright 1999. All Rights Reserved 13

 Third-Generation Switches/Routers

Switched Backplane

L Li Line CPU Line

L LiIn nene
i
I
LiIninnetneeterf Card Card Card
L I
LiIninnetneeterf rfa ace
L I
CPI Initnnetneerterf rfac acece Local Local
nUt er fa ac e
er fa ce e Buffer Buffer
M fa c e
em ce Memory Memory
or
y
MAC MAC

Copyright 1999. All Rights Reserved 14

Fourth-Generation Switches/Routers
Clustering and Multistage

1 2 3 4 5 6 13 14 15 16 17 18 25 26 27 28 29 30

1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16

17 1819 20 21 22 23 2425 26 27 28 29 30 31 32

7 8 9 10 11 12 19 20 21 22 23 24 31 32 21

Copyright 1999. All Rights Reserved 15

 Packet Switches
References
• J. Giacopelli, M. Littlewood, W.D. Sincoskie “Sunshine: A
high performance self-routing broadband packet switch
architecture”, ISS ‘90.
• J. S. Turner “Design of a Broadcast packet switching
network”, IEEE Trans Comm, June 1988, pp. 734-743.
• C. Partridge et al. “A Fifty Gigabit per second IP Router”,
IEEE Trans Networking, 1998.
• N. McKeown, M. Izzard, A. Mekkittikul, W. Ellersick, M.
Horowitz, “The Tiny Tera: A Packet Switch Core”, IEEE
Micro Magazine, Jan-Feb 1997.

Copyright 1999. All Rights Reserved 16

 Tutorial Outline
• Introduction:
What is a Packet Switch?
• Packet Lookup and Classification:
Where does a packet go next?
• Switching Fabrics:
How does the packet get there?
• Output Scheduling:
When should the packet leave?

Copyright 1999. All Rights Reserved 17

 Basic Architectural Components
Datapath: per-packet processing 3.
1.
Output
Forwarding 2. Scheduling
Table
Interconnect
Forwarding
Decision

Forwarding
Table

Forwarding
Decision

Forwarding
Table

Forwarding
Decision

Copyright 1999. All Rights Reserved 18

 Forwarding Decisions
• ATM and MPLS switches
– Direct Lookup
• Bridges and Ethernet switches
– Associative Lookup
– Hashing
– Trees and tries
• IP Routers
– Caching
– CIDR
– Patricia trees/tries
– Other methods
• Packet Classification
Copyright 1999. All Rights Reserved 19
 ATM and MPLS Switches
Direct Lookup

(Port, VCI)
Address

VCI

Data
Memory

Copyright 1999. All Rights Reserved 20

 Forwarding Decisions
• ATM and MPLS switches
– Direct Lookup
• Bridges and Ethernet switches
– Associative Lookup
– Hashing
– Trees and tries
• IP Routers
– Caching
– CIDR
– Patricia trees/tries
– Other methods
• Packet Classification
Copyright 1999. All Rights Reserved 21
 Bridges and Ethernet Switches
Associative Lookups
Associative Advantages:
Memory or CAM
• Simple
Associated
Search
Network Associated Data Disadvantages

{
Address Data
Data Hit? • Slow
48
Address • High Power
log2N
• Small
• Expensive

Copyright 1999. All Rights Reserved 22

 Bridges and Ethernet Switches
Hashing

Associated
Search Data
Data
{
Address

Data
Hashing 16 Hit?
Memory
48 Function Address
log2N

Copyright 1999. All Rights Reserved 23

 Lookups Using Hashing
An example
Memory

#1 #2 #3 #4
Associated
Search Data
Data
48
Hashing Function

CRC-16
16
#1 #2 { Hit?
Address
log2N

#1 #2 #3
Linked lists

Copyright 1999. All Rights Reserved 24

 Lookups Using Hashing
Performance of simple example

 
1   
E R = --- 1 + -------------------------------
-
2  1 – --- 1 M 
 1 – -
 N 

Where:
ER = Expected number of memory references
M = Number of memory addresses in table
N = Number of linked lists
 = M N

Copyright 1999. All Rights Reserved 25

 Lookups Using Hashing
Advantages:
• Simple
• Expected lookup time can be small

Disadvantages
• Non-deterministic lookup time
• Inefficient use of memory

Copyright 1999. All Rights Reserved 26

 Trees and Tries
Binary Search Tree Binary Search Trie

< > 0 1

< > < > log2N 0 1 0 1

010 111
N entries

Copyright 1999. All Rights Reserved 27

 Trees and Tries
Multiway tries

16-ary Search Trie

0000, ptr 1111, ptr

0000, 0 1111, ptr 0000, 0 1111, ptr

000011110000 111111111111

Copyright 1999. All Rights Reserved 28

 Trees and Tries
Multiway tries
Where:
L –1
N D
E w = D L – 11 –  1 – -------  +
  DL 
 D i   1 – D i – 1 N –  1 – D 1 – i  N D = Degree of tree
L = Number of layers/references
i=1
L–1 N = Number of entries in table
N D
E n = 1 + D L 1 – ------- +  Di – D i – 11 – D i – 1 
N
E n = Expected number of nodes
 DL 
i =1 E w = Expected amount of wasted memory

Degree of # Mem # Nodes Total Memory Fraction

Tree References (x106) (Mbytes) Wasted (%)
2 48 1.09 4.3 49
4 24 0.53 4.3 73
8 16 0.35 5.6 86
16 12 0.25 8.3 93
64 8 0.17 21 98
256 6 0.12 64 99.5
Table produced from 215 randomly generated 48-bit addresses
Copyright 1999. All Rights Reserved 29
 Forwarding Decisions
• ATM and MPLS switches
– Direct Lookup
• Bridges and Ethernet switches
– Associative Lookup
– Hashing
– Trees and tries
• IP Routers
– Caching
– CIDR
– Patricia trees/tries
– Other methods
• Packet Classification
Copyright 1999. All Rights Reserved 30
 Caching Addresses
Slow Path

CPU Buffer
Memory
Fast Path

DMA DMA DMA

Line Line Line
Card Card Card
Local Local Local
Buffer Buffer Buffer
Memory Memory Memory

MAC MAC MAC

Copyright 1999. All Rights Reserved 31

 Caching Addresses
LAN:
Average flow < 40 packets

WAN: Huge Number of flows

100%
90%
80%
Cache 70%
60%
Hit 50%
Rate 40%
30%
20%
10%
0%
Cache = 10% of Full Table
Copyright 1999. All Rights Reserved 32
 IP Routers
Class-based addresses

IP Address Space
Class A Class B Class C D

Class A
Routing Table:
212.17.9.4 Class B Exact
Class C Match
212.17.9.0 Port 4

Copyright 1999. All Rights Reserved 33

 IP Routers
CIDR
Class-based:
A B C D
0 232-1

Classless: 128.9.0.0
142.12/19
65/8
128.9/16

0 232-1
216

128.9.16.14
Copyright 1999. All Rights Reserved 34
 IP Routers
CIDR
128.9.19/24
128.9.25/24

128.9.16/20 128.9.176/20

128.9/16

0 232-1

128.9.16.14

Most specific route = “longest matching prefix”

Copyright 1999. All Rights Reserved 35

 IP Routers
Metrics for Lookups

Prefix Port
• Lookup time
65/8 3
128.9.16.14 128.9/16 5 • Storage space
128.9.16/20 2 • Update time
128.9.19/24 7
128.9.25/24 10 • Preprocessing time
128.9.176/20 1
142.12/19 3

Copyright 1999. All Rights Reserved 36

 IP Router
Lookup
H
E Dstn Forwarding Engine
Addr Next Hop
A
Next Hop Computation
D
E
R
Forwarding Table
Destination Next Hop
---- ----
---- ----

Incoming
Packet ---- ----

IPv4 unicast destination address based lookup

Copyright 1999. All Rights Reserved 37

 Need more than IPv4 unicast
lookups
• Multicast
• PIM­SM
– Longest Prefix Matching on the source and group address
– Try (S,G) followed by (*,G) followed by (*,*,RP)
– Check Incoming Interface
• DVMRP:
– Incoming Interface Check followed by (S,G) lookup

• IPv6
• 128­bit destination address field
• Exact address architecture not yet known

Copyright 1999. All Rights Reserved 38

 Lookup Performance Required
Line Line Rate Pkt­size=40B Pkt­size=240B
T1 1.5Mbps 4.68Kpps 0.78Kpps
OC3 155Mbps 480Kpps 80 Kpps
OC12 622Mbps 1.94Mpps 323Kpps
OC48 2.5Gbps 7.81Mpps 1.3Mpps
OC192 10 Gbps 31.25Mpps 5.21Mpps

Gigabit Ethernet (84B packets): 1.49 Mpps

Copyright 1999. All Rights Reserved 39
 Size of the Routing Table

Source: http://www.telstra.net/ops/bgptable.html
Copyright 1999. All Rights Reserved 40
 Ternary CAMs
Associative Memory
Value Mask
10.0.0.0 255.0.0.0 R1
10.1.0.0 255.255.0.0 R2 Next Hop
10.1.1.0 255.255.255.0 R3
10.1.3.0 255.255.255.0 R4
10.1.3.1 255.255.255.255 R4
Priority Encoder

Copyright 1999. All Rights Reserved 41

 Binary Tries
0 1 Example Prefixes
a) 00001
b) 00010
c) 00011
d) 001
d g e) 0101
f
f) 011
g) 100
h i h) 1010
e
i) 1100
a b c
j) 11110000

Copyright 1999. All Rights Reserved

j 42
 Patricia Tree
Example Prefixes
0 1 a) 00001
b) 00010
c) 00011
d) 001
Skip=5 e) 0101
f g j f) 011
d
g) 100
h) 1010
e h i i) 1100
a b c j) 11110000

Copyright 1999. All Rights Reserved 43

 Patricia Tree
Disadvantages Advantages
• Many memory accesses • General Solution
• May need backtracking • Extensible to wider
• Pointers take up a lot of fields
space

Avoid backtracking by storing the intermediate-best matched prefix.

(Dynamic Prefix Tries)

40K entries: 2MB data structure with 0.3-0.5 Mpps [O(W)]

Copyright 1999. All Rights Reserved 44

 Binary search on trie levels
Level 0

Level 8

Level 29

Copyright 1999. All Rights Reserved P 45

 Binary search on trie levels
Example Prefixes
Store a hash table for each prefix length
to aid search at a particular trie level. 10.0.0.0/8
10.1.0.0/16
Length Hash 10.1.1.0/24
8 10.1.2.0/24
10 10.2.3.0/24
12
16 Example Addrs
10.1, 10.2
24 10.1.1.4
10.4.4.3
10.2.3.9
10.2.4.8
10.1.1, 10.1.2, 10.2.3

Copyright 1999. All Rights Reserved 46

 Binary search on trie levels
Disadvantages Advantages
• Multiple hashed memory • Scaleable to IPv6.
accesses.
• Updates are complex.

33K entries: 1.4MB data structure with 1.2-2.2 Mpps [O(log W)]

Copyright 1999. All Rights Reserved 47

 Compacting Forwarding Tables

1 0 0 0 1 0 1 1 1 0 0 0 1 1 1 1

Copyright 1999. All Rights Reserved 48

 Compacting Forwarding Tables
Codeword array
10001010 11100010 10000010 10110100 11000000

R1, 0 R2, 3 R3, 7 R4, 9 R5, 0

0 1 2 3 4

Base index array

0 13
0 1
Copyright 1999. All Rights Reserved 49
 Compacting Forwarding Tables
Disadvantages Advantages
• Scalability to larger • Extremely small data
tables? structure - can fit in
• Updates are complex. cache.

33K entries: 160KB data structure with average 2Mpps [O(W/k)]

Copyright 1999. All Rights Reserved 50

 Multi-bit Tries

16-ary Search Trie

0000, ptr 1111, ptr

0000, 0 1111, ptr 0000, 0 1111, ptr

000011110000 111111111111

Copyright 1999. All Rights Reserved 51

 Compressed Tries
Only 3 memory accesses

L8

L16

L24

Copyright 1999. All Rights Reserved 52

 Routing Lookups in Hardware
Number

Prefix length
Most prefixes are 24-bits or shorter
Copyright 1999. All Rights Reserved 53
 Routing Lookups in Hardware
Prefixes up to 24-bits
224 = 16M entries
142.19.6

Next Hop
1 Next Hop
142.19.6

24
142.19.6.14
14

Copyright 1999. All Rights Reserved 54

 Routing Lookups in Hardware
Prefixes up to 24-bits

128.3.72

1 Next Hop
128.3.72

24 Next Hop
0 Pointer
128.3.72.44

Prefixes above
base 24-bits

Next
Next Hop
Hop
offset
44

Copyright 1999. All Rights Reserved 55

 Routing Lookups in Hardware
Prefixes up to n-bits
2n entries:
i 
m
2  entries

i j Prefixes
0 longer than
N+M bits

N
Next Hop

N+M

Copyright 1999. All Rights Reserved 56

 Routing Lookups in Hardware
Disadvantages Advantages
• Large memory required • 20Mpps with 50ns
(9-33MB) DRAM
• Depends on prefix-length • Easy to implement in
distribution. hardware

Various compression schemes can be employed to decrease the

storage requirements: e.g. employ carefully chosen variable length
strides, bitmap compression etc.

Copyright 1999. All Rights Reserved 57

 IP Router Lookups
References
• A. Brodnik, S. Carlsson, M. Degermark, S. Pink. “Small Forwarding Tables
for Fast Routing Lookups”, Sigcomm 1997, pp 3-14.
• B. Lampson, V. Srinivasan, G. Varghese. “ IP lookups using multiway and
multicolumn search”, Infocom 1998, pp 1248-56, vol. 3.
• M. Waldvogel, G. Varghese, J. Turner, B. Plattner. “Scalable high speed IP
routing lookups”, Sigcomm 1997, pp 25-36.
• P. Gupta, S. Lin, N.McKeown. “Routing lookups in hardware at memory
access speeds”, Infocom 1998, pp 1241-1248, vol. 3.
• S. Nilsson, G. Karlsson. “Fast address lookup for Internet routers”, IFIP Intl
Conf on Broadband Communications, Stuttgart, Germany, April 1-3, 1998.
• V. Srinivasan, G.Varghese. “Fast IP lookups using controlled prefix
expansion”, Sigmetrics, June 1998.

Copyright 1999. All Rights Reserved 58

 Forwarding Decisions
• ATM and MPLS switches
– Direct Lookup
• Bridges and Ethernet switches
– Associative Lookup
– Hashing
– Trees and tries
• IP Routers
– Caching
– CIDR
– Patricia trees/tries
– Other methods
• Packet Classification
Copyright 1999. All Rights Reserved 59
 Providing Value­Added Services
Some examples
• Differentiated services
– Regard traffic from Autonomous System #33 as `platinum­grade’
• Access Control Lists
– Deny udp host 194.72.72.33 194.72.6.64 0.0.0.15 eq snmp
• Committed Access Rate
– Rate limit WWW traffic from sub­interface#739 to 10Mbps
• Policy­based Routing
– Route all voice traffic through the ATM network

Copyright 1999. All Rights Reserved 60

 Packet Classification
H
E
Forwarding Engine
A Action
Packet Classification
D
E
R
Classifier (Policy Database)
Predicate Action
---- ----
---- ----

Incoming
Packet ---- ----

Copyright 1999. All Rights Reserved 61

 Multi-field Packet Classification
Field 1 Field 2 … Field k Action

Rule 1 152.163.190.69/21 152.163.80.11/32 … UDP A1

Rule 2 152.168.3.0/24 152.163.0.0/16 … TCP A2

… … … … … …

Rule N 152.168.0.0/16 152.0.0.0/8 … ANY An

Given a classifier with N rules, find the action associated

with the highest priority rule matching an incoming
packet.
Copyright 1999. All Rights Reserved 62
 Geometric Interpretation in 2D
Field #1 Field #2 Data
R7 R6

P1
P2
Field #2

R3
e.g. (144.24/16, 64/24)
e.g. (128.16.46.23, *) R1
R5 R4
R2

Copyright 1999. All Rights Reserved

Field #1 63
 Proposed Schemes

Pros Cons
Sequential Small storage, scales well with Slow classification rates
Evaluation number of fields
Ternary CAMs Single cycle classification Cost, density, power
consumption
Grid of Tries Small storage requirements and Not easily extendible to
(Srinivasan et fast lookup rates for two fields. more than two fields.
al[Sigcomm Suitable for big classifiers
98])

Copyright 1999. All Rights Reserved 64

 Proposed Schemes (Contd.)
Pros Cons
Crossproducting Fast accesses. Large memory
(Srinivasan et Suitable for requirements. Suitable
al[Sigcomm 98]) multiple fields. without caching for
classifiers with fewer than
50 rules.
Bil-level Parallelism Suitable for Large memory bandwidth
(Lakshman and multiple fields. required. Comparatively
Stiliadis[Sigcomm 98]) slow lookup rate.
Hardware only.

Copyright 1999. All Rights Reserved 65

 Proposed Schemes (Contd.)
Pros Cons
Hierarchical Suitable for multiple Large preprocessing
Intelligent Cuttings fields. Small memory time.
(Gupta and requirements. Good
McKeown[HotI 99]) update time.
Tuple Space Search Suitable for multiple Classification rate can be
(Srinivasan et fields. The basic scheme low. Requires perfect
al[Sigcomm 99]) has good update times hashing for determinism.
and memory
requirements.
Recursive Flow Fast accesses. Suitable for Large preprocessing time
Classification (Gupta multiple fields. and memory
and Reasonable memory requirements for large
McKeown[Sigcomm requirements for real-life classifiers.
99]) classifiers.
Copyright 1999. All Rights Reserved 66
 Grid of Tries
 Dimension 1





  R4
 
   Dimension 2
 
 
R1 R7
 R3 R5 R6
R2
Copyright 1999. All Rights Reserved 67
 Grid of Tries
Disadvantages Advantages
• Static solution • Good solution for two
• Not easy to extend to dimensions
higher dimensions

20K entries: 2MB data structure with 9 memory accesses [at most 2W]

Copyright 1999. All Rights Reserved 68

 Classification using Bit Parallelism
0
1
1
1 1
1 R1
R4 R3
R2
0
0

Copyright 1999. All Rights Reserved 69

 Classification using Bit Parallelism
Disadvantages Advantages
• Large memory • Good solution for
bandwidth multiple dimensions
• Hardware optimized for small classifiers

512 rules: 1Mpps with single FPGA and 5 128KB SRAM chips.

Copyright 1999. All Rights Reserved 70

 Classification Using Multiple Fields
Recursive Flow Classification
Packet Header
2 =2
S 128
2 =2
T 12
Memory
Memory
F1 Memory

F2 Action

F3

2S = 2128 264 224 2 =2

T 12
F4

Fn

Copyright 1999. All Rights Reserved 71

 Packet Classification
References
• T.V. Lakshman. D. Stiliadis. “High speed policy based packet
forwarding using efficient multi-dimensional range matching”,
Sigcomm 1998, pp 191-202.
• V. Srinivasan, S. Suri, G. Varghese and M. Waldvogel. “Fast and
scalable layer 4 switching”, Sigcomm 1998, pp 203-214.
• V. Srinivasan, G. Varghese, S. Suri. “Fast packet classification using
tuple space search”, to be presented at Sigcomm 1999.
• P. Gupta, N. McKeown, “Packet classification using hierarchical
intelligent cuttings”, Hot Interconnects VII, 1999.
• P. Gupta, N. McKeown, “Packet classification on multiple fields”,
Sigcomm 1999.

Copyright 1999. All Rights Reserved 72

 Tutorial Outline
• Introduction:
What is a Packet Switch?
• Packet Lookup and Classification:
Where does a packet go next?
• Switching Fabrics:
How does the packet get there?
• Output Scheduling:
When should the packet leave?

Copyright 1999. All Rights Reserved 73

 Switching Fabrics
• Output and Input Queueing
• Output Queueing
• Input Queueing
– Scheduling algorithms
– Combining input and output queues
– Other non-blocking fabrics
– Multicast traffic

Copyright 1999. All Rights Reserved 74

 Basic Architectural Components
Datapath: per-packet processing 3.
1.
Output
Forwarding 2. Scheduling
Table
Interconnect
Forwarding
Decision

Forwarding
Table

Forwarding
Decision

Forwarding
Table

Forwarding
Decision

Copyright 1999. All Rights Reserved 75

 Interconnects
Two basic techniques
Input Queueing Output Queueing

Usually a non-blocking Usually a fast bus

switch fabric (e.g. crossbar)
Copyright 1999. All Rights Reserved 76
 Interconnects
Output Queueing
Individual Output Queues Centralized Shared Memory
Memory b/w = 2N.R
1

N 1

Memory b/w = (N+1).R N

Copyright 1999. All Rights Reserved 77

 Output Queueing
The “ideal”
1
2 2 1
1
2 1

2 2
1
1

2
1

Copyright 1999. All Rights Reserved 78

 Output Queueing
How fast can we make centralized shared memory?

5ns SRAM
Shared
Memory

1 • 5ns per memory operation

• Two memory operations per packet
2 • Therefore, up to 160Gb/s
• In practice, closer to 80Gb/s
N

200 byte bus

Copyright 1999. All Rights Reserved 79

 Switching Fabrics
• Output and Input Queueing
• Output Queueing
• Input Queueing
– Scheduling algorithms
– Other non-blocking fabrics
– Combining input and output queues
– Multicast traffic

Copyright 1999. All Rights Reserved 80

 Interconnects
Input Queueing with Crossbar
Memory b/w = 2R
Scheduler
Data In

configuration Data Out

Copyright 1999. All Rights Reserved 81

 Input Queueing
Head of Line Blocking

Delay

Load
58.6% 100%

Copyright 1999. All Rights Reserved 82

 Head of Line Blocking

Copyright 1999. All Rights Reserved 83

Copyright 1999. All Rights Reserved 84
Copyright 1999. All Rights Reserved 85
 Input Queueing
Virtual output queues

Copyright 1999. All Rights Reserved 86

 Input Queues
Virtual Output Queues

Delay

Load
100%

Copyright 1999. All Rights Reserved 87

 Input Queueing
Memory b/w = 2R

Scheduler
Can be quite
complex!

Copyright 1999. All Rights Reserved 88

 Input Queueing
Scheduling
Input 1
Q(1,1)
A1,1(t) Matching, M Output 1
A1 (t) D1 (t)
Q(1,n)

?
Input m
Q(m,1)
Output n
Am (t) Dn(t)
Q(m,n)

Copyright 1999. All Rights Reserved 89

 Input Queueing
Scheduling
1 2
7
1 1 1
2 4 2 2 2
2
3 5
3 3 3
4 2 4 4 4
Request Bipartite
Graph Matching
(Weight = 18)

Question: Maximum weight or maximum size?

Copyright 1999. All Rights Reserved 90
 Input Queueing
Scheduling
• Maximum Size
– Maximizes instantaneous throughput
– Does it maximize long-term throughput?
• Maximum Weight
– Can clear most backlogged queues
– But does it sacrifice long-term throughput?

Copyright 1999. All Rights Reserved 91

 Input Queueing
Scheduling

1 1

2 2

1 1

2 2
Copyright 1999. All Rights Reserved 92
 Input Queueing
Longest Queue First or
Oldest Cell First

={ }
Queue Length
Weight 100%
Waiting Time

1 1 1 1 1
10
2 1 2 Maximum weight 2 2
3 1 3 3 3
10
4 1 4 4 4
Copyright 1999. All Rights Reserved 93
 Input Queueing
Why is serving long/old queues better than
serving maximum number of queues?
• When traffic is uniformly distributed, servicing the
maximum number of queues leads to 100% throughput.
• When traffic is non-uniform, some queues become
longer than others.
• A good algorithm keeps the queue lengths matched, and
services a large number of queues.
Uniform traffic Non-uniform traffic
Avg Occupancy

Avg Occupancy

VOQ #
Copyright 1999. All Rights Reserved VOQ # 94
 Input Queueing
Practical Algorithms
• Maximal Size Algorithms
– Wave Front Arbiter (WFA)
– Parallel Iterative Matching (PIM)
– iSLIP
• Maximal Weight Algorithms
– Fair Access Round Robin (FARR)
– Longest Port First (LPF)

Copyright 1999. All Rights Reserved 95

 Wave Front Arbiter

Requests Match
1 1 1 1
2 2 2 2
3 3 3 3
4 4 4 4
Copyright 1999. All Rights Reserved 96
 Wave Front Arbiter

Requests Match

Copyright 1999. All Rights Reserved 97

 Wave Front Arbiter
Implementation

Combinational
1,1 1,2 1,3 1,4 Logic Blocks
2,1 2,2 2,3 2,4

3,1 3,2 3,3 3,4

4,1 4,2 4,3 4,4

Copyright 1999. All Rights Reserved 98

 Wave Front Arbiter
Wrapped WFA (WWFA)
N steps instead of
2N-1

Requests Match

Copyright 1999. All Rights Reserved 99

 Input Queueing
Practical Algorithms
• Maximal Size Algorithms
– Wave Front Arbiter (WFA)
– Parallel Iterative Matching (PIM)
– iSLIP
• Maximal Weight Algorithms
– Fair Access Round Robin (FARR)
– Longest Port First (LPF)

Copyright 1999. All Rights Reserved 100

 Parallel Random
Iterative Matching
Selection Random Selection

1 1 1 1 1 1
#1 2 2 2 2 2 2
3 3 3 3 3 3
4 4 4 4 4 4
Requests Grant Accept/Match
1 1 1 1 1 1
2 2 2 2 2 2
#2
3 3 3 3 3 3
4 4 4 4 4 4
Copyright 1999. All Rights Reserved 101
 Parallel Iterative Matching
Maximal is not Maximum
1 1 1 1
2 2 2 2
3 3 3 3
4 4 4 4
Requests Accept/Match
1 1
2 2
3 3
4 4
Copyright 1999. All Rights Reserved 102
 Parallel Iterative Matching
Analytical Results

Number of iterations to converge:

2 C = # of iterations required to resolve connections
E U i   N
-------
4i N = # of ports
E  C   log N U i = # of unresolved connections after iteration i

Copyright 1999. All Rights Reserved 103

 Parallel Iterative Matching

Copyright 1999. All Rights Reserved 104

 Parallel Iterative Matching

Copyright 1999. All Rights Reserved 105

 Parallel Iterative Matching

Copyright 1999. All Rights Reserved 106

 Input Queueing
Practical Algorithms
• Maximal Size Algorithms
– Wave Front Arbiter (WFA)
– Parallel Iterative Matching (PIM)
– iSLIP
• Maximal Weight Algorithms
– Fair Access Round Robin (FARR)
– Longest Port First (LPF)

Copyright 1999. All Rights Reserved 107

 iSLIP Round-Robin Selection
Round-Robin Selection

1 1 1 1 1 1
#1 2 2 2 2 2 2
3 3 3 3 3 3
4 4 4 4 4 4
Requests Grant Accept/Match
1 1 1 1 1 1
2 2 2 2 2 2
#2
3 3 3 3 3 3
4 4 4 4 4 4
Copyright 1999. All Rights Reserved 108
 iSLIP
Properties
• Random under low load
• TDM under high load
• Lowest priority to MRU
• 1 iteration: fair to outputs
• Converges in at most N iterations. On average <=
log2N
• Implementation: N priority encoders
• Up to 100% throughput for uniform traffic
Copyright 1999. All Rights Reserved 109
 iSLIP

Copyright 1999. All Rights Reserved 110

 iSLIP

Copyright 1999. All Rights Reserved 111

 Programmable
iSLIP
Priority Encoder Implementation

N 1 1 log2N
Grant Accept

N 2 2 log2N
Grant Accept
State Decision

N N N log2N
Grant Accept

Copyright 1999. All Rights Reserved 112

 Input Queueing References
References
• M. Karol et al. “Input vs Output Queueing on a Space-Division Packet
Switch”, IEEE Trans Comm., Dec 1987, pp. 1347-1356.
• Y. Tamir, “Symmetric Crossbar arbiters for VLSI communication
switches”, IEEE Trans Parallel and Dist Sys., Jan 1993, pp.13-27.
• T. Anderson et al. “High-Speed Switch Scheduling for Local Area
Networks”, ACM Trans Comp Sys., Nov 1993, pp. 319-352.
• N. McKeown, “The iSLIP scheduling algorithm for Input-Queued
Switches”, IEEE Trans Networking, April 1999, pp. 188-201.
• C. Lund et al. “Fair prioritized scheduling in an input-buffered
switch”, Proc. of IFIP-IEEE Conf., April 1996, pp. 358-69.
• A. Mekkitikul et al. “A Practical Scheduling Algorithm to Achieve
100% Throughput in Input-Queued Switches”, IEEE Infocom 98,
April 1998.
Copyright 1999. All Rights Reserved 113
 Switching Fabrics
• Output and Input Queueing
• Output Queueing
• Input Queueing
– Scheduling algorithms
– Other non-blocking fabrics
– Combining input and output queues
– Multicast traffic

Copyright 1999. All Rights Reserved 114

 Other Non-Blocking Fabrics
Clos Network

Copyright 1999. All Rights Reserved 115

 Other Non-Blocking Fabrics
Clos Network
Expansion factor required = 2-1/N (but still blocking for multicast)

Copyright 1999. All Rights Reserved 116

 Other Non-Blocking Fabrics
Self-Routing Networks

000 000
001 001
010 010
011 011
100 100
101 101
110 110
111 111

Copyright 1999. All Rights Reserved 117

 Other Non-Blocking Fabrics
Self-Routing Networks
The Non-blocking Batcher Banyan Network
Batcher Sorter Self-Routing Network
3 7 7 7 7 7 7 000
7 2 5 0 4 6 6 001
5 3 2 5 5 4 5
010
2 5 3 1 6 5 4 011
6 6 1 3 0 3 3
100
0 1 0 4 3 2 2
101
1 0 6 2 1 0 1
110
4 4 4 6 2 2 0
111

• Fabric can be used as scheduler.

•Batcher-Banyan network is blocking for multicast.
Copyright 1999. All Rights Reserved 118
 Switching Fabrics
• Output and Input Queueing
• Output Queueing
• Input Queueing
– Scheduling algorithms
– Other non-blocking fabrics
– Combining input and output queues
– Multicast traffic

Copyright 1999. All Rights Reserved 119

 Speedup

• Context
– input-queued switches
– output-queued switches
– the speedup problem
• Early approaches
• Algorithms
• Implementation considerations

Copyright 1999. All Rights Reserved 120

 Speedup: Context
M M
e e
m m
o o
r r
y y

A generic switch

The placement of memory gives

- Output-queued switches
- Input-queued switches
- Combined input- and output-queued switches

Copyright 1999. All Rights Reserved 121

 Output-queued switches

Best delay and throughput performance

- Possible to erect “bandwidth firewalls” between sessions

Main problem
- Requires high fabric speedup (S = N)

Unsuitable for high-speed switching

Copyright 1999. All Rights Reserved 122

 Input-queued switches

Big advantage
- Speedup of one is sufficient
Main problem
- Can’t guarantee delay due to input contention

Overcoming input contention: use higher speedup

Copyright 1999. All Rights Reserved 123

 A Comparison
Memory speeds for 32x32 switch
Output-queued Input-queued
Line Rate Memory Access Time Memory Access Time
BW Per cell BW
100 Mb/s 3.3 Gb/s 128 ns 200 Mb/s 2.12 s
1 Gb/s 33 Gb/s 12.8 ns 2 Gb/s 212 ns
2.5 Gb/s 82.5 Gb/s 5.12 ns 5 Gb/s 84.8 ns
10 Gb/s 330 Gb/s 1.28ns 20 Gb/s 21.2 ns

Copyright 1999. All Rights Reserved 124

 The Speedup Problem
Find a compromise: 1 < Speedup << N
- to get the performance of an OQ switch
- close to the cost of an IQ switch

Essential for high speed QoS switching

Copyright 1999. All Rights Reserved 125

 Some Early Approaches
Probabilistic Analyses
- assume traffic models (Bernoulli, Markov-modulated,
non-uniform loading, “friendly correlated”)
- obtain mean throughput and delays, bounds on tails
- analyze different fabrics (crossbar, multistage, etc)

Numerical Methods
- use actual and simulated traffic traces
- run different algorithms
- set the “speedup dial” at various values

Copyright 1999. All Rights Reserved 126

 The findings

Very tantalizing ...

- under different settings (traffic, loading, algorithm, etc)
- and even for varying switch sizes

A speedup of between 2 and 5 was sufficient!

Copyright 1999. All Rights Reserved 127

 Using Speedup

1
2

1
2

Copyright 1999. All Rights Reserved 128

 Intuition
Bernoulli IID inputs
Speedup = 1
Fabric throughput = .58

Bernoulli IID inputs

Speedup = 2 Fabric throughput = 1.16

I/p efficiency,  = 1/1.16

Ave I/p queue = 6.25

Copyright 1999. All Rights Reserved 129

 Intuition (continued)
Bernoulli IID inputs

Fabric throughput = 1.74

Speedup = 3
Input efficiency = 1/1.74
Ave I/p queue = 1.35

Bernoulli IID inputs

Speedup = 4 Fabric throughput = 2.32

Input efficiency = 1/2.32
Ave I/p queue = 0.75

Copyright 1999. All Rights Reserved 130

 Issues

Need hard guarantees

- exact, not average

Robustness
- realistic, even adversarial, traffic
not friendly Bernoulli IID

Copyright 1999. All Rights Reserved 131

 The Ideal Solution
Inputs Outputs
Speedup = N

?
Speedup << N

Question: Can we find

- a simple and good algorithms
- that exactly mimics output-queueing
- regardless of switch sizes and traffic patterns?

Copyright 1999. All Rights Reserved 132

 What is exact mimicking?

Apply same inputs to an OQ and a CIOQ switch

- packet by packet

Obtain same outputs

- packet by packet

Copyright 1999. All Rights Reserved 133

 Algorithm - MUCF

Key concept: urgency value

- urgency = departure time - present time

Copyright 1999. All Rights Reserved 134

 MUCF

The algorithm

- Outputs try to get their most urgent packets

- Inputs grant to output whose packet is most
urgent, ties broken by port number
- Loser outputs for next most urgent packet
- Algorithm terminates when no more matchings
are possible

Copyright 1999. All Rights Reserved 135

 Stable Marriage Problem

Men = Outputs

Bill John Pedro

Women = Inputs

Hillary Monica Maria

Copyright 1999. All Rights Reserved 136

 An example

Observation: Only two reasons a packet doesn’t get to its output

- Input contention, Output contention
- This is why speedup of 2 works!!
Copyright 1999. All Rights Reserved 137
 What does this get us?
Speedup of 4 is sufficient for exact emulation of FIFO
OQ switches, with MUCF
What about non-FIFO OQ switches?
E.g. WFQ, Strict priority

Copyright 1999. All Rights Reserved 138

 Other results
To exactly emulate an NxN OQ switch

- Speedup of 2 - 1/N is necessary and sufficient

(Hence a speedup of 2 is sufficient for all N)

- Input traffic patterns can be absolutely arbitrary

- Emulated OQ switch may use a “monotone”

scheduling policies

- E.g.: FIFO, LIFO, strict priority, WFQ, etc

Copyright 1999. All Rights Reserved 139

 What gives?
Complexity of the algorithms
- Extra hardware for processing
- Extra run time (time complexity)

What is the benefit?

- Reduced memory bandwidth requirements

Tradeoff: Memory for processing

- Moore’s Law supports this tradeoff

Copyright 1999. All Rights Reserved 140

 Implementation - a closer look
Main sources of difficulty
- Estimating urgency, etc - info is distributed
(and communicating this info among I/ps and O/ps)
- Matching process - too many iterations?

Estimating urgency depends on what is being emulated

- Like taking a ticket to hold a place in a queue
- FIFO, Strict priorities - no problem
- WFQ, etc - problems

Copyright 1999. All Rights Reserved 141

 Implementation (contd)

Matching process
- A variant of the stable marriage problem
- Worst-case number of iterations for SMP = N2
- Worst-case number of iterations in switching =
N
- High probability and average approxly log(N)

Copyright 1999. All Rights Reserved 142

 Other Work
Relax stringent requirement of exact emulation
- Least Occupied O/p First Algorithm (LOOFA)
Keeps outputs always busy if there are packets
By time-stamping packets, it also exactly mimics

- Disallow arbitrary inputs

E.g. leaky bucket constrained
Obtain worst-case delay bounds

Copyright 1999. All Rights Reserved 143

 References for speedup
- Y. Oie et al, “Effect of speedup in nonblocking packet switch’’, ICC 89.

- A.L Gupta, N.D. Georgana, “Analysis of a packet switch with input and
and output buffers and speed constraints”, Infocom 91.
- S-T. Chuang et al, “Matching output queueing with a combined input and
and output queued switch”, IEEE JSAC, vol 17, no 6, 1999.
- B. Prabhakar, N. McKeown, “On the speedup required for combined input
and output queued switching”, Automatica, vol 35, 1999.
- P. Krishna et al, “On the speedup required for work-conserving crossbar
switches”, IEEE JSAC, vol 17, no 6, 1999.
- A. Charny, “Providing QoS guarantees in input buffered crossbar switches
with speedup”, PhD Thesis, MIT, 1998.

Copyright 1999. All Rights Reserved 144

 Switching Fabrics
• Output and Input Queueing
• Output Queueing
• Input Queueing
– Scheduling algorithms
– Other non-blocking fabrics
– Combining input and output queues
– Multicast traffic

Copyright 1999. All Rights Reserved 145

 Multicast Switching

• The problem
• Switching with crossbar fabrics
• Switching with other fabrics

Copyright 1999. All Rights Reserved 146

 Multicasting

1 3 5

4 6

Copyright 1999. All Rights Reserved 147

 Crossbar fabrics: Method 1

Copy network + unicast switching

Copy networks

Increased hardware, increased input contention

Copyright 1999. All Rights Reserved 148

 Method 2
Use copying properties of crossbar fabric

No fanout-splitting: Easy, but low

throughput

Fanout-splitting: higher
throughput, but not as simple.
Leaves “residue”.

Copyright 1999. All Rights Reserved 149

 The effect of fanout-splitting

Performance of an 8x8 switch with and without fanout-splitting

under uniform IID traffic
Copyright 1999. All Rights Reserved 150
 Placement of residue
Key question: How should outputs grant requests?
(and hence decide placement of residue)

Copyright 1999. All Rights Reserved 151

 Residue and throughput
Result: Concentrating residue brings more new work
forward. Hence leads to higher throughput.

But, there are fairness problems to deal with.

This and other problems can be looked at in a unified

way by mapping the multicasting problem onto a
variation of Tetris.

Copyright 1999. All Rights Reserved 152

 Multicasting and Tetris
Input ports
1 2 3 4 5

Residue

1 2 3 4 5
Output ports

Copyright 1999. All Rights Reserved 153

 Multicasting and Tetris
Input ports
1 2 3 4 5

Residue
Concentrated

1 2 3 4 5
Output ports

Copyright 1999. All Rights Reserved 154

 Replication by recycling
Main idea: Make two copies at a time using a binary tree
with input at root and all possible destination outputs at
the leaves.

b
b c x x
a y c
a
x d
y y
e
e
d

Copyright 1999. All Rights Reserved 155

 Replication by recycling (cont’d)
Receive
Reseq Transmit
Output
Table
Network

Recycle

Scaleable to large fanouts. Needs resequencing at outputs and

introduces variable delays.

Copyright 1999. All Rights Reserved 156

 References for Multicasting
• J. Hayes et al. “Performance analysis of a multicast
switch”, IEEE/ACM Trans. on Networking, vol 39, April
1991.
• B. Prabhakar et al. “Tetris models for multicast switches”,
Proc. of the 30th Annual Conference on Information
Sciences and Systems, 1996
• B. Prabhakar et al. “Multicast scheduling for input-queued
switches”, IEEE JSAC, 1997
• J. Turner, “An optimal nonblocking multicast virtual
circuit switch”, INFOCOM, 1994

Copyright 1999. All Rights Reserved 157

 Tutorial Outline
• Introduction:
What is a Packet Switch?
• Packet Lookup and Classification:
Where does a packet go next?
• Switching Fabrics:
How does the packet get there?
• Output Scheduling:
When should the packet leave?

Copyright 1999. All Rights Reserved 158

 Output Scheduling

• What is output scheduling?

• How is it done?
• Practical Considerations

Copyright 1999. All Rights Reserved 159

 Output Scheduling

Allocating output bandwidth

Controlling packet delay

scheduler

Copyright 1999. All Rights Reserved 160

 Output Scheduling

FIFO

Fair Queueing

Copyright 1999. All Rights Reserved 161

 Motivation
• FIFO is natural but gives poor QoS
– bursty flows increase delays for others
– hence cannot guarantee delays

Need round robin scheduling of packets

– Fair Queueing
– Weighted Fair Queueing, Generalized Processor Sharing

Copyright 1999. All Rights Reserved 162

 Fair queueing: Main issues
• Level of granularity
– packet-by-packet? (favors long packets)
– bit-by-bit? (ideal, but very complicated)

• Packet Generalized Processor Sharing (PGPS)

– serves packet-by-packet
– and imitates bit-by-bit schedule within a tolerance

Copyright 1999. All Rights Reserved 163

 How does WFQ work?

WR = 1
WG = 5
WP = 2

Copyright 1999. All Rights Reserved 164

 Delay guarantees

• Theorem

If flows are leaky bucket constrained and all nodes

employ GPS (WFQ), then the network can
guarantee worst-case delay bounds to sessions.

Copyright 1999. All Rights Reserved 165

 Practical considerations
• For every packet, the scheduler needs to
– classify it into the right flow queue and maintain a linked-list
for each flow
– schedule it for departure

• Complexities of both are o(log [# of flows])

– first is hard to overcome
– second can be overcome by DRR

Copyright 1999. All Rights Reserved 166

 Deficit Round Robin

50 700 250 500

250
750

400 600 500

1000

200 600 100 400

500

Good approximation of FQ
Much simpler to implement 500 Quantum size

Copyright 1999. All Rights Reserved 167

 But...

• WFQ is still very hard to implement

– classification is a problem
– needs to maintain too much state information
– doesn’t scale well

Copyright 1999. All Rights Reserved 168

 Strict Priorities and Diff Serv
• Classify flows into priority classes
– maintain only per-class queues
– perform FIFO within each class
– avoid “curse of dimensionality”

Copyright 1999. All Rights Reserved 169

 Diff Serv
• A framework for providing differentiated QoS
– set Type of Service (ToS) bits in packet headers
– this classifies packets into classes
– routers maintain per-class queues
– condition traffic at network edges to conform to

class requirements
May still need queue management inside the network

Copyright 1999. All Rights Reserved 170

 References for O/p Scheduling
- A. Demers et al, “Analysis and simulation of a fair queueing algorithm”,
ACM SIGCOMM 1989.
- A. Parekh, R. Gallager, “A generalized processor sharing approach to
flow control in integrated services networks: the single node
case”, IEEE Trans. on Networking, June 1993.
- A. Parekh, R. Gallager, “A generalized processor sharing approach to
flow control in integrated services networks: the multiple node
case”, IEEE Trans. on Networking, August 1993.
- M. Shreedhar, G. Varghese, “Efficient Fair Queueing using Deficit Round
Robin”, ACM SIGCOMM, 1995.
- K. Nichols, S. Blake (eds), “Differentiated Services: Operational Model
and Definitions”, Internet Draft, 1998.

Copyright 1999. All Rights Reserved 171

 Active Queue Management
• Problems with traditional queue management
– tail drop
• Active Queue Management
– goals
– an example
– effectiveness

Copyright 1999. All Rights Reserved 172

 Tail Drop Queue Management
Lock-Out

Max Queue Length

Copyright 1999. All Rights Reserved 173

 Tail Drop Queue Management

• Drop packets only when queue is full

– long steady-state delay
– global synchronization
– bias against bursty traffic

Copyright 1999. All Rights Reserved 174

 Global Synchronization

Max Queue Length

Copyright 1999. All Rights Reserved 175

 Bias Against Bursty Traffic

Max Queue Length

Copyright 1999. All Rights Reserved 176

 Alternative Queue Management
Schemes
• Drop from front on full queue

• Drop at random on full queue

 both solve the lock-out problem

 both have the full-queues problem

Copyright 1999. All Rights Reserved 177

 Active Queue Management
Goals
• Solve lock-out and full-queue problems
– no lock-out behavior
– no global synchronization
– no bias against bursty flow
• Provide better QoS at a router
– low steady-state delay
– lower packet dropping

Copyright 1999. All Rights Reserved 178

 Active Queue Management
• Problems with traditional queue management
– tail drop
• Active Queue Management
– goals
 an example
– effectiveness

Copyright 1999. All Rights Reserved 179

 Random Early Detection (RED)
Pk P2 P1

maxth qavg minth


if qavg < minth: admit every packet

else if qavg <= maxth: drop an incoming packet
with p = (qavg - minth)/(maxth - minth)

else if qavg > maxth: drop every incoming packet

Copyright 1999. All Rights Reserved 180

 Effectiveness of RED: Lock-Out

• Packets are randomly dropped

• Each flow has the same probability of being discarded

Copyright 1999. All Rights Reserved 181

Effectiveness of RED: Full-Queue
• Drop packets probabilistically in anticipation of congestion (not when queue is full)

• Use qavg to decide packet dropping probability: allow instantaneous bursts

• Randomness avoids global synchronization

Copyright 1999. All Rights Reserved 182

 What QoS does RED Provide?
• Lower buffer delay: good interactive service
– qavg is controlled to be small
• Given responsive flows: packet dropping is reduced
– early congestion indication allows traffic to throttle back before congestion
• Given responsive flows: fair bandwidth allocation

Copyright 1999. All Rights Reserved 183

 Unresponsive or aggressive flows

• Don’t properly back off during congestion

• Take away bandwidth from TCP
compatible flows
• Monopolize buffer space

Copyright 1999. All Rights Reserved 184

 Control Unresponsive Flows
• Some active queue management schemes

– RED with penalty box

– Flow RED (FRED)
– Stabilized RED (SRED)

identify and penalize unresponsive flows with a bit of extra work

Copyright 1999. All Rights Reserved 185

 Active Queue Management
References
• B. Braden et al. “Recommendations on queue management
and congestion avoidance in the internet”, RFC2309, 1998.
• S. Floyd, V. Jacobson, “Random early detection gateways
for congestion avoidance”, IEEE/ACM Trans. on
Networking, 1(4), Aug. 1993.
• D. Lin, R. Morris, “Dynamics on random early detection”,
ACM SIGCOMM, 1997
• T. Ott et al. “SRED: Stabilized RED”, INFOCOM 1999
• S. Floyd, K. Fall, “Router mechanisms to support end-to-
end congestion control”, LBL technical report, 1997

Copyright 1999. All Rights Reserved 186

 Tutorial Outline
• Introduction:
What is a Packet Switch?
• Packet Lookup and Classification:
Where does a packet go next?
• Switching Fabrics:
How does the packet get there?
• Output Scheduling:
When should the packet leave?

Copyright 1999. All Rights Reserved 187

 Basic Architectural Components

Congestion
Admission Control Control
Reservation
Control Routing
Output Datapath:
Policing Switching Scheduling per-packet
processing

Copyright 1999. All Rights Reserved 188

 Basic Architectural Components
Datapath: per-packet processing 3.
1.
Output
Forwarding 2. Scheduling
Table
Interconnect
Forwarding
Decision

Forwarding
Table

Forwarding
Decision

Forwarding
Table

Forwarding
Decision

Copyright 1999. All Rights Reserved 189