Hennessy and Paterson, Computer Architecture a Quantitative Approach (4th Ed)

Appendix A – Instruction Set Pipelining.

Recap – Generic MIPS 5 stage pipeline

• Pipeline for integer instruction level pipelining is summarized in figure 1.

Figure 1: Generic MIPS 5-stage pipeline

Data path considerations

• Concept of a datapath, figure 2, introduced to summarize the utilization and overlapping of
resources/ instructions.
• Observations,
o Structural hazards avoided through ensuring resource independence;
 Memory – independent Instruction and Data buses;
 Internal General Purpose Registers (GPR) – half cycle clocking;
 Program Counter – conflict with (un)conditional statements.
o Duration of clock cycle fixed by CRITICAL PATH (worst case propagation delay)
of any pipe stage;
 ALL stages use same clock cycle.
o Inter-stage pipeline registers (IF/ID, ID/EX, EX/MEM, MEM/WB) save state of
instruction as it propagates through the pipe.
o Instructions are only active in one pipe stage at a time, Table 1:
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Hennessy and Paterson, Computer Architecture a Quantitative Approach (4th Ed)
Appendix A – Instruction Set Pipelining.

 Actions can only effect the contents of the corresponding pipe stage
(interlocks and forwarding conform to this).
 Availability of any resource (data or hardware) must be assured before an
instruction is “released” from the ID stage;
• Unconditional branch instructions being the only exception, in which case a prediction
mechanism is necessary.

Figure 2: Datapath view of Pipeline.

o From Table 1,
 IF/ID, ID/EX, EX/MEM, MEM/WB denote the pipeline registers used to
store instruction state between each pipe stage.
 IF and ID are independent of instruction type;
 EX is dependent on one of three instruction types → ALU, load/store,
branch;
 MEM is dependent on one of two instruction types → ALU, load/store;
 WB is dependent on one of two instruction types → ALU, load/store;

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Hennessy and Paterson, Computer Architecture a Quantitative Approach (4th Ed)
Appendix A – Instruction Set Pipelining.

o Additionally, the information of Table 1 can be summarized by way of a set of

flows between each pipe stage, Figure 3.

Stage Instruction

IF/ID.IR ←Mem[PC];
IF
IF/ID.NPC, PC ← (if ((EX/MEM.opcode == branch) & EX.MEM.cond)
then { EX/MEM.ALUout } else {PC + 4}
ID/EX.A ← Reg[IF/ID.IR[rs]]; ID/EX.B ← [IF.ID.IR[rt]];
ID
ID/EX.NPC ← IF/ID.NPC; ID/EX.IR ← IF/ID.IR;
ID/EX.Imm ← SIGN-EXTEND(IF/ID.IR[immediate field])
ALU instruction Load / Store instruction Branch instruction

EX EX/MEM.IR ← ID/EX.IR; EX/MEM.IR ← ID/EX.IR;

EX/MEM.ALUout ← ID.EX.A op EX/MEM.ALUout ← ID/EX.A EX/MEM.ALUout ←
ID.EX.B; (or ID/EX.Imm;) + ID/EX.Imm; ID.EX.NPC +
EX/MEM.B ← ID/EX.B; (ID.EX.Imm << 2);
EX/MEM.cond ←
(ID.EX.A == 0)

MEM MEM/WB.IR ← EX/MEM.IR; MEM/WB.IR ← EX/MEM.IR;

MEM/WB.ALUout ← MEM/WB.LMD ←
EX/MEM.ALUout; Mem[EX.MEM.ALUout]; or
Mem[EX/MEM.ALUout] ←
EX/MEM.B;

WB Regs[MEM/WB.IR[rd]] ← For load case:

MEM/WB.ALUout; or, Regs[MEM/WB.IR[rt]] ←
Reg[MEM/WB.IR[rt]] ← MEM/WB.LMD;
MEM/WB.ALUout;

Table 1: MIPS 5-stage Pipe event list

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Hennessy and Paterson, Computer Architecture a Quantitative Approach (4th Ed)
Appendix A – Instruction Set Pipelining.

IF → ID ID → EX EX → MEM MB → WB
IR IR IR IR
NPC NPC
Imm
A
B B
ALUout ALUout
cond LMD
PC, NPC
GPR

Figure 3: Summary of information propagated through pipeline registers.

Control Considerations
• Releasing instruction from ID → EX is called instruction issue;
• MIPS integer pipe,
o tests all data hazards BEFORE instruction issue;
o identifies all necessary forwarding BEFORE instruction issue;
• Limiting tests for data hazards and forwarding to the ID stage simplifies hardware as the
pipeline registers already retain the state of currently issued instructions.
• Inserting a stall,
o Set ID/EX registers to ‘0’ (≡ NOP);
o Recirculate ID/EX register values to retain the stalled instruction at current
position.
• Forwarding control:
o Source ?
o Destination ?
o Implication,
 Perform comparison between destination (EX/MEM.IR and MEM/WB.IR)
against source (ID/EX.IR and EX/MEM.IR);
 Results in a total of 10 different comparisons per instruction, Table 2.
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Appendix A – Instruction Set Pipelining.

 Extension to the multiplexers, Figure 4.

Source Opcode of Destination Opcode Dest. For Comparison
instruction source forwarding (If = forward)
EX/MEM Reg-RegALU Reg-RegALU, ALU-Imm, Top ALU i/p EX/MEM.IR[rd]
== ID/EX.IR[rs]
load/ store, branch ‘A’
EX/MEM Reg-RegALU Reg-RegALU Bttm ALU i/p MEM/WB.IR[rd]
== ID/EX.IR[rt]
‘B’
MEM/WB Reg-RegALU Reg-RegALU, ALU-Imm, Top ALU i/p EX/MEM.IR[rd]
== ID/EX.IR[rs]
load/ store, branch ‘A’
MEM/WB Reg-RegALU Reg-RegALU Bttm ALU i/p EX/MEM.IR[rd]
== ID/EX.IR[rf]
‘B’
EX/MEM ALU-Imm Reg-RegALU, ALU-Imm, Top ALU i/p MEM/WB.IR[rt]
== ID/EX.IR[rs]
load/ store, branch ‘A’
EX/MEM ALU-Imm Reg-RegALU Bttm ALU i/p MEM/WB.IR[rt]
== ID/EX.IR[rt]
‘B’
MEM/WB ALU-Imm Reg-RegALU, ALU-Imm, Top ALU i/p MEM/WB.IR[rt]
== ID/EX.IR[rs]
load/ store, branch ‘A’
MEM/WB ALU-Imm Reg-RegALU Bttm ALU i/p MEM/WB.IR[rt]
== ID/EX.IR[rt]
‘B’
MEM/WB Load Reg-RegALU, ALU-Imm, Top ALU i/p EX/MEM.IR[rt]
== ID/EX.IR[rs]
load/ store, branch ‘A’
MEM/WB Load Reg-RegALU Bttm ALU i/p EX/MEM.IR[rt]
== ID/EX.IR[rt]
‘B’
Table 2: Tests for forwarding in generic MIPS 5 stage pipe
Top & Bttm correspond to the top and bottom ALU inputs, Figure 4.
Multiple instructions writing to the same register are not covered.
‘rt’, ‘rs’, ‘rd’ represent different register indexes.

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Hennessy and Paterson, Computer Architecture a Quantitative Approach (4th Ed)
Appendix A – Instruction Set Pipelining.

Figure 4: Forwarding paths for Generic 5-stage MIPS pipeline

Difficulties in implementing Pipelining

• Exceptions:
o Require that the pipe is flushed, whilst possibly also necessitating saving of the
state for the currently executed instructions.
• For our purposes it will be sufficient to know of their existence!
• Typical examples include,
o I/O device request;
o Invoking an operating system service;
o Tracing instruction execution or other programmer requested interrupt;
o Integer / FP overflow;
o Page fault (not in RAM);
o Memory protection violation;
o H/W malfunction;
o Power Failure.

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