Scribd
Upload
2K views16 pages

Asynchronous FIFO Final

This document describes asynchronous FIFO memory. It discusses how asynchronous FIFO uses two independent clocks for writing and reading data. It provides details on the architecture including dual-port RAM, read/write pointers, full/empty flags, and pointer difference logic. It also describes how to calculate the FIFO depth based on the maximum write rate and minimum read rate to prevent overflow.

Uploaded by

Ayush Katyal
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
2K views16 pages

Asynchronous FIFO Final

This document describes asynchronous FIFO memory. It discusses how asynchronous FIFO uses two independent clocks for writing and reading data. It provides details on the architecture including dual-port RAM, read/write pointers, full/empty flags, and pointer difference logic. It also describes how to calculate the FIFO depth based on the maximum write rate and minimum read rate to prevent overflow.

Uploaded by

Ayush Katyal
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 16

Asynchronous

FIFO
What is FIFO?
• FIFO (First-in-first-out) memories are Special Purpose devices that
implement a basic queue structure that has broad applications in
Computer and Communication Architecture.
• FIFO memory is a Storage device in which data is read out from its
memory array (SRAM) in same order in which it is written in memory.
• The first word written into the memory block is the first word that is read
out of the memory block. Because of this operation it is referred as First-
in-first-out memories.
• This type of memory is used to interface Slow input/output devices to fast
operating computers.
• The FIFO memory is useful as a Data-rate Buffer in which reading and
writing operations are done at independent data rates.
• The Architecture of FIFO is created by surrounding a dual-port memory
array – generally SRAM with a write pointer , read pointer and control
logic as shown in previous slide.

• FIFO is not addressed in a linear fashion but it is made to form a continous


ring of memory that is addressed by two internal pointers

• As entries are written , the write pointer increments and as entries are
read , read pointer increments as well.

• If read pointer fails to advance, the write pointer wraps around the end
of memory array and become equal to read pointer. At this point FIFO is
full
and cannot accepts any more data until reading resumes.
Types of FIFO Memories
• The following types of FIFO memories are available:
1. Asynchronous FIFO memory.
2. Synchronous FIFO memory.
3. Bi-directional FIFO memory.
• The interfaces of FIFO can be synchronous(Single clock for read & Write
operations) or Asynchronous (Two Different clock Domains).
• If Synchronous , then only one clock signal exits and this clock signal is
used for both reading and Writing operations.
• Synchronous FIFO has advantage of improved interface timing because of
flops placed at a device’s inputs and outputs reduce timing requirements
to familiar setup , hold , clock-to-out specifications.
• One common Application of FIFO is in clock domain crossing where we
need to communicate a series of data values from logic block at one clock
frequency to another block operating at different clock frequency.
• This application is governed by Asynchronous FIFO or a Dual-clock
synchronous FIFO.
Asynchronous FIFO
• There are times when a designer needs to interface two systems working
at two different clocks.
• This interfacing is difficult in the sense that design becomes asynchronous
at the boundary of interface, which results in setup and hold violation,
metastability and unreliable data transfers.
• We know that any two systems can be asynchronous to each other when
they operate at two different frequency(Case I) or when they operate at
same frequency, but at two different clock phase angles (Case II)as shown.

•
•

Case – I Case – II
Block Diagram of Asynchronous FIFO
•  In such a case if we need to do data transfer, there are very few methods to achieve this:
1. Handshake Signaling method.
2. Asynchronous FIFO.

Asynchronous FIFO
• Asynchronous FIFO has got two interfaces, one for writing the data into the FIFO and the other for reading the
data out. It has got two clocks, one for writing and the other for reading.
• System A writes the data in the FIFO and System B reads out the data from it.
• To facilitate error free operations, we have FIFO full and FIFO empty signals(With respect to corresponding
clock).
• FIFO full signal is used by system A (as when FIFO is full, we don't want
system A to write data into FIFO, this data will be lost), so it will be driven
by the write clock.
• Similarly, FIFO empty will be driven by the read clock. Here read clock
means system B clock and write clock means system A clock.
• Asynchronous FIFO is used at places when the performance is a matter,
when one does not want to waste clock cycles in handshake signals, when
there is a lot of system resources available.
• So Asynchronous FIFOs are used as buffers between two asynchronous
clock domains to exchange data safely.
• Synchronization is important to understand the signal stability in multi
clock domains since for a traveling signal the new clock domain appears to
be asynchronous.
• If the signal is not synchronized to new clock, the first storage element of
the new clock domain may go to metastable state and affects the
resolution time.
Depth of Asynchronous FIFO

• One of the most interesting architectural decision in the design project is


how to calculate the depth of a FIFO.
• FIFO is an intermediate logic where the data would be buffered or stored .
Smaller FIFO depth can cause overflow scenario and cause a data loss.
• For worst case scenario, difference in the data rate between write and
read should be maximum.
• Thus for write operation maximum data rate should be considered and
for read operation minimum data rate should be considered for
calculating the depth of the FIFO.
• Asynchronous FIFO has a write frequency and a read frequency. Assume
that the write frequency (Fw) is faster than read frequency (Fr).
Depth Calculation
• Fw = 1/Tw and Fr = 1/Tr where Tw and Tr are Time periods of write and
read respectively.
• Transmitter (Write side) wants to transmit "W" words of data. But FIFO
can take only "N" words of data in Tw time. 
So time taken to transmit "W" words is (Tw/N) * W.
• But Receiver can read "P" words in Tr time interval. 
So the Receiver can read ((Tw/N)*W*P)/Tr words in (Tw/N) * W time. 
• Subtract the the data read from FIFO to the data written into the FIFO. 
Here the data written into the FIFO is "W" words 
Data read from the FIFO is ((Tw/N)*W*P)/Tr words.
• FIFO size = W-((Tw/N)*W*P)/Tr
  W = Maximum number of bytes that the transmitter can send 
N = Number of bytes that the transmitter sends per Tw 
Tw = Transmitter's time period 
P = Number of bytes that receiver receives per Tr 
Tr = Receiver's time perio
Verilog Description of Asynchronous FIFO
• First we go through the Architectural block diagram of Asynchronous FIFO

• Here architecture of FIFO is completely characterized by read & Write


independent operations. Dual port RAM and read-write logic circuits with
synchronizers accomplish this task.
• Dual port RAM has two ports-one is for reading and the other one is for
writing operation. When data is written to FIFO write pointer gets
incremented and points to next memory location. Similarly when read
operation takes place .
• To determine full/empty flags and FIFO size, the read pointer (rptr) must
be synchronized to the write domain, and the write pointer (wptr) must be
New Asynchronous FIFO Design
• The block diagram of new Asynchronous Design consists of a dual port
RAM, two 4 bit binary up-counters, address pointer gap generation logic,
full and empty condition generation logic, next read control logic and next
write control logic.
• The naming convention are as follows:
1. d_in: input data; 8 bit width is considered.
2. d_out: output data; 8 bit width is considered
3. w_en: write enable signal
4. r_en: read enable signal
5. r_next_en: read next enable
6. w_next_en: write next enable
7. w_clk: write clock; 10 MHz for this design
8. r_clk: read clock; 50 MHz for this design
9. w_ptr: write address pointer; 4 bit to address depth of 16
10. r_ptr: read address pointer; 4 bit to address depth of 16
11. ptr_diff: address pointer difference; 4 bit width
12. f_full_flag: FIFO full flag; asserted when FIFO is full
13. f_empty_flag: FIFO empty flag; asserted when FIFO is empty
14. f_half_full_flag: FIFO half full flag; asserted when FIFO is half full
15. f_almost_full_flag: FIFO almost full flag; asserted when FIFO is
almost full(configurable)
16. f_almost_empty_flag: FIFO almost empty flag; asserted when FIFO
is almost empty(configurable)
• Dual Port RAM
- For this design depth of the RAM is considered to be 16 and the width is 8
- Data is written to FIFO memory only if FIFO is not full and write enable
signal w_en is enabled. Similarly data is read out of memory location only if
FIFO is not empty and read enable signal r_en is active.
• Binary Counters
- Four bit binary up counters are used to generate address for read and
write port.
- These address generators have external reset and enable signals called as
w_next_en and r_next_en which are generated and controlled by next
write control logic and next read control logic.
- Single reset input is mapped for both counters which resets both read and
write pointers.
• Address pointer gap generation logic
- The blocks compare the read and write addresses and gives out the
difference of two address pointers.
- If w_ptr>r_ptr, it finds the gap using relation, ptr_diff=w_ptr-r_ptr. 
-  This block consists of comparators and adder-subtractor.
- These modules always calculate the difference between r_ptr and w_ptr
whenever there is a change in r_ptr and w_ptr. Thus ptr_diff dynamically
reflects the status of the FIFO.
• Full and Empty Generation logic
- This logic takes ptr_diff as input and generates the required condition. If
ptr_diff=0, empty condition is generated and if ptr_diff =15 full condition is
generated.
-  Since pointer differences is calculated with respect to both read and write
clocks, FIFO status assertion is immediate with zero clock delay.
• Next read and write control logic
- These control blocks decide the enabling of read and write once the empty
and full conditions are asserted.
THANK YOU

You might also like