Toplevel file

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Top_Level_RS232 is
port ( Rxd: in std_logic;
send,Reset: in std_logic;
SystemClock: in std_logic;
DataIn: in std_logic_vector (7 downto 0);
An: out std_logic_vector (3 downto 0);
Ca, Cb, Cc, Cd, Ce, Cf, Cg,ground: out std_logic;
Txd: out std_logic;
RxdData: out std_logic_vector (7 downto 0));
end Top_Level_RS232;

architecture Behavioral of Top_Level_RS232 is

--component PULLDOWN
--port ( O : out std_ulogic);
--end component;

component RS232
port
( Reset, Clock16x, Rxd: in std_logic;
Send: in std_logic;
DataIn: in std_logic_vector(7 downto 0);
DataOut1: out std_logic_vector (7 downto 0);
Txd: out std_logic);
end component;

component D4to7
port ( Q: in std_logic_vector (3 downto 0);
Seg: out std_logic_vector (6 downto 0));
end component;
component scan4digit
port ( Digit3, Digit2, Digit1, Digit0: in std_logic_vector(6 downto 0);
Clock: in std_logic; An : out std_logic_vector(3 downto 0);
Ca, Cb, Cc, Cd, Ce, Cf, Cg: out std_logic);
end component;

signal iClock16x: std_logic;

signal iClock : std_logic;
signal iReset : std_logic;
signal iDigitOut3, iDigitOut2, iDigitOut1, iDigitOut0: std_logic_vector (6 downto 0);
signal iDataOut1: std_logic_vector (7 downto 0);

1
signal iDataOut2: std_logic_vector (7 downto 0);
signal iCount9: std_logic_vector (8 downto 0);

begin

ground <= '0';

RxdData <= iDataOut1;
iDataOut2 <= DataIn;

process (SystemClock)
begin
if rising_edge(SystemClock) then
if Reset = '1' then
iCount9 <= (others=>'0');
elsif
iCount9 = "101000101" then -- the divider is 325, or "101000101"
iCount9 <= (others=>'0');
else iCount9 <= iCount9 + '1';
end if;
end if;
end process;

iClock16x <= iCount9(8);

U1: RS232 port map

(
Reset => Reset,
--Clock16x => iClock16x,
Clock16x => Systemclock,
Rxd => Rxd,
Send => Send,
DataIn => DataIn,
DataOut1 => iDataOut1,
Txd => Txd);

U2: D4to7 port map (

Q => iDataOut1(3 downto 0),
Seg => iDigitOut0);

U3: D4to7 port map (

Q => iDataOut1(7 downto 4),
Seg => iDigitOut1);

U4: D4to7 port map (

Q => iDataOut2(3 downto 0),
Seg => iDigitOut2);

U5: D4to7 port map (

Q => iDataOut2(7 downto 4),
Seg => iDigitOut3);

2
U6: scan4digit port map (
Digit3 => iDigitOut3,
Digit2 => iDigitOut2,
Digit1 => iDigitOut1,
Digit0 => iDigitOut0,
Clock => SystemClock,
An => An,
Ca => Ca,
Cb => Cb,
Cc => Cc,
Cd => Cd,
Ce => Ce,
Cf => Cf,
Cg => Cg);
--PULLDOWN1 : PULLDOWN port map( O => send );
--PULLDOWN2 : PULLDOWN port map( O => reset);
--PULLDOWN3 : PULLDOWN port map( O => Datain(4) );
--PULLDOWN4 : PULLDOWN port map( O => Datain(5) );
--PULLDOWN5 : PULLDOWN port map( O => Datain(6) );
--PULLDOWN6 : PULLDOWN port map( O => Datain(7) );
end Behavioral;

RS232 controller

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RS232 is
port( Reset, Clock16x, Rxd, Send: in std_logic;
DataIn: in std_logic_vector(7 downto 0);
DataOut1: out std_logic_vector (7 downto 0);
Txd: out std_logic);
end RS232;

architecture RS232_Arch of RS232 is

3
component Rs232Rxd
port( Reset, Clock16x, Rxd: in std_logic;
DataOut1: out std_logic_vector (7 downto 0));
end component;

component Rs232Txd
port( Reset, Send, Clock16x: in std_logic;
DataIn: in std_logic_vector(7 downto 0);
Txd: out std_logic);
end component;

begin
u1: Rs232Rxd port map(
Reset => Reset,
Clock16x => Clock16x,
Rxd => Rxd,
DataOut1 => DataOut1);

u2: Rs232Txd port map(

Reset => Reset,
Send => Send,
Clock16x => Clock16x,
DataIn => DataIn,
Txd => Txd);

end RS232_Arch;

RS232Rxd.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Rs232Rxd is
port( Reset, Clock16x, Rxd: in std_logic;
DataOut1: out std_logic_vector (7 downto 0));
end Rs232Rxd;

architecture Rs232Rxd_Arch of Rs232Rxd is

attribute enum_encoding: string;

-- state definitions

4
type stateType is (stIdle, stData, stStop, stRxdCompleted);
attribute enum_encoding of statetype: type is "00 01 11 10";
signal presState: stateType;
signal nextState: stateType;
signal iReset, iRxd1, iRxd2, iClock1xEnable, iClock1x, iEnableDataOut: std_logic ;
signal iClockDiv: std_logic_vector (3 downto 0) ;
signal iDataOut1, iShiftRegister: std_logic_vector (7 downto 0) ;
signal iNoBitsReceived: std_logic_vector (3 downto 0) ;

begin

process (Clock16x)
begin
if Clock16x'event and Clock16x = '1' then
if Reset = '1' or iReset = '1' then
iRxd1 <= '1';
iRxd2 <= '1';
iClock1xEnable <= '0';
iClockDiv <= (others=>'0');
else
iRxd1 <= Rxd;
iRxd2 <= iRxd1;
end if;
if iRxd1 = '0' and iRxd2 = '1' then
iClock1xEnable <= '1';
elsif iClock1xEnable = '1' then
iClockDiv <= iClockDiv + '1';
end if;
end if;
end process;

iClock1x <= iClockDiv(3);

process (iClock1xEnable, iClock1x)

begin
if iClock1xEnable = '0' then
iNoBitsReceived <= (others=>'0');
presState <= stIdle;
elsif iClock1x'event and iClock1x = '1' then
iNoBitsReceived <= iNoBitsReceived + '1';
presState <= nextState;
end if;
if iClock1x'event and iClock1x = '1' then
if iEnableDataOut = '1' then
iDataOut1 <= iShiftRegister;
else
iShiftRegister <= Rxd & iShiftRegister(7 downto 1);
end if;
end if;
end process;
DataOut1 <= iDataOut1;

5
process (presState, iClock1xEnable, iNoBitsReceived)
begin
-- signal defaults
iReset <= '0';
iEnableDataOut <= '0';
case presState is
when stIdle =>
if iClock1xEnable = '1' then
nextState <= stData;
else
nextState <= stIdle;
end if;
when stData =>
if iNoBitsReceived = "1001" then
iEnableDataOut <= '1';
nextState <= stStop;
else
iEnableDataOut <= '0';
nextState <= stData;
end if;
when stStop =>
nextState <= stRxdCompleted;
when stRxdCompleted =>
iReset <= '1';
nextState <= stIdle;
end case;
end process;
end Rs232Rxd_Arch;

6
RS232Txd.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Rs232Txd is
port( Reset, Send, Clock16x: in std_logic;
DataIn: in std_logic_vector(7 downto 0);
Txd: out std_logic);
end Rs232Txd;

architecture Rs232Txd_Arch of Rs232Txd is

attribute enum_encoding: string;

-- state definitions
type stateType is (stIdle, stData, stStop, stTxdCompleted);
attribute enum_encoding of stateType: type is "00 01 11 10";
signal presState: stateType;
signal nextState: stateType;
signal iSend, iReset, iClock1xEnable, iEnableTxdBuffer, iEnableShift: std_logic;
signal iTxdBuffer: std_logic_vector (9 downto 0);
signal iClockDiv: std_logic_vector (3 downto 0);
signal iClock1x: std_logic;
signal iNoBitsSent: std_logic_vector (3 downto 0);

Begin
Process (Clock16x,Send,iReset,iClock1xEnable,Reset)
Begin
if Clock16x 'event and Clock16x= '1' then
if Reset = '1' or iReset = '1' then
iClock1xEnable <= '0';
iClockDiv <= (others=>'0');
end if;

7
if send ='1' then
iClock1xEnable<='1';
end if;
if iClock1xEnable ='1' then
iClockDiv<= iClockDiv+'1';
end if;
end if;
end process;

iClock1x <= iClockDiv(3);

Process (iClock1xEnable,iClock1x,iEnableTxdBuffer,iEnableShift)

Begin
if iClock1xEnable ='0' then
iNoBitsSent <= (others=>'0');
presState <= stIdle;
Txd <= '1';

if iEnableTxdBuffer ='1' then

iTxdBuffer <= '1' & Datain &'0';
end if;

else if iClock1x 'event and iClock1x ='1' then

iNoBitsSent <= iNoBitsSent+'1';
presState <= nextState;
if iEnableShift <= '1' then
iTxdBuffer <= '1' & iTxdBuffer(9 downto 1);
Txd <= iTxdBuffer(0);
end if;
end if;
end if;
end process;

Process (presState,iClock1xEnable,iNoBitsSent)

Begin
iReset <= '0';
iEnableShift <= '0';
iEnableTxdBuffer <= '0';
Case presState is
When stIdle =>
iEnableTxdBuffer <= '1';
if iClock1xEnable ='1' then
nextState <= stData;
else
nextState <= stidle;
end if;
When stData =>
iEnableShift <= '1';
iEnableTxdBuffer <= '1';
if iNoBitsSent <= "1001" then
nextState <= stStop;

8
 iEnableShift <= '0';
iEnableTxdBuffer <= '0';
else
nextState <= stData;
end if;

When stStop =>

nextState <= stTxdCompleted;

When stTxdCompleted =>

iReset <= '1';
nextState <= stidle;

End Case;
End Process;
End Rs232Txd_Arch;