Scribd Logo
Upload

Welcome to Scribd!

  • 109 views

    Instruction Description Clock Cycles Number of Bytes

    Uploaded by

    Kashyap Shah
    The document summarizes instruction timings for the Intel 8086 microprocessor. It lists common instructions like ADD, SUB, MUL, DIV and MOV along with the number of clock cycles and bytes each instruction takes to execute in different operating modes, such as operating on registers versus memory. It also provides timing details for other operations like conditional jumps, calls, returns and memory addressing modes. In general, instructions take fewer cycles when operating on registers compared to memory, and memory operations have variable cycles depending on the addressing mode used.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    Instruction Description Clock Cycles Number of Bytes

    Uploaded by

    Kashyap Shah
    109 views5 pages
    The document summarizes instruction timings for the Intel 8086 microprocessor. It lists common instructions like ADD, SUB, MUL, DIV and MOV along with the number of clock cycles and bytes each instruction takes to execute in different operating modes, such as operating on registers versus memory. It also provides timing details for other operations like conditional jumps, calls, returns and memory addressing modes. In general, instructions take fewer cycles when operating on registers compared to memory, and memory operations have variable cycles depending on the addressing mode used.

    Original Title

    Instruction_Timing

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document summarizes instruction timings for the Intel 8086 microprocessor. It lists common instructions like ADD, SUB, MUL, DIV and MOV along with the number of clock cycles and bytes each instruction takes to execute in different operating modes, such as operating on registers versus memory. It also provides timing details for other operations like conditional jumps, calls, returns and memory addressing modes. In general, instructions take fewer cycles when operating on registers compared to memory, and memory operations have variable cycles depending on the addressing mode used.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    109 views5 pages

    Instruction Description Clock Cycles Number of Bytes

    Uploaded by

    Kashyap Shah
    The document summarizes instruction timings for the Intel 8086 microprocessor. It lists common instructions like ADD, SUB, MUL, DIV and MOV along with the number of clock cycles and bytes each instruction takes to execute in different operating modes, such as operating on registers versus memory. It also provides timing details for other operations like conditional jumps, calls, returns and memory addressing modes. In general, instructions take fewer cycles when operating on registers compared to memory, and memory operations have variable cycles depending on the addressing mode used.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 5

    Intel 8086 Instruction Timing 1

    Instruction Description Clock Cycles Number of Bytes


    NEG Reg 3 2
    Mem 16 + EA 2-4
    DEC, INC 16-bit Reg 2 1
    8-bit Reg 3 2
    Mem 15 + EA 2-4
    ADD, SUB Reg à Reg 3 2
    Mem à Reg 9 + EA 2-4
    Reg à Mem 16 + EA 2-4
    Immediate à Reg 4 3-4
    Immediate à Mem 17 + EA 3-6
    Immediate à Acc 4 2-3
    CMP Reg à Reg 3 2
    Mem à Reg 9 + EA 2-4
    Reg à Mem 9 + EA 2-4
    Immediate à Reg 4 3-4
    Immediate à Mem 10 + EA 3-6

    Instruction Description Clock Cycles Number of Bytes


    CBW Convert byte to 2 1
    word
    CWD Convert word to 5 1
    double word
    MUL 8-bit Reg 70 – 77 2
    16-bit Reg 118 – 133 2
    8-bit Mem (76 – 83) + EA 2-4
    16-bit Mem (124 – 139) + EA 2-4
    IMUL 8-bit Reg 80-98 2
    16-bit Reg 128 – 154 2
    8-bit Mem (86 – 104) + EA 2-4
    16-bit Mem (134 – 160) + EA 2-4
    DIV 8-bit Reg 80 - 90 2
    16-bit Reg 144 - 162 2
    8-bit Mem (86 – 96) + EA 2-4
    16-bit Mem (150 – 168) + EA 2-4
    IDIV 8-bit Reg 101 – 112 2
    16-bit Reg 165 – 184 2
    8-bit Mem (107 – 118) + EA 2-4
    16-bit Mem (171 – 190) + EA 2-4
    Intel 8086 Instruction Timing 2

    Instruction Description Clock Cycles Number of Bytes


    NOT Reg 3 2
    Mem 16 + EA 2-4
    AND, OR, XOR Reg à Reg 3 2
    Mem à Reg 9 + EA 2-4
    Reg à Mem 16 + EA 2-4
    Immediate à Reg 4 3-4
    Immediate à Mem 17 + EA 3-6
    Immediate à Acc 4 2-3
    RCL, RCR, ROL, Reg with 1 shift 2 2
    ROR, SAL/SHL,
    SAR/SHR
    Reg with variable 8 + 4/bit 2
    shift
    Mem with 1 shift 15 + EA 2-4
    Mem with variable 20 = EA + 4/BIT 2-4
    shift
    TEST Reg à Reg 3 2
    Mem à Reg 9 + EA 2-4
    Immediate à Acc 4 2-3
    Immediate à Reg 5 3-4
    Immediate à Mem 11 + EA 3-6
    Intel 8086 Instruction Timing 3

    Instruction Description Clock Cycles Number of Bytes


    CALL Intrasegment direct 19 3
    Intrasegment 16 2
    indirect through
    register
    Intrasegment 21 + EA 2-4
    indirect through
    memory
    Intersegment direct 28 5
    Intersegment 37 + EA 2-4
    indirect
    RET Intrasegment 8 1
    Intrasegment with 12 3
    constant
    Intersegment 18 1
    Intersegment with 17 3
    constant
    Conditional Jump branch taken 16 2
    branch not taken 4 2

    Instruction Description Clock Cycles Number of Bytes


    JMP Intrasegment direct 15 2
    short
    Intrasegment direct 15 3
    Intrasegment direct 15 5
    Intrasegment 18 + EA 2-4
    indirect through
    memory
    Intrasegment 11 2
    indirect through
    register
    Intrasegment 24 + EA 2-4
    indirect
    INT Type 3 52 1
    Not Type 3 51 2
    LEA Load effective 2 + EA 2-4
    address
    LOOP branch taken 17 2
    branch not taken 5 2
    LOOPE, LOOPZ branch taken 18 2
    branch not taken 6 2
    LOOPNE, branch taken 19 2
    LOOPNZ
    branch not taken 5 2
    Intel 8086 Instruction Timing 4

    Instruction Description Clock Cycles Number of Bytes


    MOV Acc à Mem 10 3
    Mem à Acc 10 3
    Reg à Reg 2 2
    Mem à Reg 8 + EA 2-4
    Reg à Mem 9 + EA 2-4
    Immediate à Reg 4 2-3
    Immediate à Mem 10 + EA 3-6
    Reg à SS, DS, ES 2 2
    Mem à SS, DS, ES 8 + EA 2-4
    Seg Reg à Reg 2 2
    Seg Reg à Mem 9 + EA 2-4
    XCHG Reg ßà Acc 3 1
    Reg ßà Mem 17 + EA 2-4
    Reg ßà Reg 4 2
    XLAT 11 1

    Instruction Description Clock Cycles Number of Bytes


    POP Reg 8 1
    Seg Reg SS, DS, ES 8 1
    Mem 17 + EA 2-4
    PUSH Reg 11 1
    Seg Reg 10 1
    Mem 16 + EA 2-4
    POPF 8 1
    PUSHF 10 1
    Intel 8086 Instruction Timing 5

    EA Number of
    Clock Cycles
    Direct 6
    Register indirect 5
    Register relative 9
    Based indexed
    (BP)+(DI) or (BX)+(SI) 7
    (BP)+(SI) or (BX)+(DI) 8
    Based indexed relative
    (BP)+(DI)+DISP or 11
    (BX)+(SI)+DISP
    (BP)+(SI)+DISP or 12
    (BX)+(DI)+DISP

    Yu-cheng Liu and Glenn A. Gibson, Microcomputer Systems: The 8086/8088 Family
    Architecture, Programming, and Design, Second Edition, Appendix A, Prentice-Hall
    (1986)

    You might also like