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Introduction To DSP Processors

This document discusses digital signal processors (DSPs). It explains that DSPs are optimized for common signal processing algorithms like convolution and filtering that involve array operations and multiplication/accumulation. DSPs have features like multiple registers, buffers, and pointers that allow fast arithmetic on multiple data streams. A key component is the multiplier-accumulator unit that can perform a multiply-accumulate operation in one clock cycle. DSPs also use specialized memory access schemes and bus structures compared to general-purpose processors in order to more efficiently handle their signal processing workloads.

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92 views9 pages

Introduction To DSP Processors

This document discusses digital signal processors (DSPs). It explains that DSPs are optimized for common signal processing algorithms like convolution and filtering that involve array operations and multiplication/accumulation. DSPs have features like multiple registers, buffers, and pointers that allow fast arithmetic on multiple data streams. A key component is the multiplier-accumulator unit that can perform a multiply-accumulate operation in one clock cycle. DSPs also use specialized memory access schemes and bus structures compared to general-purpose processors in order to more efficiently handle their signal processing workloads.

Uploaded by

guptalagishetty
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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8.

INTRODUCTION TO DSP PROCESSORS


PROGRAMMABLE DSPs
1. Various algorithms like convolution, fft, filtering,
correlation etc…
2. Algorithms works on common things like
a. Processing on arrays
b. Major operations like multiply and accumulate
c. Linear and Circular shifting of arrays
3. General purpose processors vs DSPs
Features of DSP Processors
1. Multiple Registers
2. Multiple operand fetch capacity
3. Circular buffers
4. Fast manipulation of multiplications and accumulation
5. Multiple pointers
6. Multi processing ability
7. On chip memory
8. Interrupt structure and Timers
Multiplier and Accumulator Unit(MAC)
1. Dedicated hardware unit
2. Complete MAC operation is executed in one
clock cycle
3. In Texas DSP processor 320C5X output stores in product
register. The
product register contents are added accumulator register
ACC in ALU
4. Special instruction in DSP processors like MACD(multiply
accumulate with data shift)
Modified Bus Structures and Memory Access
schemes in DSPs
MACD instruction execution requires four clock
cycles with conventional architecture(Von- Neumann)
a. Fetch MACD instruction from program memory
b. Fetch one of the operands from program memory
c. Fetch the second operand from data memory
d. Data memory write
Von- Neumann Architecture
Not suitable for DSP Processors
a. All general purpose processors have this
architecture
b. Shares same memory for program and data
c. Performs fetch, decode and execute operations
sequentially
d. Speed can be increased by pipe lining
e. Contains common interval address and same bus
structure for both data/instructions read/write
Harvard Architecture
Harvard Architecture
1. Separate on chip memories for data and
programs
2. Separate address and data buses for data and programs
3. Speed of execution is high
4. Simultaneous fetching of instruction code and
operands
5. Fetch, decode and execution operations done parallely
Modified Harvard Architecture

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