Scribd
Upload
76 views

Entity Bit4

This document describes a 4-bit ALU entity with ports for two 4-bit inputs (A and B), a 3-bit selection input (S), a 4-bit output (Y) and a 3-bit flags output (FLAG). The entity instantiates components for 4-bit addition, subtraction, AND, OR, XOR, complement, increment and decrement operations. It uses a case statement on the selection input to determine which operation is performed and outputs the result on ports Y and FLAG.

Uploaded by

Nirjhar Ghosh
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
76 views

Entity Bit4

This document describes a 4-bit ALU entity with ports for two 4-bit inputs (A and B), a 3-bit selection input (S), a 4-bit output (Y) and a 3-bit flags output (FLAG). The entity instantiates components for 4-bit addition, subtraction, AND, OR, XOR, complement, increment and decrement operations. It uses a case statement on the selection input to determine which operation is performed and outputs the result on ports Y and FLAG.

Uploaded by

Nirjhar Ghosh
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

entity bit4_alu is

Port ( A : in std_logic_vector(3 downto 0);

B : in std_logic_vector(3 downto 0);

S : in std_logic_vector(2 downto 0);

Y : out std_logic_vector(3 downto 0);

FLAG : out std_logic_vector(2 downto 0));

end bit4_alu;

architecture Behavioral of bit4_alu is

component bit4_add

port(a,b:in std_logic_vector(3 downto 0);

s:out std_logic_vector(3 downto 0);

fr:out std_logic_vector(2 downto 0));

end component;

component bit4_sub

port(a,b:in std_logic_vector(3 downto 0);

d:out std_logic_vector(3 downto 0);

fr:out std_logic_vector(2 downto 0));

end component;

component bit4_and

port(a,b:in std_logic_vector(3 downto 0);

m:out std_logic_vector(3 downto 0);

fr:out std_logic_vector(2 downto 0));

end component;

component bit4_or

port(a,b:in std_logic_vector(3 downto 0);


n:out std_logic_vector(3 downto 0);

fr:out std_logic_vector(2 downto 0));

end component;

component bit4_xor

port(a,b:in std_logic_vector(3 downto 0);

r:out std_logic_vector(3 downto 0);

fr:out std_logic_vector(2 downto 0));

end component;

component bit4_complement

port(a:in std_logic_vector(3 downto 0);

q:out std_logic_vector(3 downto 0);

fr:out std_logic_vector(2 downto 0));

end component;

component bit4_increment

port(a:in std_logic_vector(3 downto 0);

k:out std_logic_vector(3 downto 0);

fr:out std_logic_vector(2 downto 0));

end component;

component bit4_decrement

port(a:in std_logic_vector(3 downto 0);

l:out std_logic_vector(3 downto 0);

fr:out std_logic_vector(2 downto 0));

end component;

signal g1:std_logic_vector(3 downto 0);

signal j1:std_logic_vector(2 downto 0);

signal g2:std_logic_vector(3 downto 0);

signal j2:std_logic_vector(2 downto 0);


signal g3:std_logic_vector(3 downto 0);

signal j3:std_logic_vector(2 downto 0);

signal g4:std_logic_vector(3 downto 0);

signal j4:std_logic_vector(2 downto 0);

signal g5:std_logic_vector(3 downto 0);

signal j5:std_logic_vector(2 downto 0);

signal g6:std_logic_vector(3 downto 0);

signal j6:std_logic_vector(2 downto 0);

signal g7:std_logic_vector(3 downto 0);

signal j7:std_logic_vector(2 downto 0);

signal g8:std_logic_vector(3 downto 0);

signal j8:std_logic_vector(2 downto 0);

begin

add1:bit4_add port map(A,B,g1,j1);

sub1:bit4_sub port map(A,B,g2,j2);

and1:bit4_and port map(A,B,g3,j3);

or1:bit4_or port map(A,B,g4,j4);

xor1:bit4_xor port map(A,B,g5,j5);

complement1:bit4_complement port map(A,g6,j6);

increment1:bit4_increment port map(A,g7,j7);

decrement1:bit4_decrement port map(A,g8,j8);

process(A,B,S)

begin

case S is
when "000" =>

Y<=g1;

FLAG<=j1;

when "001" =>

Y<=g2;

FLAG<=j2;

when "010" =>

Y<=g3;

FLAG<=j3;

when "011" =>

Y<=g4;

FLAG<=j4;

when "100" =>

Y<=g5;

FLAG<=j5;

when "101" =>

Y<=g6;

FLAG<=j6;

when "110" =>

Y<=g7;

FLAG<=j7;

when others =>

Y<=g8;

FLAG<=j8;

end case;

end process;
end Behavioral;

You might also like