Analog to Digital Conversion

ADC Essentials
A/D Conversion Techniques
Interfacing the ADC to the IBM PC
DAS (Data Acquisition Systems)
How to select and use an ADC
A low cost DAS for the IBM PC

1
 Why ADC ?

Digital Signal Processing is more popular
 Easy to implement, modify, …
 Low cost

Data from real world are typically Analog

Needs conversion system
 from raw measurements to digital data
 Consists of
 Amplifier, Filters
 Sample and Hold Circuit, Multiplexer
 ADC

Chap 0 2
 
n bits ADC
ADC Essentials  Number of discrete output
level : 2n
 Quantum

Basic I/O Relationship  LSB size
 ADC is Rationing  Q = LSB = FS / 2n
System 
Quantization Error
 1/2 LSB
 x = Analog input /
 Reduced by increasing n
Reference
• Fraction: 0 ~ 1

Chap 0 3
 Converter Errors

Integral Linearity Error

Offset Error


Differential Linearity Error

Gain Error


Nonlinear Error

Can be eliminated by initial
adjustments
 Hard to remove

Chap 0 4
 Terminologies

Converter Resolution 
Conversion Time
 The smallest change  Required time (tc) before
required in the analog the converter can provide
input of an ADC to valid output data
change its output code by 
Converter Throughput Rate
one level  The number of times the

Converter Accuracy input signal can be
 The difference between sampled maintaining full
the actual input voltage accuracy
and the full-scale  Inverse of the total time
weighted equivalent of the required for one
binary output code successful conversion
 Maximum sum of all  Inverse of Conversion
converter errors including time if No S/H(Sample and
quantization error Hold) circuit is used

Chap 0 5
 More on Conversion Time

Example
 8-bit ADC

Input voltage change  Conversion Time: 100sec
during the conversion  Sinusoidal input

process introduces an 

undesirable uncertainty
 Rate A sin(2
 change
vi of ft )

Full conversion accuracy is dvi
realized only if this   fA cos(2
Let FS=22A ft )  2 fA
dt
uncertainty is kept low
below the converter’s
2A
resolution 2 fA 
2 n tc
 Rate of Change x tc  Limited ftoLow1frequency
 of 12.4
 resolution Hz 2n  t
12.4 Hz
dV FS c
 ( ) max  n  Few Applications
dt 2 tc

Chap 0 6
 S/H increase Performance
S/H (Sample and Hold)
Example


 Analog circuits that
quickly samples the
 20 nsec aperture time
1
input signal on 
f   62.17 KHz
command and then 2  ta
n

holds it relatively  Reasonably good for

constant while the ADC 100sec converter
performs conversion
 Aperture time (ta)
 Time delay occurs in S/H
circuits between the time the
hold command is received and
the instant the actual transition
to the hold mode takes place
 Typically, few nsec

Chap 0 7
 Analog Input Signal

Typically, Differential or Single- 
Matching input signal
ended input signal of a single
polarity and input range
 Typical Input Range  Prescaling input signal
 0 ~ 10V and 0 ~ 5V using OP Amp
 If Actual input signal  In a final stage of
does not span Full Input preconditioning circuit
range  By proportionally
 Some of the converter output scaling down the
code never used reference signal
 Waste of converter dynamic
range
 If reference signal is
 Greater relative effects of the adjustable
converter errors on output

Chap 0 8
 Converting bipolar to unipolar

Input signal is scaled and an
offset is added

Using unipolar converter when
input signal is bipolar Add
 Scaling down the input offset
scaled
 Adding an offset

Bipolar Converter
 If polarity information in
output is desired
 Bipolar input range
 Typically, 0 ~ 5V
 Bipolar Output
 2’s Complement
 Offset Binary
 Sign Magnitude
 …

Chap 0 9
 Outputs and Analog Reference Signal

I/O of typical ADC

Errors in reference signal
 From
 Initial Adjustment
 Drift with time and
temperature
 Cause

ADC output  Gain error in Transfer
characteristics
 Number of bits
 8 and 12 bits are typical

To realize full accuracy of
 10, 14, 16 bits also available
ADC
 Typically natural binary  Precise and stable
 BCD (3½ BCD) reference is crucial
• For digital panel meter, and  Typically, precision IC
digital multimeter
voltage reference is used
• 5ppm/C ~ 100ppm/C

Chap 0 10
 Control Signals

HBE / LBE

Start  From CPU
 From CPU  To read Output word
 Initiate the conversion after EOC
process  HBE
• High Byte Enable

BUSY / EOC
 LBE
 To CPU • Low Byte Enable
 Conversion is in
progress
 0=Busy: In progress
 1=EOC: End of
Conversion

Chap 0 11
 A/D Conversion Techniques

Counter or Tracking ADC

Successive Approximation ADC
 Most Commonly Used

Dual Slop Integrating ADC

Voltage to Frequency ADC

Parallel or Flash ADC
 Fast Conversion

Software Implementation

Shaft Encoder

Chap 0 12
 Counter Type ADC 
Operation

Block diagram  Reset and Start Counter
 DAC convert Digital output of
Counter to Analog signal
 Compare Analog input and
Output of DAC
 Vi < VDAC
• Continue counting
 Vi = VDAC
• Stop counting
 Digital Output = Output of
Counter

Waveform 
Disadvantage
 Conversion time is varied
 2n Clock Period for Full
Scale input

Chap 0 13
 Tracking Type ADC

Tracking or Servo 
Can be used as S/H circuit
 By stopping desired
Type
instant
 Using Up/Down
 Digital Output
Counter to track input
 Long Hold Time
signal continuously
 For slow varying input

Disabling UP (Down)
control, Converter generate
 Minimum (Maximum)
value reached by input
signal over a given period

Chap 0 14
 Successive Approximation ADC

Most Commonly used in 
Block Diagram
medium to high speed
Converters

Based on approximating
the input signal with binary
code and then
successively revising this
approximation until best
approximation is achieved

SAR(Successive
Approximation Register)
holds the current binary
value

Chap 0 15
 Successive Approximation ADC

Circuit waveform 
Conversion Time
 n clock for n-bit ADC
 Fixed conversion time

Serial Output is easily
generated
 Bit decision are made
in serial order

Logic Flow

Chap 0 16
 Dual Slope Integrating ADC

Operation

Excellent Noise Rejection
T1
 Integrate 0 vi dt  High frequency noise
t2 cancelled out by integration
 Reset and integrate
0 Vr dt  Proper T1 eliminates line
 Thus T1vi ( AVG )  t2Vr
t noise
 
vi ( AVG )  Vr 2  Easy to obtain good
T1

Applications resolution
 DPM(Digital Panel Meter),

Low Speed
DMM(Digital Multimeter),
 If T1 = 60Hz, converter
…
throughput rate < 30
samples/s

Chap 0 17
 Voltage to Frequency ADC

VFC (Voltage to Frequency 
Low Speed
Converter) 
Good Noise Immunity
 Convert analog input 
High resolution
voltage to train of pulses  For slow varying signal

Counter
 Generates Digital output
 With long conversion
time
by counting pulses over a
fixed interval of time

Applicable to remote data
sensing in noisy
environments
 Digital transmission
over a long distance

Chap 0 18
 Parallel or Flash ADC

Very High speed 
Homework #5-1
conversion  어떻게 동시에 비교가
 Up to 100MHz for 8 bit
되는지를 설명하라 .
resolution
 Video, Radar, Digital
Oscilloscope

Single Step Conversion
 2n –1 comparator
 Precision Resistive
Network
 Encoder

Resolution is limited
 Large number of
comparator in IC

Chap 0 19
 Software Implementation

Implementation with 
Limited Practical Use
software using  Availability of Good
microprocessor performance with very
 Counting reasonable Cost
 Shifting
 Inverting
 Code Conversion
 …

Chap 0 20
 Binary Encoder
Shaft Encoder


 Misalignment of mechanism

Elctromechanical ADC causes large error
 Convert shaft angle to digital  Ex: 011  111 (180deg)
output

Encoding
 Optical or Magnetic Sensor

Applications
 Machine tools, Industrial
robotics, Numerical control 
Gray Encoder
 Misalignment causes 1 LSB
error

Chap 0 21
 Interfacing the ADC to the IBM PC

Interface Operations  Using CPU Interrupt
 Most-recent-data Scheme  CPU initiate conversion
 At end of conversion it every time it needs new
updates an output FIFO data
 Automatically start new
 CPU can proceed to do
conversion other thing
 CPU read FIFO to
 ADC interrupt CPU when
acquire most recent data conversion is complete
 CPU goes to ISR
 Start-and-wait Scheme
 CPU initiate conversion
every time it needs new
data  See Chapter 3, For more
 CPU check EOC until information about 8259A
conversion is finished

Chap 0 22
 Interface Software

DMA (Direct Memory
Access)

Memory Mapped Transfers  CPU release system bus
 ADC is assigned in by the request of DMA
Memory Space  DMA controller carried out
 MRD, MWR signal data transfer by generating
the required addresses and
 MOV instruction control signals
 More complex decoding  The system bus control
logic reverts back to CPU when

I/O Mapped Transfers data transfer is finished
 ADC is in I/O Space

DMA is useful
 High Speed
 IOR, IOW signal
 High volume data transfer
 IN, OUT instruction
 Disk Drive interface
 More Simple decoding
logic

Chap 0 23
 Interface Hardware

Parallel Data Format 
Serial Data Format
 Three state output  Asynchronous Serial
buffer in ADC transmission to send
data over long distance
 To Interface ADC to a monitoring station
 CPU + Decoding logic  UART is commonly
• To generate Chip used
Select signal
• To generate Start
Signal

Interfacing 10 or 12 bit
• To Check EOC
ADC
signal  Transfer data in chunks
of 8 bits one after
another

Chap 0 24
 DAS (Data Acquisition System)

DAS performs the 
Applications
complete function of  Simple monitoring of a
converting the raw single analog variable
outputs from one or  Control and Monitoring
more sensors into of hundreds of
equivalent digital parameters in a nuclear
signals usable for plant
further processing,
control, or displaying
applications

Chap 0 25
 Single Channel System

S/H (Sample and Hold)
 Reduce uncertainty error

Transducer
in the converted output
 Generate signal of low when input changes are
amplitude, mixed with fast compared to the
undesirable noise conversion time

Amplifier, Filters  In Multi-channel system

 Amplify  To hold a sample from

one channel while
 Remove noise multiplexer proceed to
 Linearize sample next one
 Simultaneous sampling
of two signal

Chap 0 26
 Sample and Hold Circuits

Care in selecting hold
capacitor Ch
 Low Value
 Reduces acquisition time
 Increase Droop
 High Value
 Minimize Droop
 Increase acquisition time
 Choose capacitor to get a
best acquisition time
while keeping the droop
per conversion below 1
LSB

Chap 0 27
 Commercially Available S/H

Chap 0 28
 Multi-channel System

Analog multiplexer 
Local ADCs and digital
and a ADC multiplexer
 Low cost  Higher sampling rate

Chap 0 29
 How to select and use an ADC

Range of commercially 
Guidelines for using
available ADCs ADCs
 Use the full input range
of the ADC
 Use a good source of
reference signal
 Look out for fast input
signal changes
 Keep analog and digital
grounds separate
 Minimize interference
and loading problem

Chap 0 30
 Commercially available monolithic ADCs

Chap 0 31
 Commercially available hybrid ADCs

Chap 0 32
 A low cost DAS for the IBM PC

Generating clock
 For starting ADC

Multi-channel system
conversion
 Less than $100  For causing interrupt
 ADC0816 from  Make a pulse stream
National from TCLK with short
Semiconductor pulses of duration = ½ x
 Constant, repetitive BCLK/4
rate  TCLK from 8253
Timer/Counter
 1000 samples/s
• Wide pulse

Chap 0 33
 ADC circuit for
PC prototype
board
SCSLCT
(Start Conversion SeLeCT)
: Latched trough port 30CH
SCSLCT = H
Selection of 30AH (/E10)
start conversion
SCSLCT = L
TCLK’ start conversion

INTSLCT
(INTerrupt SeLeCT)
: Latched trough port 30CH
INTSLCT = H
EOC cause IRQ2
INTSLCT = L
No Interrupt
CPU read Status register
(Port 309H) to check EOC

Chap 0 34
 Status Register

For polling TCLK and
EOC signal

Port 309H (/E9)

Polling of EOC results
in a low level after the
data from ADC have
been read

Chap 0 35
 Throughput rate calculation

4.77MHz / 8
= 596KHz

Chap 0 36
 Accuracy Calculation

Better than 1% accuracy is ensured

Actual accuracy with smooth input signal at room
temperature will be better than 0.5%

Chap 0 37
 Basic Program for Controlling ADC

Sampling rate < 200 samples/s

Because OUT and IN
instruction in Basic takes 5ms

Chap 0 38
 C Programming for Controlling ADC


Sampling from ADC channel 1 at 5ms interval and sending each sampled data
point to the DAC
Chap 0 39
 Homework #5-2

Prototype board 의 회로 도를 참고하여 앞의
C program 이 수행되는 과정을 해석하라
 예를 들면 Outp(CNTRL,5) 가 수행되면 회로도
에서 어떤 신호가 구동되는지 등… .

Chap 0 40