Acronics Systems, Inc.

http://www.acronics.com
683 River Oaks Parkway- San Jose, CA 95134 - USA

PCB GUIDLINES
1. CREATING THE LIBRARY FOR THE BOARD (BUILDING THE
FOOTPRINTS)
1.1. CONCEPT OF FOOTPRINTS
a. Footprints (Package Symbol, Footprint, Parts…) is package imitate ICs (or chips, connector,
sockets…) use for a PCB (Print Circuit Board).
b. Footprint includes Padstack, Pin Number, Assembly Top, Silkscreen Top and Bottom, Place-
Bound-Top, Place-Bound-Bottom, No-Probe-Top, No-Probe-Bottom, Dimension and Text
convention, Fiducial, Reference Designator, Keep Out.
c. To create a Footprints, we need datasheet of IC and base on some standard convention.
d. We can get parts for the board from (in order):
+ Customer (Include the names of all of the customers' projects).
+ Acronics LIB.
+ Search datasheets from internet (Make sure P/N are correct).
e. When building library, we have to do these things following:
- Find out from netlist or BOM from the customer to build the Footprints and device.
- Parts can be from:
+ Customer (Include the names of all of the customers' projects).
+ Acronics LIB.
+ Search datasheets from internet.
+ Do not use Temp parts on the board. (Difficult to manage).
- Make EXCEL files (Bom file) ( to know which parts are correct or temporary)
- Make Footprint board: "B" size (11"x17") and place parts for Customer to check (if need).
1.2. BUILDING FOOTPRINTS
Look datasheet carefully to determine dimension of Padstacks, Pitch, Dimension between pins,
Pin order.
1. Set up Drawing Units: Mils or Milimeters.
Accuracy for Mils is 3 (decimal places) and Millimeter is 4 (decimal places)
If unit used in datasheet is milimeter, you must set User Units as milimeter.
If there are 2 units (mil and milimeter) used in datasheet, choose unit that is more accurate.

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http://www.acronics.com
683 River Oaks Parkway- San Jose, CA 95134 - USA

2. Run gs command (Skill: gsnew.il) to set color for necessary subclasses and set origin (0,0)
co-ordinate at middle of Working Window
3. Create padstack:
- Run cps command (skill: create_padstack4.il) to build necessary padstack automatically or
manually by Pad Designer software. In padstack has Flash, we can create by Allegro.exe or use
skill Create_Thermal_Flash.il (command: cts).
- Padstack are created base on dimension of datasheet and our convention about padstacks. (See
“CREATING_PARTS_02Mar05.doc” to more clearly).
- If beside drawing, there is a note such as “Recommended PCB Layout”, “Recommended Hole
Layout”, “Land Pattern Recommendation” or similar in datasheet, you must use types of padstack
recommended and build Footprint based on dimension in datasheet.
4. Add pins into Package Footprint:
- Use Allegro.exe: Select Package Footprint. The Pakage Footprint is *.DRA file.
- Layout > Pin. After that, fill parameters base on the datasheet.
**Note: For mechanical pins (pins are not connected) choose mechanical
Option. These pins will not have pin name (pin number).
For connect pins that are not used, do not fill Pin # text box. There will be a
Triangle shape at location of pin number.
5. Add fiducial (if needed), add Route_Keep_Out for fiducial. Fiducial is mechanical pin.
6. Drawing Package Geometry/Assembly_Top: follow the company’s rule.
**Note: Only use Line to draw Assembly, do not use shape.
Remember to add circle to indicating pin 1 inside body.
Add shape (Triangle) indicating the front of part if needed.
Add Mark of polarization Capacitor, Diode, Led.
7. Drawing Package Geometry/ Silkscreen_Top:
- Package Geometry/ Silkscreen_Top include Line to model Body of part, shape indicating pin 1
and text indicating pin number.
- You can copy Assembly_Top Line then change to Package Geometry/Silkscreen Top
- Add shape indicating pin1 on Package Geometry/ Silkscreen_Top. The shape must be large
enough, symmetric, outside body.

- Add text indicating number on Package Geometry/ Silkscreen_Top (Text Block 2): You can do
this step by the way: Copy Text from Package Geometry/ Pin Number, change these Text to
Package Geometry/ Silkscreen_Top with Text Bock 2. (You can add text by use the skill
bgatext.il to add text for BGA. Command: bga ).
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http://www.acronics.com
683 River Oaks Parkway- San Jose, CA 95134 - USA

**Note: You only need some texts indicating pin numbers at the conners. If the part have
many pins, you should add text for each 10 pins. For example, the part has 60 pins, you
will add text indicating pin 10, 20, 30, 40, 50 and 60.
For parts have pins arrange in matrix with rows and columns (BGA…), you should
mark pin number by row name and column name.
Only use Line to draw Assembly, do not use shape.
Add shape (Triangle) indicating the front of part if needed.
Add Mark of polarization Capacitor, Diode, Led.
Add line indicate PCB Edge for Connectors that will be placed near PCB edges. Write
note “PCB Edge” next to this line and outside the silkscreen.
- Cut part of Line on Silkscreen_Top cross pin.
8. Add text indicate pin number on Package Geometry/Silkscreen_Bottom (only for Thu pins
Footprints and BGA): Text Block 2: Do similar above. The text must be mirrored.
9. Drawing Place_Bound_Top:
Draw a shape on temporary subclass (for example Assembly Bottom) surrounds pin and
silkscreen. To expand the shape: Edit => Z copy shape, choose Package_Geometry\
Place_Bound_Top, choose expand options, fill in Offset the size you want to expand.
** Notes: Do not draw Place_Bound_Top too large. With connector, BGA: have Place
Bound Top 100 mils larger Body part. With IC: have Place Bound Top 25 mils larger
Body part. With dicrete Footprints: have Place Bound Top larger Body 12-15mil.
When modified Place_Bound_Top, remember to add com height for Footprint.
10. Drawing Manufacutre \ No Probe_Top:
Do similar Place_Bound_Top.
11. Delete shape on temporary subclass .
12. Run gs command to fill related information such as Comp Height, Creator or Checker or
Modifier Name, Part Number, Manufacture, Spec… then click Gensym.
13. Add dimension on Package_Geometry \Comp_Dim Subclass (Not on Board_Geometry \
Dimension ). *Note: Dimension should follow datasheet and clearly to check easily.

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http://www.acronics.com
683 River Oaks Parkway- San Jose, CA 95134 - USA

1.3. WHEN BUILDING SYBOLS, PLEASE PAY ATTENTION FOLLOWING:

1. We have to make Excel file to list parts for the board ) ( to know which parts are correct
or temporary).
2. Pin order are wrong, because we didn't read datasheet carefully: Ditermine Pin Order
Top and Bottom in the Datasheet. We have to follow Pin Order on Top.
3. We have to differentiate drill hole and finished hole (use the finished hole to design).
4. Silkscreen are wrong and not detail.
- For example: With connector, we often forgot made two triangle shapes to specify the front
side.
- With some components, the silk screen was drew not detail. This thing made poeple don't know
about sides of components. Special, with Diodes, Led, if the silkscreen was drawn not detail,
people will don't know pin order and don't differentiate Anode pin and Cathode pin, so we have to
notes the polaris for Diodes, led…carefully.
5. Missing fiducials.
6. When design BGA and parts have unit: milimiters, have to use unit: milimeters.
7. When build the Footprints the dimension should be shown the same as in the
spec_sheet. That way will be easy for people to check the Footprints.
9. If the datasheets were downloaded from Internet which missing the information (Infor
about Pin-Order, padstack…), should find the other and ask for help from co-worker or
instructions.
10. Have to check the Thru Hole padstacks carefully (Thru-Hole Plated and Non-plated),
Example: Check the Flash, check the holes…
11. Have to check the Pole of Capacitor and Diode, LEDs.
12. Have to care Pin order Top and Bottom side.
13. If parts came from Customer’s LIB., we need to check again to make sure they are
correct and so that we can make the parts better.
14. The place bound Top follow DFA type.
15. The spacing between sodermasks do not less than 2.5 mils. If spacing between to Pin is
too small, the Soldermask should be equal the Pads or larger 1 mil.
16. When build part, please see schematic to build right part (Kind of parts, Pin order….).
17. When use the polar capacitors, pay attention Tantalum caps and Aluminum
Electrolytic Capacitor.
18. Should use the netlist file to find the Package Type (Footprint)(File *.NET, file:
pstxprt.dat).

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683 River Oaks Parkway- San Jose, CA 95134 - USA

19. Do not delete Pin number if the schematic miss pin number. We add pin connect but
no assign pin number for this pin. It will be have triangle pin.
20. Please check the schematic when check parts to make sure Pin order, P/N…
21. Hot plug connector:

Short pin: Power.

Medium pin: Signal. In order to distinguish 3 net types easily.
Long pin: Gnd.
Please build it carefully.

22. There are some footprints need pay attention following:

- For the SOT23: Have to base on datasheet to determine pin order. Because
pin order in schematic can be wrong.
Example:

Datasheet Schematic

3 1
D D
1 G 2 G
S S
2 3

- For the DPAK: Have to check body center C. It is determined as follows:

X

Y
C
Y/4

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http://www.acronics.com
683 River Oaks Parkway- San Jose, CA 95134 - USA

- For the CAPACITOR and DIODE, LED: Have to check the Pole. (Start from
1206 to bigger Footprint ).

23. Bom file: Don’t miss Part number and Manufacture informations. If missing one of
two informations, main worker need to ask customer.
24. Footprint board: Need to check body centers of footprints. (Please turn on body
centers of all footprints in footprint board to look over them quickly).
25. Edge connector have 2 pin rows (top and bottom) :
1. Need to cover all pins with solder mask shape (Package geometry/solder
mask top & bottom) as it will be drawn below.
2. Padstacks have no paste mask. Because there is no assembly step at here.
3. Need to draw board outline in Footprint file. When place Footprint in
board, this board outline will be overlap board outline of board.
4. Remember chamfering for board outline as follows (base on datasheet to
determine X, as usual X = 20 mils ).

5. Remember adding information about board thickness in Fab note.

Example:

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683 River Oaks Parkway- San Jose, CA 95134 - USA

26. For Shroud Header connecter should draw detail silkscreen to do placement and do
assembly easier.
27. For edge connector special need cut board outline : We need to add board outline in
footprint and need drill at corner (you can reference to Sibeam_chimchim or
Sibeam_MIXED_Signal_Test board ).

28. For IC have many pin consecutive same as net name GND or Power: If the board
cover shape ground or Power on top or bottom cover these pins. Please thermal these pin
to void overflow lead.
29. For the footprints which have large PADs (center pad): Please separate pastemask into
smaller shape.
30. Please build part with rotation 00 degree. Please reference to “Package-Rotation.doc”.
(Hw_server\HARDWARE LIBRARY\TECHNICAL
DOCUMENT\Creating_Part_Document_DN)

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 Acronics Systems, Inc.
http://www.acronics.com
683 River Oaks Parkway- San Jose, CA 95134 - USA

1.4. THESE ARE THE SKILLS FOR THIS STEP:

1. Gsnew.il ( Command : gs) : Set up format information for building parts following
Acronics conventions.
2. Create_Flash.il (Command : cts): It looks like Add>Flash in Allegro, but more powerful,
It can create RECTANGLE and OBLONG Flash.
3. Create_padstack32.il (Command : cps): No need to remember all rule from Acronics
Standard of padstack, It will help you filling the name of padstack to the form and auto create it
(including its flash)
4. bgatext.il (Command : bga): Help to creat text indicate pin numbers of BGA easier.
5. CheckPadstack2.il (Command : cpad): Help to check the padstack base on our
convenions by report.

90% PROBLEM OF THE BOARD COME FROM FOOTPRINTS.

PLEASE BUILD AND CHECK THE FOOTPRINTS VERY CAREFULLY,
ONE PERSON BUILD, SHOULD HAVE OTHER PEOPLE CHECK.
*********************************************

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 Acronics Systems, Inc.
http://www.acronics.com
683 River Oaks Parkway- San Jose, CA 95134 - USA

2. PLACEMENT
2.1. MADE THE BOARD OUTLINE:
Board outline contains dimension of a board, location of mechanical components (Mounting
holes, connectors…). Some cases, it also contains location of main components. Made the board
outline by the way:
a .Draw board outline: Use Line to draw board outline. Add dimension for the board base on
documents from customer. Board outline line width = 1 mils.
b. Use DXF file to made the board outline: DXF file is a AutoCad file from customer, it
contains the board outline dimensions, location of mechanical components (Mounting holes,
connectors…). We can import this file into Allegro, then base on this file to create board outline.
We have to care about unit and ratio of the drawing before importing DXF into the board(May be
the dimension is not correct when import into Allegro, with this case, we have to measure
dimension in Allegro, compare with real dimension, then we get Ratio to scale DXF file to
correct).

**
When creating the board outline, please pay attention some things
following:
- Should use MASTER BOARD to save the time.
- Set up Route_KeepIn, Package_KeepIn
- Also set up route_Keep_out, Package_Keep_out or via keep out if needed.
- Add fiducials . We must put fiducial far away board outline minimum 200 mils and. Don’t
place 2 fiducials of board in a straight line.
- Draw dimension and indicate mechanical location clearly to help to place parts easier.
2.2. IMPORT NETLIST INTO THE BOARD :
a. Netlist file:
- Netlist is a file which is exported from Schematic (Logic Design). It
constains Package Footprints, list of nets, and property of nets (If the Schematic was added
property).
- Net list has difference forms:
** NETLIST FROM ORCAD:
+ If we use the Orcad Version 9.2: We have the netlist file: *.NET.
+ If we use the Orcad Version 10.5 (Include in Allegro15.5) or later, we have netlist include 3 file
“*.DAT”: (pstxprt.dat, pstchip.dat, pstxnet.dat). 3 file “*.DAT” must has standard name
(pstxprt.dat, pstchip.dat, pstxnet.dat). If we use difference name, we can not import into Allegro.

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683 River Oaks Parkway- San Jose, CA 95134 - USA

** We also have Netlist from Concept, View Draw….: *.TEL file or Protel file.
b. Importing netlist: We need DEVICE file when importing netlist for file *.NET, *.TEL. We
can create Device file from Package Symbol files. A device file contains information of one
Footprint (Pin number, function…).
c. When importing netlist, please pay attention some things following:
- If netlist is PROTEL file, we need to convert to ALLEGRO file: Use Program
ConvertFromPROTELtoALLEGRO.
- Netlist sometimes has errors because:
+ Missing PCB Footprint name.
+ OrCAD symbol has problems.
+ PCB Footprint name has illegal character.
We need to fix netlist or schematic before importing.
2.3. GOT PARTS FROM BUFFER AND PLACE PARTS PAGE BY PAGE BASE ON
THE SCHEMATIC:
a. Got the parts from buffer:
- After importing the netlist, we can got part from buffer to place them into the board. When got
the part, we need:
+ File *.PSM : The file are created from Pakage Symbol file (*.DRA).
+ File *.FSM: The file are created from Flash Symbol file (*.DRA).
+ All the padstacks (*.PAD).
b. Place the parts page by page base on the schematic:
We should place follow each group of main IC in each page, then combine the difference parts of
this IC in the other pages to one before start place parts. By the way, we can overview the quality of part
and can estimate the room for each IC group on the board.
2.4. PLACE PARTS INTO THE BOARD:
a. Place symbols into the board:
- Main worker place main ICs on the board and draw room to place small comps of one IC. Then
assign jobs to other person follow each IC (include pages that contain this IC).
When place parts into the board, recommend place follow the steps following:
The first, PAY ATTENTION:
- Set grid 25 for Big components and Set grid 5 for Small
components. (Skill SetGrid.il: Command: g x (x: value of grid, example: 5, 25…))
- The clearance around BGA minimum 100mils.

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683 River Oaks Parkway- San Jose, CA 95134 - USA

- The spacing between SMD and Thru hole on bottom is 100mil

minimum. (Should be set constraint first).

- Turn Place Bound Top and Bottom, silkcreen top and bottom,
then place components so that Place Bound do not overlap together.
1. - Turn on the DRC (THIS IS IMPORTANT).
- Turn rats of Diff. pairs.
- Turn rats of Clock nets.
- Turn rats of Pwr nets.
- Hightlight PWR nets.
2. Place parts which have mechanical locations first (Connectors, Header, sockets….).
3. Place main components of each page of the schematic. Most of them are BGA, IC,
Connectors…
4. Place small components around main components in each page of schematic close to the main
components.
When place small components, recommend place follow the order following:
- Place decoupling capacitors: Decoupling capacitors should be placed
close to Power Pins, each pin should have one cap. When place decoupling capacitors, should
highlight PWR nets and GND nets to place them correctly (Pin PWR of caps close to Pin PWR
of IC).
- Place terminal resistor: The terminal resistors include serial resistor
and parallel resistor. Serial resistors should be placed close to source IC, Parrallel resistors
should be placed close to destination IC. When place terminal resistors, turn rat nets and swap
resistors to route easier. When place terminal resistors connect diff-pair nets, we should hi-light
all net diff-pair to place exactly.
- Place rest components.
*** (Skill for this step: align_sym.il (Command : align_sym): Align symbols for placement
better).
5. The components in each page of the schematic should be placed close together.
6. Place components by the way so that we can route easiest: Turn rat nets to find the way to
place each components.
7. Pay attention to the similar group to can copy placement.
8. Pay attention about RF section and ANALOG sections: Need some special way to place
them.
9. Try put all SMD symbols among length of board far away edge board 200mils if possible.
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683 River Oaks Parkway- San Jose, CA 95134 - USA

2.5. WHEN PLACEMENT, PLEASE PAY ATTENTION FOLLOWING:

1. The Power Section, The Clock Section and The Analog Section should be placed close
together for each section. The Power section should be placed so that we can cut planes easiest.
In general, these sections will be placed at separate areas, and we limit run traces cross them.
2. When place Power section: Need pat attention for INPUT and OUTPUT of powers. Need
cut shapes and put many of vias at INPUT and OUTPUT to carry large current.
3. RF section need pay attention: There are some special way to place RF section.
4. The Analog section should be placed apart from the Digital section. And all the Digital
signals are not routed cross Analog section, and all the analog signals are not routed cross to
Digital section.
5. If the board need 100% testpoints, we should prepaid for test vias: Place the components
by the way so that we have room to put testvia. Testvia is via have Pad 35mils or 32 mils. We
often put testvia on Bottom side. We need to prepaid room for Testvia to put testvia do not
overlap No_Pro_Bottom.
6. Terminate resistor of diff pair should be close to the Diff-pair pins. And place them so that
we can put via for diff_pair.
7. Don’t place connectors (symbol thru) under SMT components.
8. With the board very tie, don't need to use the placebound to do the placement.
a./ Keep the component 100 mils away from the BGA.
b./ Keep the big components about 50 mils away from other components.
c./ Keep the discrete 20mils pad to pad to others.
9. With Resistor and Conductor connect 2 PWR, should place at the split planes.
10. The components of a page have to place close together.
2.6. THESE ARE THE SKILLS FOR THIS STEP:
1. Check_comp25.il (Command : check): Find some components not on 25 mil grid.
2. export_place3.il(Command : export place): This SKILL program was designed to export
placement of selected component or find the changed components between an old board and the
new one. Use it in some cases that will show its powerful funtions: Whenever you want to
export a group of selected components that had been done placement.There are 3 mode select:
select from list, loading list or select by cursor.we can do that easily.
3. align_sym.il (Command : align_sym): Align symbols for placement better.
************************************

3. SET CONSTRAINT FOR THE BOARD.

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683 River Oaks Parkway- San Jose, CA 95134 - USA

3.1. CONCEPT OF CONSTRAINT

Set constraint for a board is set rule between traces, vias, pin…When design the board, if we
violate the constraint, the board will appear errors (DRCs). We must clean up DRCs to match
the constraint for the board.
3.2. SET CONSTRAINT: Pay attention: Should use the Master Board to save time.
3.2.1. General Design Rule: General constraint have Spacing Rule and Physical Rule. These
are the basic rule: Please refer Master board for detail about basic constraint.
The basic constraint must based on the Stackup of the board.
3.2.2. Electrical Design Rule:
We often use Constraint Manager to set Electrical constraint. Electrical constraint include Diff-
pair, Relative Propagation Delay, Propagation Delay…New engineers will be trained this
constraint when they study designing board.
3.3. THESE ARE THE SKILLS FOR THIS STEP:
1. add_layer_New.il (Command: al) : Add layer for the board from a text file.
2. sch_property.il : Command :
- schedule: Set schedule nets.
- get rpropa: Getting RELATIVE_PROPAGATION_DELAY property nets.
- get propa: Getting PROPAGATION_DELAY property nets.
3. Set_Daisy_Chain.il (Command: sdc)
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683 River Oaks Parkway- San Jose, CA 95134 - USA

4. FANOUT THE BOARD:

4.1. FANOUT RULE
- Set grid: 5 and try to do spacing 50 mils via to via (center to center of the via).
- Do not put the vias far a way from the pad. Follow the constraint have been set.
- Prepare for test point if the board needs testpoint. If the board needs Testpoint, should turn on
the No_Probe_Bottom when fanout.
- Don’t make traces bigger than pad size.
- Do pin escape for BGA, even those pins are dummy net.
- Trace from SMD Pad should be 900.
- Person that do placement and fanout one section should be one person.
- Fanout Bottom first: Because we need pay attention for Testpoint. Fanout Power nets first and
decoupling caps: Because via of PWR nets need to near pins
4.2. THESE ARE THE SKILLS FOR THIS STEP:
1. Check_pin_escape.il (Command : cpe): Checks and zooms to the pins that
don't have via-escapes.
2. putting_via_bga.il ( Command : pvrun)
3. replace_via.il ( Command : rvrun)
4. via_grid.il (Command : grid) : Check via on grid 5 and spacing 50mils.

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683 River Oaks Parkway- San Jose, CA 95134 - USA

5. ROUTE THE BOARD:

5.1. RECOMMEND ROUTING: Please try to route off (no bubble) and use grid 5 (no grid
1 except inside bga): because by the way we will avoid the sliver errors in gerber file and the
board look better.
- Route critical nets first. Critical nets include Clock, Diff_pair, Bus…(Customer define).
Recommend route critical nets on the layer that adjust by GND planes.
- Route at areas where have dense ratnets, then route at areas have less net.
- Should be high light nets that have the same direction, we will try to route these nets in the same
layer.
- Just sketch out routing first (route with DRCs), after complete sketch out one group (or one
area), we will clean up DRCs and traces.
- The routing is short as possible.
- Two signals layer next to should be route trace not overlap together to avoid Tandem. Should
use one layer to route horizontal and one layer to route vertical (important).
- We must clean up traces after routing one group (or one place): Pay attention:
+ Long traces: We should look the board to find the long traces and clean up them for
better. We can re-route them if need. (Use Skill: DelBox.il (Command : db )).
+ Traces have wrong angle (Use skill check_cline3.il (Command : check cline ).
+ Clean up the trace middle between two Pins, two vias (Use skill middle_clinep_v2.il
(Command: midp ).
+ Trace come or from Pin have to from Center Pins.
+ Clean up Tandem and Parallelism.
+ Clean up trace cross split planes.
- Match the length for the board.
- Cut planes for the board.
5.2. WHEN ROUTING, PLEASE PAY ATTENTION FOLLOWING:
1. With big board do not route traces on the Top and Bottom layers much, try to only do fanout on
Top and Bottom layers. Some small boards you may need to use TOP and/or BOTTOM layers to
route.
2. If there is the room please make the spacing larger between traces. (Not for diff. pairs.)
3. Make all the planes 50 mils away from the GND_EARTH (Chasis_GND) even they are not
the same layer (if room available). ( Some customers don't care )
4. Try to void all the trace run across to plit-plane (Important).
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5. Never route ‘T’ juntion. (For Power net, we can do it, however limit).
6. Have to do Pin Escape for BGA even those PINs ARE DUMMY NETS.
7. When you fill the GND copper on top and bottom layers please set constraint
Shape to shape = 25 mils
Shape to line = 10 mils
Shape to via = 10 mils
Shape to pin = 10 mils.
8. The air gap between two shapes is 15 mils.
9. Remember that the neck of shape (between two pins) is not less than 4.5 mils.
10. In the power section: We should use the thick traces for all the signals.
(Engineers who working on this area should check schematic to make sure which nets need
have thick trace)
11. The filter powers : Use thick traces on both sides of components (Most of them are inductor).
(Don’t route trace under power inductors on Top and Bottom)
12. You need turn on all ratnets on the areas that you will route. Try find out the way to route , by
fan out all traces from this area out first, then connect them later. Try to route short traces. The last
one, when you complete routing, you will do matching length.
(Turn on “Electrical Constraint Spreadsheet” when routing to make sure it’s possible to do
matching length later)
13. When cut the small planes, try to do not cross any trace on adjust layers over the planes.
14. Have to care Tandem and Parallelism when start to route the board (Very important). Suggest:
Two next layers : Has one layer: Vertical, one layer: Horizontal.
(When routing parallel, main working engineer should let others know which layers they will
route their nets group, so others remain nets will have room to route at later phases)
15. Clock nets have spacing rule normally: 3 X trace width.
16. Set Longest Pinpair instead of setting: All Drivers/ All Receiver.
(Set Pin-Pin when nets have more than 2 pins)
17. Do not route Digital signals cross Analog section and also, do not route Analog signal cross
Digital section. In general, Analog signal has Analog GND, and this GND are cut so that we can
route Digital trace without cross it.
18. When do ECO board: When routing and add via : Bubble: Select OFF. So, when add via.
We keep old trace as much as we can when do ECO board.
- Try to avoid moving vias or traces from the old board.

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http://www.acronics.com
683 River Oaks Parkway- San Jose, CA 95134 - USA

- Do not remove change Artwork film from the customer's project except customer allow, just add
more layer to the artwork.
- Try to no move part. So We can re-use database for assembly.
19. With PWR 48V: away from other signals are 60 mils in TOP/BOTTOM layers. For internal
layers, 40 mils spacing to other signals. Shape to via (or trace to via) minimum 25mils.
20. Check and clean up Stubs.
21. Try to make shape good (Check spacing between shapes). Cover vias: The shape should cover
full vias (not a half).
22. The Power net: Route big traces or Shape, good for shape. We via escape for Power nets and
cut shape later (Do not route the power net with small trace).
23. Do not route the traces cross Split planes.
24. If the board need match length +/-10mils means set tolorance: 0:10mils or –5mil:5mil.
25. If the board have room, do not route two traces between 2 vias or 2 pins.
26. When cut planes, try to cover vias (Need check vias inside the gap of the planes).
27. When assigning routing jobs: Fist, check constraint to see: nets have Max vias, net have Ref
GND planes…so we can know the nets that route first or priority. We can create list of nets to can
manage easier.
28. When matching length: the horizontal layer should match length follow horizontal, vertical
should follow vertical…
29. When clean up inside bga, we will use special grid (g3937), we will set grid so that we can
clean up off and trace inside grid, it will be quickly. (When set grid inside bga, please set offset to ogigin
on via of bga, use skill “SetOffset.il”). we should create some script to set grid to use later.
5.3. THESE ARE THE SKILLS FOR THIS STEP:
1. check_cline3.il (Command : check cline ).
2. check_clines_under_cap.il (Command : check clines ).
3. check_loopnet.il (Command : cln ): This skills use check the loop traces.
4. DelBox.il (Command : db )
5. middle_clinep_v2.il (Command: midp ): Adjust traces to middle two pins or to vias.
6. net_report_v2.il (Command: report )
7. mot_find_stubs.il (Command : find_stubs)
8. tv_report1.il (Command : tv report)

6. MAKE ARTWORK.
The skill: Artwork_films_new.il (Command: art)

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 Acronics Systems, Inc.
http://www.acronics.com
683 River Oaks Parkway- San Jose, CA 95134 - USA

** For FAB film:

- The first: If the our board use old board to do then we must delete all information (ex: name other
company, logo, fab number, assembly number…) before we run artwork film.
- On the drill chart : you need to combine all drill have same size come to one figure.
- Need adjust Tolerance for Thru Padstack (Recommend old board).
- Need to read Fab_Notes carefully to find out the notes that do not match with current board and
modify them.
- Undefine Line Width for Silk: 6, the other 5.

7. CLEAN UP SILKSCREEN AND ASSEMBLY

7.1. CLEAN UP SILKSCREEN AND ASSEMBLY
For slikscreen: need turn pins and vias, soldermask (Pin/Soldermask, Package
Geometry/Soldermask, Board Geometry/Sodermask), then make sure the Texts not overlap silkscreen and
pads,smask. The Text can overlap Vias, but make sure we still read them ok.
For Assy drawing: if there are room you can move the Text inside the parts.
Use skill: silkassembly.il (Command: silk assembly) for this step.
- Line width: 6 For Silkscreen; 4 for Assembly.
- Text Block: 3 For RefDes. 2 for Silk.
- Text Mark for silk: Text Block 4, 4x4 Text Overlap togerther, Spacing 2 mil to Right for Top
and To left for Bottom.
7.2. CHECK SILKSCREEN AND ASSEMBLY
1. When QA silk: Just ask other someone to check:
- Turn on all Vias and Pins also the soldermask of pins, SM of board geometry and package
geometry that we want clean up (Top or Bottom)
- High light each the symbols. (they will high light all the symbols and REF DES), then you will
see the which symbols missing the REF DES or MIX between the symbols
2. With Text mark on Asy Bottom and Silk bottom (Board Geometry/ Asy bott or Silk bott), have to
mirror.
3. When clean up silksceen for the board which have Testpoint, please Turn on: Manufacturing/Pro
Bottom, and make sure no silkscreen overlap Test via, Test point and Fiducials.
5. - Check silk by Text pad (Use macro to check rotation and mirror of texts).
6. Check Pin 1: Hilight pin 1 all symbol on board and check indicate pin 1 must close to this pin.
7. Move silkscreen far away via as much as possible.
8. Need add more text for LED, connector base on schematic. This is important and make sure
the information add on board is true.
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 Acronics Systems, Inc.
http://www.acronics.com
683 River Oaks Parkway- San Jose, CA 95134 - USA

7.3. THESE ARE THE SKILLS FOR THIS STEP:

1. check_silk4.il (Command : checksilk)
2. silkassembly.il (Command: silk assembly).
3. silkex_import152.il (Command: export silk).

8. QA THE BOARD
REF the QA list.
The skills:
1. drc_walk.il (Command: drc walk)
2. checkpin3.il (Command: checkpin): Check via overlap to pin.
3. checkvia.il il (Command: checkvia): Check the dummy via…
4. check_loopnet.il (Command: cln)
5. checkcline3.il (Command: check cline)
6. check_clines_under_cap.il (Command : check clines ).
********************************************************

Updated 06Feb09 by SHT.

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