This document describes a VHDL module for a comparator ALU. The module takes in two 4-bit inputs A and B and outputs signals to indicate whether A equals B, A is greater than B, or A is less than B. It also takes in a 3-bit selection signal and outputs a 4-bit result based on the selected operation, which includes subtraction, addition, XOR, OR, and AND.
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Comparator ALU
This document describes a VHDL module for a comparator ALU. The module takes in two 4-bit inputs A and B and outputs signals to indicate whether A equals B, A is greater than B, or A is less than B. It also takes in a 3-bit selection signal and outputs a 4-bit result based on the selected operation, which includes subtraction, addition, XOR, OR, and AND.
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comparator_ALU.
vhd Thu Dec 30 23:14:08 2010
1 ---------------------------------------------------------------------------------- 2 -- Create Date: 21:51:50 12/30/2010 -- Module Name: comparator_ALU - Behavioral 3 ---------------------------------------------------------------------------------- 4 library IEEE; 5 use IEEE.STD_LOGIC_1164.ALL; 6 use ieee.std_logic_unsigned.all; 7 8 entity comparator_ALU is 9 Port ( A : in STD_LOGIC_VECTOR (3 downto 0); 10 B : in STD_LOGIC_VECTOR (3 downto 0); 11 AeqB : out STD_LOGIC; 12 AgtB : out STD_LOGIC; 13 AltB : out STD_LOGIC; 14 s : in STD_LOGIC_VECTOR (2 downto 0); 15 F : out STD_LOGIC_VECTOR (3 downto 0)); 16 end comparator_ALU; 17 18 architecture Behavioral of comparator_ALU is 19 begin 20 AeqB <= '1' when A = B else '0'; 21 AgtB <= '1' when A > B else '0'; 22 AltB <= '1' when A < B else '0'; 23 process (s,A,B) 24 begin 25 case s is 26 when "000" => F <= "0000"; 27 when "001" => F <= B - A; 28 when "010" => F <= A - B; 29 when "011" => F <= A + B; 30 when "100" => F <= A xor B; 31 when "101" => F <= A or B; 32 when "110" => F <= A and B; 33 when others => F <= "1111"; 34 end case; 35 end process; 36 end Behavioral;