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Verilog Manual

The document contains 12 Verilog code examples for common digital logic circuits including gates, binary to gray code conversion, counters, comparators, multiplexers, full adders, priority encoders, and up/down counters. The codes provide structural and behavioral modeling approaches for designing basic building blocks of digital systems in Verilog.

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Shiva Kumar A
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© Attribution Non-Commercial (BY-NC)
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Download as DOC, PDF, TXT or read online on Scribd
159 views

Verilog Manual

The document contains 12 Verilog code examples for common digital logic circuits including gates, binary to gray code conversion, counters, comparators, multiplexers, full adders, priority encoders, and up/down counters. The codes provide structural and behavioral modeling approaches for designing basic building blocks of digital systems in Verilog.

Uploaded by

Shiva Kumar A
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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“ HDL lab”

1)Verilog pgm to realize all gates

module allgate(a,b,y);
input a,b;
output [1:6] y;
assign y[1]= a & b,
y[2]= a | b,
y[3]= ~a ,
y[4]= ~(a & b),
y[5]= ~(a | b),
y[6]= a ^ b;
endmodule

2) Verilog pgm for binary to gray convertion

module b2g(b,g);
input [3:0] b;
output [3:0] g;

xor (g[0],b[0],b[1]),
(g[1],b[1],b[2]),
(g[2],b[2],b[3]);
assign g[3]=b[3];
endmodule

3)Verilog pgm for 4-bit counter

module cnt4(rst,clk,q);
input rst,clk;
output [3:0] q;
reg[3:0]q;
always @ (posedge clk)
if (rst==0)
q<= 0;
else
q<=q+1;
endmodule

IV Semister Verilog Lab Manual 1 ECEDEPARTMENT,GCE


“ HDL lab”

4) Verilog pgm for comparator

module comp(a,b,aeqb,agtb,altb);
input [3:0] a,b;
output aeqb,agtb,altb;
reg aeqb,agtb,altb;
always @(a or b)
begin
aeqb=0; agtb=0; altb=0;
if(a==b)
aeqb=1;
else if (a>b)

agtb=1;
else
altb=1;
end
endmodule

5)Verilog pgm for asyncronus counter with reset and enable

module count4(clk,resetn,en,q);
input clk,resetn,en;
output q;
reg q;

always@(posedge clk or negedge resetn)


if (resetn==0)
q<=0;
else if(en==1)
q<=q+1;
endmodule

6) verilog pgm for d flip flop

module dff(d,clk,q);
input d,clk;
inout q;
reg q;

always @(posedge clk)


q<=d;
endmodule

IV Semister Verilog Lab Manual 2 ECEDEPARTMENT,GCE


“ HDL lab”

7) verilog pgm for 1 to 8 DEMUX.

module dmux1t8 (I,sel,f);


input I;
input [2:0]sel;
output [7:0]f;
reg [7:0]f;

always@(I or sel)
begin
if(sel==3'b000)
f[7]=I;
else if(sel==3'b001)
f[6]=I;
else if (sel==3'b010)
f[5]=I;
else if (sel==3'b011)
f[4]=I;
else if (sel==3'b100)
f[3]=I;
else if (sel==3'b101)
f[2]=I;
else if (sel==3'b110)
f[1]=I;
else
f[0]=I;
end
endmodule

8) verilog code for full adder structural.

module fa (x,y,z,cout,sum);
input x,y,z;
output cout,sum;
wire P1,P2,P3;

HA HA1 (sum(P1),cout(P2),a(x), b(y));


HA HA2 (sum(sum),carry(P3),a(P1),b(Z));
OR1 ORG (P2,P3, Cout);

Endmodule

IV Semister Verilog Lab Manual 3 ECEDEPARTMENT,GCE


“ HDL lab”

9) verilog code for full adder behavioral.

module fulladd(cin,x,y,s,co);
input cin,x,y;
output s,co;
reg s,co;
always@(cin or x or y)
begin
case ({cin,x,y})

3'b000:{co,s}='b00;
3'b001:{co,s}='b01;
3'b010:{co,s}='b01;
3'b011:{co,s}='b10;
3'b100:{co,s}='b01;
3'b101:{co,s}='b10;
3'b110:{co,s}='b10;
3'b111:{co,s}='b11;
endcase
end
endmodule

10) verilog code for priority encoder

module priority(w,y,f);
input [3:0] w;
output [1:0] y;
output f;
reg [1:0]y;
assign f=(w!=0);
always @(w)
begin
casex(w)
'b1xxx:y=3;
'b1xxx:y=2;
'b1xxx:y=1;
default:y=0;
endcase
end
endmodule

IV Semister Verilog Lab Manual 4 ECEDEPARTMENT,GCE


“ HDL lab”

11) verilog pgm for priority encoder


module priority1(w,y,z);
input [3:0] w;
output [1:0] y;
output z;
reg [1:0] y;
reg z;
always@ (w)
begin
Z='1';
casex(w)
4'b1xxx:y=3;
4'b01xx:y=2;
4'b001x:y=1;
4'b0001:y=0;
default:
begin
Z=='0'
y==2'bx;
end
endcase
end
endmodule

12) verilog pgm for 4-bit updown counter

module updown(r,clk,l,e,u_d,q);
parameter n=8
input [n-1:0]r;
input clk,l,e,u_d;
output [n-1:0]q
reg [n-1:0]q;
integer dir;
always@(posedge clk)
begin
if (u_d)
dir=1;
else
dir=0;
if (l)
q<=r;
else if(e)
q<=Q+dir
end
endmodule

IV Semister Verilog Lab Manual 5 ECEDEPARTMENT,GCE

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