ECE 520 Class Notes

Synthesizable Verilog
Dr. Paul D. Franzon
Outline
1. Combinational Logic Examples.
2. Sequential Logic
3. Finite State Machines
4. Datapath Design
References
1. Smith and Franzon, Chapters 5, 8, Appendix A (on this web site)
2. M. Smith, Chapter 10, 11
3. D. Smith, Chapters 4, 6, 8.

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 1

ECE 520 Class Notes

Revision - Structure of a Module

D. Smith, Example 9.4 (modified) : Shift Register:
module shift_reg(clock, reset, load, sel, inload, shftreg);
input clock, reset, load;
input [4:0] sel;
input [3:0] inload;
output [3:0] shftreg;
reg [3:0] shftreg;
reg shftleft, shftright;
wire zero, ten, both;
always@(posedge clock)
if (reset)shftreg <= 0;
else if (load) shftreg <= inload;
else if (shftleft) shftreg <= shftreg << 1;
else if (shftright) shftreg <= shftreg >> 1;
always@(sel)
begin
shftleft = 1’b0; shftright = 1’b0;
casex (sel) //synopsys full_case
5’b000x1 : shftleft = 1’b1;
5’b0001x : shftright = 1’b1;
default : shftleft = 1’b0;
endcase
end
assign zero = (shftreg == 4’d0);
assign ten = (shftreg == 4’d10);
assign both = zero & ten;
endmodule
©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 2
 ECE 520 Class Notes

... Shift Register

1. Sketch circuit being described.
2. Consider the always@(posedge clock) procedural block
l Is the reset synchronous (synchronized with the clock) or asynchronous?

l Every variable assigned to in this procedural block becomes a ......

3. Consider the always@(sel) procedural block

l What is a casex() statement?

l Why are no latches inferred?

The //synopsys full_case tells Synopsys that all alternatives have been specified,
thus preventing latches. It is an example of a Synopsys Directive. The ‘default’ and
pre-assignment works to prevent unintentional latches also.

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 3

ECE 520 Class Notes

Revision - Design Steps

1. Understand the specification fully
l Preferably have a C or Verilog code that captures the overall behavior
2. Design the hardware
l The closer it looks like the final netlist, the better your synthesis results generally are.
l At least explicitly identify ALL OF THE FOLLOWING:
u Registers
u Combinational logic blocks and their functions
u interconnecting wires
l Think carefully about the following:
u What happens on power up?
Ð On power-up all signals take random values (Verilog does not simulate this
… on power up, all signals are initialized as ‘x’ for unknown)
Ð Is the behavior safe or do you need a reset signal?
u What happens before and after each clock edge

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 4

 ECE 520 Class Notes

…Design Steps
3. Write your Verilog:
l All register outputs are assigned within always@(posedge clock) blocks
u Also place register input logic within these blocks
u EVERY VARIABLE ASSIGNED WITHIN SUCH A BLOCK BECOMES THE
OUTPUT OF A FLIP-FLOP
l Combinational logic can be designed:
u As input logic to the registers, or,
u as its own Procedural block, or,
u using continuous assignment, or,
u structurally (see later)
4. Write your verification test fixture
l Make sure your verification is as complete as possible (see later section)
5. Synthesize your design
l Fix all Errors, understand or fix (as appropriate) all Warnings
l Make sure timing is met (‘slack (met)’)
6. Conduct post-synthesis verification
l Especially, timing and function
©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 5

ECE 520 Class Notes

Combinational Logic Approaches

The following types of examples are given:
• Logic built in procedural blocks
l Encoders, decoders, selectors (multiplexors)
l Some other useful constructs
• Logic built using continuous assignment
l Gate-level logic, multiplexors
• Logic specified directly in the target library

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 6

 ECE 520 Class Notes

Priority Encoder
Truth Table: A2 A1 A0 Y1 Y0
0 0 0 0 0
0 0 1 F 0
0 1 X 0 F
1 X X 1 1
Capture in Verilog using if-then-else or a casex statement:
input [2:0] A;
input F;
reg [1:0] Y;
always@(A or F)
begin
if (A[2]) Y = 2’b11;
else if (A[1]) Y = {1’b0,F};
else if (A[0]) Y = {F,1’b0};
else Y = 2’b00;
end

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 7

ECE 520 Class Notes

…Priority Encoder
begin
casex (A) //synopsys full_case
3’b1xx : Y = 2’b11;
3’b01x : Y = {1’b0,F};
3’b001 : Y = {F,1’b0};
default : Y = 2’b00;
endcase
end

case and casex statements are much like the C ‘switch’ statement
l Only one alternative is selected though
casex statement allows some of the alternatives to contain ‘don’t cares’

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 8

 ECE 520 Class Notes

Non-Priority Encoder
Truth Table: A2 A1 A0 Y1 Y0
all others 0 0
0 0 1 F 0
0 1 0 0 F
1 0 0 1 1

Capture in a Verilog case statement:

input [2:0] A;
input F;
reg [1:0] Y;
always@(A or F)
case (A) \\ synopsys full_case parallel_case
3’b100 : Y = 2’b11;
3’b010 : Y = {1’b0,F};
3’b001 : Y = {F,1’b0};
default : Y = 2’b00;
endcase

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 9

ECE 520 Class Notes

...Procedural Blocks
//synopsys parallel_case tells Synopsys we only ever expect one of the case
alternatives to be true, leading to non-priority logic which is usually smaller.
Q. Why do the examples on the previous page describe priority logic while the example on
this page describes non-priority logic?

Q. How are latches prevented in these cases?

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 10

 ECE 520 Class Notes

Exercise
Implement the following logic: OP[1:0] Fu nct[4:0] Sel[1:0] B
01 x 11 0

11 xxx11 01 1
11 xxx01 10 1

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 11

ECE 520 Class Notes

Other Procedural Block Examples

Loops can be used (with care) to specify logic:

integer i;
reg [7:0] A;

always@(A)
begin
OddParity = 1’b0;
for (i=0; i<=7; i=i+1)
if (A[i]) OddParity = ~OddParity;
end
Is the following code fragment synthesizable?
integer i, N;
parameter N=7;
reg [N:0] A;
always@(A)
begin
OddParity = 1’b0;
for (i=0; i<=N; i=i+1)
if (A[i]) OddParity = ~OddParity;
end
©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 12
 ECE 520 Class Notes

…Other Procedural Block Examples

The loop constructs (for, repeat, while) can sometimes be used to specify
combinational logic
l For example, to traverse an array of bits
l The loop determination must be a constant
u If it’s a variable, the size of the loop can not be determined staticly and thus the
loop can not be synthesized

Generally, the following statements are rarely used in synthesizable designs:

wait, forever, disable, [procedural] assign/deassign,
force, release
• forever is unsynthesizable in Synopsys under all uses.

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 13

ECE 520 Class Notes

Logic Built Using Continuous Assignment

Example 1. Multiplexor built via indexing:
input [2:0] bc;
input A, B, C;
input [3:0] D, E;
wire [7:0] codes;
wire final;

assign codes = {1’b1, {2{C}}, ~&D, A^B, !A, A&B, D>E};

assign final = codes[bc[2:0]];
Draw this logic:

Notes:
l Multiplexor-based design is often smaller and faster than logicgate based design in
CMOS. Often structural code has to be used to force this implementation style.
l Explicit coding of width and msb of bc in final = codes[bc[1:0]];

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 14

 ECE 520 Class Notes

Continuous Assignment Logic

Examples:
1.
wire foo;
wire [3:0] bar;

assign foo = select ? &bar : ^bar;

2.
wire [7:0] mush;
tri [3:0] bus;

assign bus = enable ? mush[4:1] : 4’bz;

• A continuous assignment logic style must be used in Synthesis for tri-state logic.

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 15

ECE 520 Class Notes

Registers
Some Flip Flop Types:
reg Q0, Q1, Q2, Q3, Q4; Note:
// D Flip Flop Registers with asynchronous
always@(posedge clock) reset are smaller than
Q0 <= D;
// D Flip Flop with asynchronous reset
those with synchronous
always@(posedge clock or negedge reset)
if (!reset) Q1 <= 0;
reset
else Q1 <= D; + don’t need clock to reset
// D Flip Flop with synchronous reset BUT it is a good idea to
always@(posedge clock)
if (!reset) Q2 <= 0; sychronize reset at the block
else Q2 <= D;
level to reduce impact of noise.
// D Flip Flop with enable
always@(posedge clock)
if (enable) Q3 <= D;
// D Flip Flop with synchronous clear and preset
always@(posedge clock)
if (!clear) Q4 <= 0;
else if (!preset) Q4 <= 1;
else Q4 <= D;

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 16

 ECE 520 Class Notes

Finite State Machine Types

Finite State Machines can be classified by the following attributes:
• Moore or Mealy type outputs

Next Output Moore Outputs

State Logic Outputs depend
Logic solely on state vector
State
(generally, a Moore FSM
Reg.
is the simplest to
State Vector design)

Next Output Mealy Outputs

State Logic Outputs depend
Logic on inputs and state vector
State
(only use if it is significantly
Reg.
State Vector smaller or faster)

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 17

ECE 520 Class Notes

… FSM Types
• State Vector Encoding
l Minimal encoding
u Minimum number of bits
l Minimum, sequential encoding
u Minimum number of bits and states in sequence
Ð Does not necessarily optimize ‘next state logic’ size
l Gray encoding
u state bit changes by only one bit between sequential states
Ð Minimizes switching activity in state vector register
l One-hot encoding
u one bit per state
Ð usually gives fastest ‘next state’ logic
Example: 7-state FSM, states S0 … S7:

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 18

 ECE 520 Class Notes

… FSM Types
• Resets:
l Reset usually occurs only on power-up and when someone hits the ‘reset’ button
l Asynchronous reset:
u FSM goes to reset state whenever reset occurs
l Synchronous reset:
u FSM goes to reset state on the next clock edge after reset occurs
l Asynchronous reset leads to smaller flip-flops while synchronous reset is ‘safer’
(noise on the reset line is less likely to accidently cause a reset).

• Fail-Safe Behavior:
l If the FSM enters an ‘illegal’ state due to noise is it guaranteed to then enter a
legal state?
u ‘Yes’ is generally desirable

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 19

ECE 520 Class Notes

… FSM Types
• Sequential Next state or output logic
l Usually, these blocks are combinational logic only
l However, can place sequential logic (e.g. a counter, or a toggle-flip-flop) in these
blocks if it is advantageous
l AVOID DOING THIS AS MUCH AS YOU CAN UNLESS YOU ARE REALLY
SURE ABOUT WHAT YOU ARE DOING
u Sequential next state or output logic can get very confusing to design and debug
• Registered or Unregistered Outputs
l Do not register the outputs unless you need to ‘deglitch’ the outputs (for example, for
asynchronous handshaking - combinational logic has to be assumed to be glitchy) or
are pipelining the control
l e.g. Next Output
State Logic reg_out
Logic State
Reg.
State Vector

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 20

 ECE 520 Class Notes

Example - Drag Racing Lights

At the start of a new race (‘car’), go through the Red-Yellow-Green sequence:

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 21

ECE 520 Class Notes

Drag Light Controller ...Verilog

module traffic_light_controller (clock, reset, car, red, yellow, green);
input clock;
input reset;
input car;
output red, yellow, green;
parameter [1:0] // synopsys enum states
S0 = 2’b00,
S1 = 2’b01,
S2 = 2’b10,
S3 = 2’b11;
reg [1:0] /* synopsys enum states */ current_state, next_state;
// synopsys state_vector current_state
reg red, yellow, green;
/*------- Sequential Logic ----*/
always@(posedge clock or negedge reset)
if (!reset) #1 current_state <= S0;
else #1 current_state <= next_state;
/* next state logic and output logic */
always@(current_state or car)
begin
red = 0; yellow = 0; green = 0; /* defaults to prevent latches */
case (current_state) // synopsys full_case parallel_case
S0: begin
red = 1;
if (car) next_state = S1
else next_state = S0;
end
S1: begin
yellow = 1;
next_state = S2;
end
S2 : begin
green = 1;
next_state = S0;
end
default : next_state = S0;
endcase
end
endmodule

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 22

 ECE 520 Class Notes

FSM Verilog Notes

1. Code each FSM by itself in one module.
2. Separate Sequential and Combinational Logic
3. Is this reset Synchronous or Asynchronous?

l Asynchronous usually results in less logic (reset is actually synchronized when it

enters the chip).
4. Note use of Synthesis directives:
l //synopsys enum states and //synopsys state_vector
current_state tell Synopsys what the state vector is.
l Why can we state //synopsys full_case parallel_case for FSMs?

5. How to we prevent accidently inferring latches?

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 23

ECE 520 Class Notes

FSM Synthesis...Script Extract...

replace_synthetic /* map onto generic logic - could use compile */
ungroup -all -flatten /* create one single level */

/* optimize the FSM */

set_fsm_state_vector {current_state_reg[0] current_state_reg[1]}
set_fsm_encoding {}
set_fsm_encoding_style auto /*auto=encode state vector for min. area*/
group -fsm -design_name traffic_fsm
current_design = traffic_fsm
report_fsm
extract
report_fsm
set_fsm_minimize true
compile

/* optimize the design at the top level */

current_design = traffic_light_controller
compile

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 24

 ECE 520 Class Notes

FSM State Encoding Options

Can either do `by hand’ in Verilog source code or by reassigning states in Synopsys:
u Binary or Sequential (minimal) encoding:
State 0 = 000
State 1 = 001, etc.
u Gray encoding gives the minimum change in the state vector between states:
State 0 = 000
State 1 = 001
State 2 = 011, etc
Ð Reduces state transition errors caused by asynchronous inputs changing during flip-
flop set-up times.
Ð Minimizes power consumed in state vector flip-flops
Synopsys: set_fsm_encoding_style gray //+ See manual
u One-hot encoding assigns one flip-flop per state:
State 0 = 0001
State 1 = 0010
State 2 = 0100, etc
Ð Fastest but largest design
Synopsys: set_fsm_encoding_style one_hot
u Custom: Assign states by hand in Verilog of Synopsys

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 25

ECE 520 Class Notes

Registering FSM Outputs

Sometimes useful to register the outputs of FSMs:
l Necessary when these outputs are interfacing asynchronously with other modules or
off-th-chip
u e.g. RAS and CAS outputs for a memory interface
l Useful if delays in output combinational logic are making it hard to meet timing
requirements in the module they are connected to.
u assumes flip-flop t_cp_Q is faster (might not be - look in library sheets)
e.g.
always@(posedge clock) Output
begin
red = int_red; Logic from
yellow = int_yellow; FSM
green = int_green;
end
...
case (current_state)
S0: begin int_red=1;
l Note: changes now delayed one clock when compared with previous version

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 26

 ECE 520 Class Notes

Final Exercise
Linear Feedback Shift Register
• Used to generate a pseudo-random sequence of numbers
l ‘pseudo-random’ because the number sequence cycles
• Next number obtained by ‘hashing’ the previous number with a bunch of XOR
gates
l With the right design, no number is ever repeated (up to 2N, where N = # bits)

Applications
• Random number generators
• Built In Self Test (BIST)
l Generates test vector sequence for production test of a block of logic
• Used in data encryption, checksum generation, and data compression techniques

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 27

ECE 520 Class Notes

Final Exercise
What is the following Verilog building? (D. Smith, Example 7.10)
module LFSR_8BIT (Clock, Reset, Y);
input Clock, Reset;
output [7:0] Y;
integer N [1:7];
parameter [7:0] Taps = 8’b10001110;
reg Bits0_6_Zero, Feedback;
reg [7:0] LFSR_Reg, Next_LFSR_Reg;
always@(posedge clock or negedge Reset)
begin: LFSR_Reg
if (!Reset)
LFSR_Reg <= 8’b0;
else
LFSR_Reg <= Next_LFSR_Reg;
end

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 28

 ECE 520 Class Notes

…exercise
always@(LFSR_Reg)
begin: LFSR_Feedback
Bits0_6_Zero = ~| LFSR_Reg[6:0];
Feedback = LFSR_Reg[7] ^ Bits0_6_Zero;
for (N=7; N>=1; N=N-1)
if (Taps[N-1] == 1)
Next_LFSR_Reg[N] = LFSR_Reg[N-1] ^ Feedback;
else
Next_LFSR_Reg[N] = LFSR_Reg[N-1];
Next_LFSR_Reg[0] = Feedback;
end

assign Y = LFSR_Reg;

endmodule

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 29

ECE 520 Class Notes

Features of Design
• Parameterized Design:
l Details of design can be changed by changing Taps (see example)

• Employing Functions and Tasks

l See examples provided

• always@(LFSR_Reg) block
l Note ‘chain’ of logic in this block
u Intermediate results used on road to final result

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 30

 ECE 520 Class Notes

Summary
l Combinational Logic implied by always@(x ...) or assign statements
u Try to build unprioritized logic in a case statement when possible
u Use structural Verilog (assign) to build muxes for smallest fastest design

l Continuous Assignment Logic

u Often leads to most efficient implementation
u Only approach to building tri-state buses

l Finite State Machines

u Describe and optimize separately from datapath and random logic
u Consider style of implementation for best design

©2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 31