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Lect 3: Instruction Set and Addressing Modes

This document discusses the instruction set and addressing modes of the Intel 386 microprocessor. It describes the basic, extended, and 386-specific instruction sets. It then explains the various addressing modes including register, immediate, direct, indirect, based, indexed, and based-indexed addressing. Finally, it notes that the 32-bit 386 enhanced memory addressing with scale factors and allowed 32-bit displacements, controlled by the default bit and size prefixes.

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0% found this document useful (0 votes)
21 views

Lect 3: Instruction Set and Addressing Modes

This document discusses the instruction set and addressing modes of the Intel 386 microprocessor. It describes the basic, extended, and 386-specific instruction sets. It then explains the various addressing modes including register, immediate, direct, indirect, based, indexed, and based-indexed addressing. Finally, it notes that the 32-bit 386 enhanced memory addressing with scale factors and allowed 32-bit displacements, controlled by the default bit and size prefixes.

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kalpita85
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© Attribution Non-Commercial (BY-NC)
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Download as PPT, PDF, TXT or read online on Scribd
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Lect 3: Instruction Set and

Addressing Modes
386 Instruction Set (3.4)

– Basic Instruction Set : 8086/8088 instruction set


– Extended Instruction Set : 80286; several new instructions and add
itional addressing modes
– 80386 specific instruction set:

8086/8088 80286 80386


Protected Mode

System control System control


Instruction set Instruction set

Basic + Basic +
Basic
Extended Extended+
Instruction
Instruction 80386 specific
Set
Set Instruction
Set

Real Mode
386 Instruction Set (3.4)

• Addressing Modes of 386DX (3.5)

– Addressing Modes: a method of specifying an operand


• Operands : in REG, Memory, I/O ports, and within Instruction
– * Control Transfer : direct, indirect addressing
– the modes available
register addressing : REG
immediate addressing: within Instruction
direct addressing
register indirect addressing
based addressing
MEM or I/O
indexed addressing
based indexed addressing
Addressing Modes

– Register Operand Addressing Mode


• can be accessed in byte, word, or double word sizes.
• MOV AX, BX
• Byte: AL, AH, BL, BH, CL, CH, DL, DH
Word: AX, BX, CX, DX, SP, BP, SI, DI, CS, DS, SS, ES, FS, GS
Double Word: EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI
• See Fig 3.8 in page 64
– Immediate Operand Addressing
• an operand is part of the instruction
• MOV AL, 15H
• 8 bits, 16 bits, and 32 bits in length
• See Fig 3.10 in page 67
Register Addressing

Address Memory
Instruction
80386 Content
0000 IP
MPU
0100 CS 01000 8B MOV AX, BX
DS 01001 C3
SS 01002 XX
ES
FS
GS

XXXX
ABCD AX
ABCD BX
CX
DX

SP
BP
SI
DI
Immediate Addressing

Address Memory
Instruction
80386 Content
0000 IP
MPU
0100 CS 01000 B0 MOV AL, 15H
DS 01001 15
SS 01002 XX
ES
FS
GS

15
XX AX
BX
CX
DX

SP
BP
SI
DI
Direct Addressing

• 16-bit Memory Operand Addressing Modes


– 16-bit addressing modes and 32-bit addressing modes
– Physical address = Segment Base: EA(effective address)
• Segment Base Address(SBA) : the starting location of the
segment
• EA : the offset of the operand from the beginning of the
segment of memory
EA = Base + Index + Displacement
Base = BX or BP, Index = SI or DI, displacement = 8-bit
or 16-bit
16-bit Memory Operand Addressing

– Direct Addressing Mode


• PA = Segment Base : Direct Address
• MOV CX, [1234H]
01000 8B MOV CX, [1234H]
01001 0E
0000 IP 01002 34
01003 12
0100 CS XX
01004
0200 DS
SS
ES
FS
GS
AX
XXXX BX
CX 03234 ED
DX 03235 BE
SP
BP
SI BEED
DI
16-bit Memory Operand Addressing

– Register Indirect Addressing Mode


• PA = Segment Base : Indirect Address {BX,BP,SI,DI}
• example : MOV AX, [SI]
01000 8B MOV AX,[SI]
01001 04
0000 IP 01002 XX
01003 XX
0100 CS XX
01004
0200 DS
SS
ES
FS
GS
XXXX AX
BX
CX 03234 ED
DX 03235 BE
SP
BP
1234 SI BEED
DI
16-bit Memory Operand Addressing
• Based Addressing Mode
– PA = Segment Base : {BX or BP} + {8-bit or 16-bit displacement}
– Base register : the beginning of a data structure (See Fig 3.16 (b) in page 74
– Example: MOV [BX]+1234H, AL
01000 88 MOV [BX]+1234H, AL
01001 07
0000 IP 01002 34
01003 12
0100 CS XX
01004
0200 DS
SS
ES
FS
GS Element n-1
Displacement
ED AX
1000 BX Data Structure
CX 04234 +
DX 04235
Element 1
SP Base Register
BP Element 0
1234 SI
DI
16-bit Memory Operand Addressing
– Indexed Addressing Mode
• PA = Segment Base : {SI, DI}+{8-bit or 16-bit displacement}
• Displacement : the starting address of an array; Index: selects the specific element in the array
• Example: MOV AL, [SI]+2000H

01000 8A MOV AL, [SI]+1234H


01001 44
0000 IP 01002 34
01003 12
0100 CS XX
01004
0200 DS
SS
ES
FS
GS Index Register Element n-1

XX AX
1000 BX Array of data
CX 05234 BE +
DX 05235
Element 1
SP Displacement
BP Element 0
2000 SI
DI
16-bit Memory Operand Addressing

– Based-Indexed Addressing Mode


• PA= Seg Base: {BX, BP}+{SI,DI}+{8-bit or 16-bit
displacement}
• to access complex data structures
• See fig 3.20 in page 80
• Example: MOV AH, [BX][SI]+1234H
opcode : 8A 44 34 12
32-bit Memory Operand Addressing Modes

– Enhanced in two ways


• Scale factor : EA = base + (index x scale factor) + displacemen
t
• PA = Segment Base: EA

AX 
  AX 
CS  BX   
SS  CX  BX  1
    CX   
DS DX    2 8  bit displacement 
PA    :    DX       
ES SP
    BP    4 32 - bit displacement 
FS  BP    8 
    SI 
GS SI   
DI  DI 
 
32-bit Memory Operand Addressing Modes

– See fig 3.23 in page 83: change 16-bit displacement to 32-bit


displacement
– How can we specify the 32-bit extension modes?
• Default (D) bit in the code segment descriptor
• 2 prefixes to the instruction set
Operand size prefix
Address size prefix

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