CITY ENGINEERING COLLEGE

Doddakallasandra, Off Kanakapura Road, Bangalore - 560061

4TH SEM ELECTONICS AND COMMUNICATION

S K LAKSHMI NARAYAN R C VISHVAKIRAN

HDL LAB MANUAL

10ESL 48
ELECTRONICS AND COMMUNICATION ENGG DEPT.

CONTENTS PART A: PROGRAMMING (using VHDL and Verilog) 1. Write HDL code to realize all the logic gates ................................................................................ 1 2. Write a HDL program for the following combinational designs ............................................... 3-16 a. 2 to 4 decoder ............................................................................................................................ 3 b. 8 to 3 (encoder without priority & with priority) .................................................................. 5,7 c. 8 to 1 multiplexer ..................................................................................................................... 9 d. 4 bit binary to gray converter ................................................................................................. 11 e. De-multiplexer, comparator .............................................................................................. 13,15 3. Write a HDL code to describe the functions of a Full Adder Using 3 modeling styles .......... 17-21 a. Full Adder Data Flow Description ......................................................................................... 17 b. Full Adder Behavioral Description ........................................................................................ 18 c. Full Adder Structural Description .......................................................................................... 20 4. Write a model for 32 bit ALU using the schematic diagram shown below A (31:0) B (31:0) ................................................................................................... 22 ALU should use combinational logic to calculate an output based on the four-bit op-code input. ALU should pass the result to the out bus when enable line in high, and tri-state the out bus when the enable line is low. ALU should decode the 4 bit op-code according to the given in example below. OPCODE ALU OPERATION 1. 2. 3. 4. 5. 6. 7. A+B AB A Complement A AND B A OR B A NAND B A XOR B
ENABLE OPCODE ALU OPERATION

5. Develop the HDL code for the following flip-flops, SR, JK, D, T ......................................... 24-31 a. SR Flip Flop ........................................................................................................................... 24 b. JK Flip Flop ............................................................................................................................ 26 c. D Flip Flop ............................................................................................................................. 28 d. T Flip Flop .............................................................................................................................. 30 6. Design 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset) and any sequence counters .................................................................................................... 32-40 a. Binary Synchronous Reset 4bit Counter ................................................................................ 32 b. Binary Asynchronous Reset 4bit Counter .............................................................................. 33 c. BCD Synchronous Reset 4bit Counter ................................................................................... 35 d. BCD Asynchronous Reset 4bit Counter ................................................................................. 37 e. Binary Any Sequence up down 4bit Counter ......................................................................... 39

PART B: INTERFACING (at least four of the following must be covered using VHDL/Verilog) 1. Write HDL code to display messages on the given seven segment display and LCD and accepting Hex keypad input data .............................................................................................................. 41-47 a. 7 Segment Display ................................................................................................................. 41 b. LCD Display .......................................................................................................................... 45 2. Write HDL code to control speed, direction of DC and Stepper motor .................................. 48-53 a. Stepper Motor ......................................................................................................................... 48 b. DC Motor ............................................................................................................................... 51 3. Write HDL code to control external lights using relays. .............................................................. 54 4. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,) using DAC change the frequency and amplitude ............................................... 56-66 a. Sine Wave .............................................................................................................................. 57 b. Square Wave .......................................................................................................................... 59 c. Triangle Wave ........................................................................................................................ 61 d. Positive Ramp ........................................................................................................................ 63 e. Negative Ramp ....................................................................................................................... 65

Web link: http://www.scribd.com/doc/49031100

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4TH SEM, HDL MANUAL, 10ESL48

2012
not_op and_op nand_op outputs or_op nor_op xor_op xnor_op

E&C DEPT., CEC, BANGALORE

1.

ALL LOGIC GATES

a_in inputs b_in Figure 1: Block Diagram of All Logic Gates
not_op

ALL LOGIC GATES

a_in b_in

and_op

nand_op or_op nor_op xor_op xnor_op

Logic Diagram of All Gates

Inputs a_in b_in 0 0 1 1 0 1 0 1

not_op and_op nand_op or_op nor_op xor_op xnor_op (a_in) 1 0 1 0 1 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 0 1 0 0 1 Truth Table 1: All Logic Gates

Outputs

VHDL File Name: AlllogicGates.vhd -- All Logic Gates - DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity AllLogicGates is port ( a_in : in STD_LOGIC; b_in : in STD_LOGIC; not_op : out STD_LOGIC; and_op : out STD_LOGIC; nand_op : out STD_LOGIC; or_op : out STD_LOGIC; nor_op : out STD_LOGIC; xor_op : out STD_LOGIC; xnor_op : out STD_LOGIC); end AllLogicGates;
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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

architecture DataFlow of AllLogicGates is begin not_op <= not a_in; and_op <= a_in and b_in; nand_op <= a_in nand b_in; or_op <= a_in or b_in; nor_op <= a_in nor b_in; xor_op <= a_in xor b_in; xnor_op <= a_in xnor b_in; end DataFlow; Verilog File Name: AlllogicGates.v // All Logic Gates module AllLogicGates( a_in, b_in, not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op ); input a_in, b_in; output not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op; assign assign assign assign assign assign assign endmodule not_op and_op nand_op or_op nor_op xor_op xnor_op = = = = = = = ~(a_in); a_in & ~(a_in & a_in | ~(a_in | a_in ^ ~(a_in ^

b_in; b_in); b_in; b_in); b_in; b_in);

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

2.

Decoder 2 to 4
d_in 2 inputs en Figure 2: Block Diagram of Decoder 2 to 4 4 outputs

Decoder 2 to 4

d_op

en 1 0 0 0 0

Inputs Outputs d_in(1) d_in(0) d_op(3) d_op(2) d_op(1) X X Z Z Z 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 Truth Table 2: Decoder 2 to 4

d_op(0) Z 1 0 0 0

VHDL File Name: decoder2to4.vhd -- decoder2to4 - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder2to4 is Port ( d_in : in STD_LOGIC_VECTOR (1 downto 0); en : in STD_LOGIC; d_op : out STD_LOGIC_VECTOR (3 downto 0)); end decoder2to4; architecture Behavioral of decoder2to4 is begin process(en,d_in) begin if(en/='0')then -- Active Low Enabled d_op<="ZZZZ"; else case d_in is when "00" => d_op <= "0001"; when "01" => d_op <= "0010"; when "10" => d_op <= "0100"; when "11" => d_op <= "1000"; when others => d_op <= "ZZZZ"; end case; end if; end process; end Behavioral;

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

Verilog File Name: decoder2to4.v // decoder2to4 module decoder2to4( d_in, en, d_op ); input [1:0] d_in; input en; output [3:0] d_op; wire en; wire [1:0] d_in; reg [3:0] d_op; always @ (en, d_in) begin if(en) // Active Low Enabled d_op = 4'bZZZZ; else begin case (d_in) 2'b00 : d_op = 4'b0001; 2'b01 : d_op = 4'b0010; 2'b10 : d_op = 4'b0100; 2'b11 : d_op = 4'b1000; default : d_op = 4'bZZZZ; endcase end end endmodule

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

3.

Encoder Without Priority

a_in

8 inputs Encoder Without Priority 3 outputs

y_op

en Figure 3: Block Diagram of Encoder Without Priority

Inputs en a_in(7) a_in(6) a_in(5) a_in(4) a_in(3) a_in(2) a_in(1) a_in(0) 1 0 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 1 X 0 0 0 0 0 0 1 0 X 0 0 0 0 0 1 0 0 X 0 0 0 0 1 0 0 0 X 0 0 0 1 0 0 0 0 X 0 0 1 0 0 0 0 0 X 0 1 0 0 0 0 0 0 X 1 0 0 0 0 0 0 0 Outputs y_op y_op y_op (2) (1) (0) Z 0 0 0 0 1 1 1 1 Z 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1

Truth Table 3: Encoder Without Priority VHDL File Name: encd_wo_prior.vhd -- encoder without priority - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encd_wo_prior is Port ( en : in STD_LOGIC; a_in : in STD_LOGIC_VECTOR (7 downto 0); y_op : out STD_LOGIC_VECTOR (2 downto 0)); end encd_wo_prior;

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

architecture Behavioral of encd_wo_prior is begin process (en,a_in) begin if(en /= '0') then -- Active Low Enabled y_op <= "ZZZ"; else case a_in is when "00000001" => y_op <= "000"; when "00000010" => y_op <= "001"; when "00000100" => y_op <= "010"; when "00001000" => y_op <= "011"; when "00010000" => y_op <= "100"; when "00100000" => y_op <= "101"; when "01000000" => y_op <= "110"; when "10000000" => y_op <= "111"; when others => y_op <= "ZZZ"; end case; end if; end process; end Behavioral; Verilog File Name: encd_wo_prior.v // encoder without priority module encd_wo_prior( en, a_in, y_op ); input en; input [7:0] a_in; output [2:0] y_op; wire en; wire [7:0] a_in; reg [2:0] y_op; always @ (a_in, en) begin if(en) //Active Low Enabled y_op = 3'bZZZ; else begin case (a_in) 8'b00000001 : y_op = 3'b000; 8'b00000010 : y_op = 3'b001; 8'b00000100 : y_op = 3'b010; 8'b00001000 : y_op = 3'b011; 8'b00010000 : y_op = 3'b100; 8'b00100000 : y_op = 3'b101; 8'b01000000 : y_op = 3'b110; 8'b10000000 : y_op = 3'b111; default : y_op = 3'bZZZ; endcase end end endmodule
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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

4.

Encoder With Priority

a_in

8 inputs Encoder With Priority 3 outputs

y_op

en Figure 4: Block Diagram of Encoder With Priority

Inputs en 1 0 0 0 0 0 0 0 0 a_in(7) X 1 0 0 0 0 0 0 0 a_in(6) X X 1 0 0 0 0 0 0 a_in(5) X X X 1 0 0 0 0 0 a_in(4) X X X X 1 0 0 0 0 a_in(3) X X X X X 1 0 0 0 a_in(2) X X X X X X 1 0 0 a_in(1) X X X X X X X 1 0 a_in (0) X X X X X X X X 1 y_op (2) Z 1 1 1 1 0 0 0 0 Outputs y_op (1) Z 1 1 0 0 1 1 0 0 y_op (0) Z 1 0 1 0 1 0 1 0

Truth Table 4: Encoder With Priority VHDL File Name: encd_w_prior.vhd -- encd_w_prior - Dataflow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encd_w_prior is Port ( en : in STD_LOGIC; a_in : in STD_LOGIC_VECTOR (7 downto 0); y_op : out STD_LOGIC_VECTOR (2 downto 0)); end encd_w_prior;

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

architecture Dataflow of encd_w_prior is begin y_op <= "ZZZ" when en = '1' else -"111" when a_in(7)='1' "110" when a_in(6)='1' "101" when a_in(5)='1' "100" when a_in(4)='1' "011" when a_in(3)='1' "010" when a_in(2)='1' "001" when a_in(1)='1' "000" when a_in(0)='1' "ZZZ"; end Dataflow; Verilog File Name: encd_w_prior.v // encoder with priority module encd_w_prior( en, a_in, y_op ); input en; input [7:0] a_in; output [2:0] y_op; wire en; wire [7:0] a_in; reg [2:0] y_op;

Active Low Enabled else else else else else else else else

always @ (a_in, en) begin if (en == 1'b1) // Active Low Enabled y_op = 3'bZZZ; else begin if(a_in[7] == 1'b1) y_op = 3'b111; else if(a_in[6] == 1'b1) y_op = 3'b110; else if(a_in[5] == 1'b1) y_op = 3'b101; else if(a_in[4] == 1'b1) y_op = 3'b100; else if(a_in[3] == 1'b1) y_op = 3'b011; else if(a_in[2] == 1'b1) y_op = 3'b010; else if(a_in[1] == 1'b1) y_op = 3'b001; else if(a_in[0] == 1'b1) y_op = 3'b000; else y_op = 3'bZZZ; end end endmodule

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

5.

Multiplexer 8 to 1
i_in 8 inputs en 3

Multiplexer 8 to 1 output

y_out

sel

Figure 5: Block Diagram of Multiplexer 8 to 1

Inputs i_in (5) X 0 0 0 0 0 1 0 0 Output i_in (4) X 0 0 0 0 1 0 0 0 i_in (3) X 0 0 0 1 0 0 0 0 i_in (2) X 0 0 1 0 0 0 0 0 i_in (1) X 0 1 0 0 0 0 0 0 i_in (0) X 1 0 0 0 0 0 0 0 y_out Z 1 1 1 1 1 1 1 1

en 1 0 0 0 0 0 0 0 0

sel (2) X 0 0 0 0 1 1 1 1

sel (1) X 0 0 1 1 0 0 1 1

sel (0) X 0 1 0 1 0 1 0 1

i_in (7) X 0 0 0 0 0 0 0 1

i_in (6) X 0 0 0 0 0 0 1 0

Truth Table 5: Mux 8 to 1 VHDL File Name: mux8to1.vhd --mux8to1 - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux8to1 is Port ( en : in STD_LOGIC; sel : in STD_LOGIC_VECTOR (2 downto 0); i_in : in STD_LOGIC_VECTOR (7 downto 0); y_out : out STD_LOGIC); end mux8to1; architecture Behavioral of mux8to1 is begin process(en,sel,i_in) begin

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if( en /= '0') then -- Active Low Enabled y_out <= 'Z'; else case sel is when "000" => y_out <= i_in(0); when "001" => y_out <= i_in(1); when "010" => y_out <= i_in(2); when "011" => y_out <= i_in(3); when "100" => y_out <= i_in(4); when "101" => y_out <= i_in(5); when "110" => y_out <= i_in(6); when "111" => y_out <= i_in(7); when others => y_out <= 'Z'; end case; end if; end process; end Behavioral; Verilog File Name: mux8to1.v // Multiplexer 8 to 1 module mux8to1(en,i_in,sel,y_out); input en; input [2:0] sel; input [7:0] i_in; output y_out; wire en; wire [7:0] i_in; wire [2:0] sel; reg y_out; always@(en,sel,i_in) begin if(en != 0) // Active Low Enabled y_out = 1'bZ; else begin case(sel) 3'b000: y_out = i_in[0]; 3'b001: y_out = i_in[1]; 3'b010: y_out = i_in[2]; 3'b011: y_out = i_in[3]; 3'b100: y_out = i_in[4]; 3'b101: y_out = i_in[5]; 3'b110: y_out = i_in[6]; 3'b111: y_out = i_in[7]; default: y_out = 1'bZ; endcase end end endmodule

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

6.

4Bit Binary to Gray Converter

b_in

inputs 4

Binary to Gray Converter

4 outputs

g_op

Figure 6: Block Diagram of Binary to Gray Converter

b_in(0) b_in(1) b_in(2) b_in(3) g_op(0) g_op(1) g_op(2) g_op(3)

Logic Diagram of 4bits Binary to Gray Converter

Boolean Expressions g_op(3) = b_in(3) g_op(2) = b_in(3) b_in(2) g_op(1) = b_in(2) b_in(1) g_op(0) = b_in(1) b_in(0)
Inputs Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 b_in(3) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Binary b_in(2) b_in(1) 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

b_in(0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

g_op(3) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Outputs Gray g_op(2) g_op(1) 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0

g_op(0) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

Truth Table 6: Binary to Gray

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VHDL File Name: bin_to_gray_4bit.vhd -- Binary to Gray 4 bit converter - Dataflow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bin_to_gray_4bit is Port ( b_in : in STD_LOGIC_VECTOR (3 downto 0); g_op : out STD_LOGIC_VECTOR (3 downto 0)); end bin_to_gray_4bit; architecture Dataflow of bin_to_gray_4bit is begin g_op(3) <= b_in(3); g_op(2) <= b_in(3) xor b_in(2); g_op(1) <= b_in(2) xor b_in(1); g_op(0) <= b_in(1) xor b_in(0); end Dataflow;

Verilog File Name: bin_to_gray_4bit.v // Binary to Gray 4bit Converter module bin_to_gray_4bit( b_in, g_op ); input [3:0] b_in; output [3:0] g_op; wire [3:0] b_in; reg [3:0] g_op; always @ (b_in) begin g_op[3] = b_in[3]; g_op[2] = b_in[3] ^ b_in[2]; g_op[1] = b_in[2] ^ b_in[1]; g_op[0] = b_in[1] ^ b_in[0]; end endmodule

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

7.
en

Demultiplexer 1 to 4

sel a_in

inputs 2

Demultiplexer 1 to 4

4 outputs

y_out

Figure 7: Block Diagram of Demultiplexer 1 to 4

Inputs Outputs en sel (1) sel (0) a_in y_out (3) y_out (2) y_out (1) y_out (0) 1 X X X Z Z Z Z 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 1 1 1 0 0 0

Truth Table 7: Demux 1 to 4 VHDL File Name: demux1to4.vhd -- Demux1to4 - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux1to4 is Port ( en sel a_in y_out end demux1to4;

: : : :

in STD_LOGIC; in STD_LOGIC_VECTOR(1 downto 0); in STD_LOGIC; out STD_LOGIC_VECTOR (3 downto 0));

architecture Behavioral of demux1to4 is begin process(en,sel,a_in) begin if(en /= '0') then -- Active Low Enabled y_out <= "ZZZZ"; else y_out <= "0000"; case sel is when "00" => y_out(0) <= a_in; when "01" => y_out(1) <= a_in; when "10" => y_out(2) <= a_in; when "11" => y_out(3) <= a_in; when others => y_out <= "ZZZZ"; end case; end if; end process; end Behavioral;

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Verilog File Name: demux1to4.v // Demultiplexer 1 to 4 module demux1to4(en,sel,a_in,y_out); input en; input [1:0] sel; input a_in; output [3:0] y_out; wire en; wire [1:0] sel; wire a_in; reg [3:0] y_out; always@(en,sel,a_in) begin if(en != 0) // Active Low Enabled y_out = 4'bZZZZ; else begin y_out = 4'b0000; case(sel) 2'b00 : y_out[0] = a_in; 2'b01 : y_out[1] = a_in; 2'b10 : y_out[2] = a_in; 2'b11 : y_out[3] = a_in; default : y_out = 4'bZZZZ; endcase end end endmodule

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

8.

4Bit Comparator
a_in 4 inputs 4 Comparator 4bit outputs g_op L_op e_op

b_in

Figure 8: Block Diagram of Comparator 4bit

Inputs a_in ---1100 0110 1000

Outputs a_in > b_in a_in = b_in a_in < b_in b_in g_op e_op L_op ---Z Z Z 0011 1 0 0 0110 0 1 0 1110 0 0 1 Truth Table 8: Comparator 4Bits

VHDL File Name: comparator4bit.vhd --Comparator4bit - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comparator4bit is Port ( a_in : in STD_LOGIC_VECTOR (3 downto 0); b_in : in STD_LOGIC_VECTOR (3 downto 0); g_op : out STD_LOGIC; e_op : out STD_LOGIC; L_op : out STD_LOGIC); end comparator4bit; architecture Behavioral of comparator4bit is begin process(a_in,b_in) begin if( a_in > b_in) then g_op <= '1'; e_op <= '0'; L_op <= '0'; elsif(a_in = b_in) then g_op <= '0'; e_op <= '1'; L_op <= '0'; elsif(a_in < b_in) then g_op <= '0'; e_op <= '0'; L_op <= '1';

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else g_op <= 'Z'; e_op <= 'Z'; L_op <= 'Z'; end if; end process; end Behavioral; Verilog File Name: comparator4bit.v // Comparator 4bit module comparator4bit( a_in,b_in,g_op,L_op,e_op); input [3:0] a_in,b_in; output g_op,L_op,e_op; wire [3:0] a_in,b_in; reg g_op,L_op,e_op; always@(a_in,b_in) if( a_in > b_in) begin g_op = 1; L_op = 0; e_op = 0; end else if( a_in < b_in) begin g_op = 0; L_op = 1; e_op = 0; end else if( a_in == b_in) begin g_op = 0; L_op = 0; e_op = 1; end else begin g_op = 1'bZ; L_op = 1'bZ; e_op = 1'bZ; end endmodule

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9.

Full Adder
a_in b_in c_in inputs Full Adder outputs carry Figure 9: Block Diagram of Full Adder
a_in b_in x1 S1 x2 sum

sum

a2 S3 a1 S2 c_in o1 carry

Logic Diagram of Full Adder

Inputs Outputs a_in b_in c_in sum carry 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Truth Table 9: Full Adder Full Adder Data Flow Description VHDL File Name: FullAdder_DF.vhd -- FullAdder_DF - Data_Flow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FullAdder_DF is Port ( a_in, b_in, c_in : in STD_LOGIC; sum, carry : out STD_LOGIC); end FullAdder_DF;
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architecture Data_Flow of FullAdder_DF is begin sum <= a_in xor b_in xor c_in; carry <= (a_in and b_in) or (b_in and c_in) or (a_in and c_in); end Data_Flow; Verilog File Name: FullAdder_DF.v // FullAdder - Data Flow Model module FullAdder_DF( a_in, b_in, c_in, sum, carry ); input a_in, b_in, c_in; output sum, carry; assign sum = a_in ^ b_in ^ c_in; assign carry = (a_in & b_in) | (b_in & c_in) | (c_in & a_in); endmodule Full Adder Behavioral Description VHDL File Name: FullAdder_Behav.vhd -- Full Adder - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FullAdder_Behav is Port ( a_in, b_in, c_in : in STD_LOGIC; sum, carry : out STD_LOGIC); end FullAdder_Behav; architecture Behavioral of FullAdder_Behav is begin process ( a_in, b_in, c_in) begin if(a_in='0' and b_in='0' and c_in = '0') then sum <= '0';carry <= '0'; elsif (( a_in='0' and b_in='0' and c_in = '1') or (a_in='0' and b_in='1' and c_in = '0') or (a_in='1' and b_in='0' and c_in = '0')) then sum <= '1';carry <= '0'; elsif (( a_in='0' and b_in='1' and c_in = '1') or (a_in='1' and b_in='0' and c_in = '1') or (a_in='1' and b_in='1' and c_in = '0')) then sum <= '0';carry <= '1'; elsif(a_in='1' and b_in='1' and c_in = '1') then sum <= '1';carry <= '1'; end if; end process; end Behavioral;

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Verilog File Name: FullAdder_Behav.v //FullAdder - Behavioral Model module FullAdder_Behav( a_in, b_in, c_in, sum, carry ); input a_in, b_in, c_in; output sum, carry; wire a_in, b_in, c_in; reg sum, carry; always @ ( a_in, b_in, c_in) begin if(a_in==0 & b_in==0 & c_in==0) begin sum = 0; carry = 0; end else if (( a_in==0 & b_in==0 & c_in == 1) | (a_in==0 & b_in==1 & c_in == 0) | (a_in==1 & b_in==0 & c_in == 0)) begin sum = 1; carry = 0; end else if (( a_in==0 & b_in==1 & c_in | (a_in==1 & b_in==0 & c_in | (a_in==1 & b_in==1 & c_in begin sum = 0; carry = 1; end else if(a_in==1 & b_in==1 & c_in == begin sum = 1; carry = 1; end end endmodule == 1) == 1) == 0))

1)

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Full Adder Structural Description VHDL File Name: full_adder_struct.vhd -- Full Adder - Structural library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full_adder is port ( a_in, b_in, c_in : in STD_LOGIC; sum,carry : out STD_LOGIC); end full_adder; architecture structural of full_adder is component xor2_1 port( a, b : in STD_LOGIC; y : out STD_LOGIC); end component; component and2_1 port( a, b : in STD_LOGIC; y : out STD_LOGIC); end component; component or2_1 port( a, b : in STD_LOGIC; y : out STD_LOGIC); end component; signal s1,s2,s3: STD_LOGIC; begin x1: xor2_1 port map (a_in, b_in, s1); a1: and2_1 port map (a_in, b_in, s2); x2: xor2_1 port map (s1, c_in, sum); a2: and2_1 port map (s1, c_in, s3); o1: or2_1 port map (s2, s3, carry); end structural; VHDL File Name: xor2_1.vhd -- xor2_1 - DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor2_1 is Port ( a,b : in STD_LOGIC; y : out STD_LOGIC); end xor2_1; architecture data_flow of xor2_1 is begin y <= a xor b; end data_flow;

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VHDL File Name: and2_1.vhd -- and2_1 - DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2_1 is port ( a, b : in STD_LOGIC; y : out STD_LOGIC); end and2_1; architecture data_flow of and2_1 is begin y <= a and b; end data_flow; VHDL File Name: or2_1.vhd -- or2_1 - DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or2_1 is Port ( a,b : in STD_LOGIC; y : out STD_LOGIC); end or2_1; architecture data_flow of or2_1 is begin y <= a or b; end data_flow; Verilog File Name: full_adder_struct.v //Full Adder - Structural module full_adder( a_in, b_in, c_in, sum, carry ); input a_in, b_in, c_in; output sum, carry; wire s1,s2,s3; //syntax: gate_operator lable (ouput, input, input); xor x1 (s1, a_in, b_in); and a1 (s2, a_in, b_in); xor x2 (sum, s1, c_in); and a2 (s3, s1, c_in); or o1 (carry, s2, s3); endmodule

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4TH SEM, HDL MANUAL, 10ESL48

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10.

ALU 32 Bits
en a_in 32 inputs b_in 32 ALU 32bits 32 outputs y_op

opc

4 Figure 10: Block Diagram of ALU 32bits

Inputs en 0 1 1 1 1 1 1 1 opc XXXX 0001 0010 0011 0100 0101 0110 0111 a_in
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Outputs b_in
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

y_op
ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ

Actions No Change a_in + b_in a_in - b_in not a_in a_in and b_in a_in or b_in
a_in nand b_in

01100000000000000111111111111111 01100000000000000111111111111111 01100000000000000111111111111111 01100000000000000111111111111111 01100000000000000111111111111111 01100000000000000111111111111111 01100000000000000111111111111111

01000000000000000111111110011001 01000000000000000111111110011001 01000000000000000111111110011001 01000000000000000111111110011001 01000000000000000111111110011001 01000000000000000111111110011001 01000000000000000111111110011001

10100000000000001111111110011000 00100000000000000000000001100110 10011111111111111000000000000000 01000000000000000111111110011001 01100000000000000111111111111111 10111111111111111000000001100110 00100000000000000000000001100110

a_in xor b_in

Truth Table 10: ALU 32bits VHDL File Name: alu32bit.vhd --ALU32bit Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity alu32bit is Port ( en : in BIT; opc : in STD_LOGIC_VECTOR (3 downto 0); a_in, b_in : in STD_LOGIC_VECTOR (31 downto 0); y_op : out STD_LOGIC_VECTOR (31 downto 0)); end alu32bit;

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4TH SEM, HDL MANUAL, 10ESL48

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architecture Behavioral of alu32bit is begin process(en, a_in, b_in, opc) begin if (en = '1') then -- Active High Enabled case opc is when "0001" => y_op <= a_in + b_in; when "0010" => y_op <= a_in - b_in; when "0011" => y_op <= not a_in; when "0100" => y_op <= a_in and b_in; when "0101" => y_op <= a_in or b_in; when "0110" => y_op <= a_in nand b_in; when "0111" => y_op <= a_in xor b_in; when others => null; end case; else y_op <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; end if; end process; end behavioral; Verilog File Name: alu32bit.v // ALU 32bit module alu32bit( en, opc, a_in, b_in, y_op ); input en; input [3:0] opc; input [31:0] a_in, b_in; output [31:0] y_op; wire en; wire [3:0] opc; wire [31:0] a_in, b_in; reg [31:0] y_op; always @ ( en, opc, a_in, b_in) if (en == 1) // Active High Enabled case (opc) 4'b0001 : y_op = a_in + b_in; 4'b0010 : y_op = a_in - b_in; 4'b0011 : y_op = ~ a_in; 4'b0100 : y_op = a_in & b_in; 4'b0101 : y_op = a_in | b_in; 4'b0110 : y_op = ~ (a_in & b_in); 4'b0111 : y_op = a_in ^ b_in; default null; endcase else y_op = 32'bZ; endmodule

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

11.

S R Flip Flop
s q r inputs rst SR Flip Flop outputs qb

clk Figure 11: Block Diagram of SR Flip Flop

Inputs Outputs rst clk s r q qb Action 1 0 0 0

Illegal 0 1 1 - Truth Table 11: S R Flip Flop VHDL File Name: sr_ff.vhd -- S R Flip Flop library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sr_ff is Port ( s,r,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end sr_ff; architecture Behavioral of sr_ff is signal temp : std_logic := '0'; begin process(clk,rst) begin if(rst = '1') then temp <= '0';

X X q qb No Change 0 0 q qb No Change 0 1 0 1 0 1 1 0 Reset Set

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4TH SEM, HDL MANUAL, 10ESL48

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elsif (clk'event and clk = '1') then if(s = '0' and r ='0') then temp <= temp; elsif(s = '0' and r ='1') then temp <= '0'; elsif(s = '1' and r ='0') then temp <= '1'; elsif(s = '1' and r ='1') then temp <= 'X'; end if; end if; end process; q <= temp; qb <= not temp; end Behavioral;

Verilog File Name: sr_ff.v //Async SR Flip Flop module sr_ff( sr , clk , reset , q ,qb ); input [1:0] sr; input clk, reset ; output q,qb; reg q,qb; always @ ( posedge clk or if (reset) begin q = 1'b0; qb = ~q; end else begin case (sr) 2'd0 : q = 2'd1 : q = 2'd2 : q = 2'd3 : q = endcase qb = ~q; end endmodule posedge reset)

q; 1'b0; 1'b1; 1'bX;

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

12.

J K Flip Flop
j q k inputs rst JK Flip Flop outputs qb

clk Figure 12: Block Diagram of JK Flip Flop

Inputs rst clk j 1 X 0 0 0 0 0 1 0 1 Truth Table

k q X q 0 q 1 0 0 1 1 q' 12: J

Outputs qb Action qb No Change qb No Change Reset 1 Set 0 Toggle q' K Flip Flop

VHDL File Name: jk_ff.vhd --JK Flip Flop library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jk_ff is Port ( j,k,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end jk_ff; architecture Behavioral of jk_ff is signal temp : std_logic := '0'; begin process(clk,rst) begin if(rst = '1') then temp <= '0'; elsif(clk'event and clk = '1') then if(j = '0' and k ='0') then temp <= temp; elsif(j = '0' and k ='1') then temp <= '0'; elsif(j = '1' and k ='0') then temp <= '1'; elsif(j = '1' and k ='1') then temp <= not temp; end if; end if; end process; q <= temp; qb <= not temp; end Behavioral;
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Verilog File Name: jk_ff.v //Async JK Flip Flop module jk_ff( jk , clk , reset , q ,qb ); input [1:0] jk; input clk, reset ; output q,qb; reg q,qb; always @ ( posedge clk or if (reset) begin q = 1'b0; qb = ~q; end else begin case (jk) 2'd0 : q = 2'd1 : q = 2'd2 : q = 2'd3 : q = endcase qb = ~q; end endmodule posedge reset)

q; 1'b0; 1'b1; ~q;

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

13.

D Flip Flop

d inputs rst D Flip Flop outputs

qb

clk Figure 13: Block Diagram of D Flip Flop

Inputs Outputs rst clk d q qb Action 1 X q qb No Change Reset 0 0 0 1 Set 0 1 1 0 Truth Table 13: D Flip Flop VHDL File Name: d_ff.vhd -- D Flip Flop library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity d_ff is Port ( d,clk,rst : in STD_LOGIC; q,qb : out STD_LOGIC); end d_ff; architecture Behavioral of d_ff is signal temp : std_logic := '0'; begin process(clk,rst) begin if(rst = '1') then temp <= '0'; elsif(clk'event and clk = '1') then temp <= d; end if; end process; q <= temp; qb <= not temp; end Behavioral;

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Verilog File Name: d_ff.v //Async D Flip Flop module d_ff( d , clk , reset , q ,qb ); input d, clk, reset ; output q,qb; reg q,qb; always @ ( posedge clk or posedge reset) if (reset) begin q = 1'b0; qb=~q; end else begin q = d; qb=~q; end endmodule

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

14.

T Flip Flop
t inputs rst T Flip Flop outputs qb q

clk Figure 14: Block Diagram of T Flip Flop

Outputs q qb Action 1 X q qb No Change 0 0 q qb No Change Toggle 0 1 q' q' Truth Table 14: T Flip Flop VHDL File Name: t_ff.vhd --T Flip Flop library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity t_ff is Port ( t,clk,rst : in STD_LOGIC; q,qb : out STD_LOGIC); end t_ff; architecture Behavioral of t_ff is signal temp : std_logic := '0'; begin process(clk,rst) begin if(rst = '1') then temp <= '0'; elsif(clk'event and clk = '1' and t = '1') then temp <= not temp; end if; end process; q <= temp; qb <= not temp; end Behavioral;

Inputs rst clk t

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Verilog File Name: t_ff.v //Async T Flip Flop module t_ff( t, clk, reset, q, qb ); input t, clk, reset ; output q,qb; reg q,qb; always @ ( posedge clk or posedge reset) if (reset) begin q = 1'b0; qb=~q; end else if (t) begin q = ~q; qb = ~q; end endmodule

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

15.

Binary Synchronous Reset 4bit Counter

rst inputs

Binary Synchronous Reset 4bit Counter

4 outputs

bin_out

clk Figure 15: Block Diagram of Binary Synchronous Reset 4bit Counter

VHDL File Name: bin_counter_sync_4bit.vhd -- Binary Synchronous reset 4bit counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bin_counter_sync_4bit is Port ( clk,rst : in STD_LOGIC; bin_out : out STD_LOGIC_VECTOR (3 downto 0)); end bin_counter_sync_4bit; architecture Behavioral of bin_counter_sync_4bit is signal temp: std_logic_vector(3 downto 0); begin process(clk) begin if ( clk'event and clk='1') then if(rst = '1') then temp <= "0000"; else temp <= temp+'1'; end if; end if; end process; bin_out <= temp ; end Behavioral; Verilog File Name: bin_counter_sync_4bit.v // Binary synchronous reset 4bit counter module bin_sync_4bit ( rst, clk, count); input rst,clk; output [3:0] count; reg [3:0] count; initial begin count = 4'b0000; end always @(posedge clk) if(rst) count = 4'b0000; else count = count + 4'b0001; endmodule
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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

16.

Binary Asynchronous Reset 4bit Counter

rst inputs

Binary Asynchronous Reset 4bit Counter

4 outputs

bin_out

clk Figure 16: Block Diagram of Binary Asynchronous Reset 4bit Counter

VHDL File Name: bin_counter_async_4bit.vhd --Binary Asynchronous reset 4bit counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bin_counter_async_4bit is Port ( clk,rst : in STD_LOGIC; bin_out : out STD_LOGIC_VECTOR (3 downto 0)); end bin_counter_async_4bit; architecture Behavioral of bin_counter_async_4bit is signal temp: std_logic_vector(3 downto 0); begin process(clk,rst) begin if(rst = '1') then temp <= "0000"; elsif ( clk'event and clk='1') then temp <= temp+'1'; end if; end process; bin_out <= temp ; end Behavioral;

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Verilog File Name: bin_counter_async_4bit.v // Binary asynchronous reset 4bit counter module bin_async_4bit ( rst, clk, count); input rst,clk; output [3:0] count; reg [3:0] count; initial begin count = 4'b0000; end always @(posedge clk or posedge rst) if(rst) count = 4'b0000; else count = count + 4'b0001; endmodule

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

17.

BCD Synchronous Reset 4bit Counter

rst inputs

BCD Synchronous Reset 4bit Counter

4 outputs

bcd_out

clk Figure 17: Block Diagram of BCD Synchronous Reset 4bit Counter

VHDL File Name: bcd_counter_sync_4bit.vhd --BCD Synchronous reset 4bit counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcd_counter_sync is Port ( clk,rst : in STD_LOGIC; bcd_out : out STD_LOGIC_VECTOR (3 downto 0)); end bcd_counter_sync; architecture Behavioral of bcd_counter_sync is signal temp: std_logic_vector(3 downto 0); begin process(clk) begin if ( clk'event and clk='1') then if(rst = '1' or temp = "1001") then temp <= "0000"; else temp <= temp+'1'; end if; end if; end process; bcd_out <= temp ; end Behavioral;

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Verilog File Name: bcd_counter_sync_4bit.v // BCD synchronous reset 4bit counter module bcd_sync ( rst, clk, count); input rst,clk; output [3:0] count; reg [3:0] count; initial begin count = 4'd0; end always @(posedge clk) if(rst) count = 4'd0; else if(count < 4'd9 ) count = count + 4'd1; else count = 4'd0; endmodule

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

18.

BCD Asynchronous Reset 4bit Counter

rst inputs

BCD Asynchronous Reset 4bit Counter

4 outputs

bcd_out

clk Figure 18: Block Diagram of BCD Asynchronous Reset 4bit Counter

VHDL File Name: bcd_counter_async_4bit.vhd -- BCD asynchronous reset 4bit counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcd_counter_async is Port ( clk,rst : in STD_LOGIC; bcd_out : out STD_LOGIC_VECTOR (3 downto 0)); end bcd_counter_async; architecture Behavioral of bcd_counter_async is signal temp: std_logic_vector(3 downto 0):= "0000"; begin process(clk,rst) begin if(rst = '1' or temp = "1010") then temp <= "0000"; elsif ( clk'event and clk='1') then temp <= temp+'1'; end if; end process; bcd_out <= temp ; end Behavioral;

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Verilog File Name: bcd_counter_async_4bit.v // BCD asynchronous reset 4bit counter module bcd_async ( rst, clk, count); input rst,clk; output [3:0] count; reg [3:0] count; initial begin count = 4'd0; end always @(posedge clk or posedge rst) if(rst) count = 4'd0; else if(count < 4'd9 ) count = count + 4'd1; else count = 4'd0; endmodule

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

19.

Binary Any Sequence up down

4 Binary Any Sequence 4bit Counter inputs rst clk

4bit Counter

d_in load updown

4 outputs

bin_out

Figure 19: Block Diagram of Binary Any Sequence 4bit Counter

VHDL File Name: bin_counter_any_seq_4bit.vhd -- Binary Any Sequence up down 4bit counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bin_counter_any_seq is Port ( clk,rst,load,updown : in STD_LOGIC; d_in :in STD_LOGIC_VECTOR( 3 downto 0); bin_out : out STD_LOGIC_VECTOR (3 downto 0)); end bin_counter_any_seq; architecture Behavioral of bin_counter_any_seq is signal temp: std_logic_vector(3 downto 0):= "0000"; begin process(clk, rst) begin if(rst = '1') then temp <= "0000"; elsif(load = '1') then temp <= d_in; elsif ( clk'event and clk='1' and load = '0') then if ( updown = '1') then temp <= temp+'1'; else temp <= temp-'1'; end if; end if; end process; bin_out <= temp ; end Behavioral;

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Verilog File Name: bin_counter_any_seq_4bit.v // Binary Any Sequence Up Down Counter module any_seq_bin ( rst,load, clk,din,updown, count); input rst,clk,updown,load; input [3:0] din; output [3:0] count; reg [3:0] count; always @(posedge clk) if(rst) count = 4'b0000; else if(load) count = din; else if (updown) count = count + 4'b0001; else count = count - 4'b0001; endmodule

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4TH SEM, HDL MANUAL, 10ESL48

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E&C DEPT., CEC, BANGALORE

1.

7 Segment to Accept Hex Keypad

7 Segment

PC

JTAG

(Comman Cathode)

Power Supply

CPLD XC9572

J6

BUS/STRIP CABLE

J2

0 4 8 C

1 5 9 D

2 6 A E

3 7 B F

Keypad

CPLD Board

Mega KBDSP1

Figure 1: Interface Diagram of CPLD Board and MEGA KBDSP1

key_rl

4 inputs

key_sc digit seg_out

clk

7 Segment Display to accept Hex Keypad Input Data

outputs 6 7

Figure 2: Block diagram of 7Segment Display to accept Hex Keypad Input Data

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

VHDL File Name: keypad_led_display.vhd --keypad_led_display.vhd -- keypad_led_display - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity keypad_led_display is Port ( clk : in STD_LOGIC; key_rl : in BIT_VECTOR (3 downto 0); key_sc : out BIT_VECTOR (3 downto 0); digit : out STD_LOGIC_VECTOR (5 downto 0); seg_out : out STD_LOGIC_VECTOR (6 downto 0)); end keypad_led_display; architecture Behavioral of keypad_led_display is signal clk_div:std_logic_vector(12 downto 0); signal key_sc_temp :bit_vector(3 downto 0):="0001"; begin digit <= "111110"; --active low enable process(clk) begin if(clk'event and clk = '1') then clk_div <= clk_div + '1'; end if; end process; process(clk_div(12)) begin if (clk_div(12)'event and clk_div(12) = '1') then key_sc_temp <= key_sc_temp rol 1; end if; key_sc <= key_sc_temp; end process;
PART-B: INTERFACING 42

-- 2 msec delay, 4Mhz clock source / 8 KHz = 500Hz

-- ( = 2 msec) -- 2 ^ 13 = 8KHz, 12 downto 0

SKLN,RCVK

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

process(key_rl,clk_div(12)) begin if (clk_div(12)'event and clk_div(12) = '1') then if (key_sc_temp="0001" and key_rl="0001") elsif (key_sc_temp="0001" and key_rl="0010") elsif (key_sc_temp="0001" and key_rl="0100") elsif (key_sc_temp="0001" and key_rl="1000") elsif (key_sc_temp="0010" and key_rl="0001") elsif (key_sc_temp="0010" and key_rl="0010") elsif (key_sc_temp="0010" and key_rl="0100") elsif (key_sc_temp="0010" and key_rl="1000") elsif (key_sc_temp="0100" and key_rl="0001") elsif (key_sc_temp="0100" and key_rl="0010") elsif (key_sc_temp="0100" and key_rl="0100") elsif (key_sc_temp="0100" and key_rl="1000") elsif (key_sc_temp="1000" and key_rl="0001") elsif (key_sc_temp="1000" and key_rl="0010") elsif (key_sc_temp="1000" and key_rl="0100") elsif (key_sc_temp="1000" and key_rl="1000") end if; end if; end process; end Behavioral;

then then then then then then then then then then then then then then then then

seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out

--gfedcba <= "0111111"; <= "0000110"; <= "1011011"; <= "1001111"; <= "1100110"; <= "1101101"; <= "1111101"; <= "0000111"; <= "1111111"; <= "1101111"; <= "1110111"; <= "1111100"; <= "0111001"; <= "1011110"; <= "1111001"; <= "1110001";

--0 --1 --2 --3 --4 --5 --6 --7 --8 --9 --A --b --C --D --E --F

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

UCF File Name: keypad_led_display.ucf #keypad_led_display.ucf NET "clk" LOC = NET "digit<0>" LOC = NET "digit<1>" LOC = NET "digit<2>" LOC = NET "digit<3>" LOC = NET "digit<4>" LOC = NET "digit<5>" LOC = NET "key_rl<0>" LOC = NET "key_rl<1>" LOC = NET "key_rl<2>" LOC = NET "key_rl<3>" LOC = NET "key_sc<0>" LOC = NET "key_sc<1>" LOC = NET "key_sc<2>" LOC = NET "key_sc<3>" LOC = NET "seg_out<0>" LOC = NET "seg_out<1>" LOC = NET "seg_out<2>" LOC = NET "seg_out<3>" LOC = NET "seg_out<4>" LOC = NET "seg_out<5>" LOC = NET "seg_out<6>" LOC =

"p9" "p68" "p67" "p66" "p65" "p63" "p62" "p1" "p84" "p83" "p82" "p5" "p4" "p3" "p2" "p81" "p80" "p79" "p75" "p72" "p71" "p70"

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

PART-B: INTERFACING

44

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

2.

LCD Message Display

LCD Display

ELECTRONICS
PC
JTAG Power Supply

CPLD J6 XC9572

BUS/STRIP CABLE

J2

0 4 8 C

1 5 9 D

2 6 A E

3 7 B F

Keypad

CPLD Board

Mega KBDSP1
8

Figure 3: Interface Diagram of CPLD Board and MEGA KBDSP1

data reg_sel rd_wr en

input clk

outputs

LCD

Figure 4: Block Diagram of LCD

PART-B: INTERFACING 45 SKLN,RCVK

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

VHDL File Name: lcd_message.vhd -- lcd_message.vhd -- LCD_message Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity lcd_message is Port ( clk : in std_logic; data : out std_logic_vector(7 downto 0); reg_sel : out std_logic; rd_wr : out std_logic; en : out std_logic); end lcd_message; architecture Behavioral of lcd_message is signal clkdiv : std_logic_vector(21 downto 0); signal dispclk : std_logic; begin process(clk) begin if( rising_edge(clk)) then clkdiv <= clkdiv + 1; end if; dispclk <= clkdiv(15); en <= clkdiv(15); end process; process(dispclk) variable a : integer range 0 to 14:=0 ; type lcd_type is array (natural range <>) of std_logic_vector ( 7 downto 0); constant lcd_data : lcd_type( 0 to 14):=("00111000","00001110","00000110","00000001", "01000101","01001100","01000101","01000011","01010100","01010010","01001111","01001110", "01001001","01000011","01010011");

PART-B: INTERFACING

46

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

begin rd_wr <= '0'; if(rising_edge(dispclk))then if(a < 4) then reg_sel <= '0'; else reg_sel <= '1'; end if; data <= lcd_data(a); a := a + 1; if( a = 15) then a := 3; end if; end if; end process; end Behavioral; UCF File Name: LCD_message.ucf #LCD_message.ucf NET "clk" LOC = "p9" ; NET "data<0>" LOC = "p81" ; NET "data<1>" LOC = "p80" ; NET "data<2>" LOC = "p79" ; NET "data<3>" LOC = "p75" ; NET "data<4>" LOC = "p72" ; NET "data<5>" LOC = "p71" ; NET "data<6>" LOC = "p70" ; NET "data<7>" LOC = "p69" ; NET "en" LOC = "p66" ; NET "rd_wr" LOC = "p67" ; NET "reg_sel" LOC = "p68" ;

PART-B: INTERFACING

47

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4TH SEM, HDL MANUAL, 10ESL48

2012
KEY 1 Direction Control

E&C DEPT., CEC, BANGALORE

3.

Stepper Motor Speed and Direction Control

J4
PC
JTAG

To Stepper Motor

Power Supply

CPLD J6 XC9572

BUS/STRIP CABLE

J3

KEY1

KEY2

KEY3

KEY4

RELAY1

RELAY2

CPLD Board

Stepper/DC Motor Interface Card

Figure 5: Interface Diagram of CPLD Board and Stepper Motor Interface Card

KEY

C_A inputs

Direction Control

STEPPER MOTOR

4 outputs

d_out

clk_4M

Figure 6: Block Diagram of Stepper Motor

PART-B: INTERFACING

48

SKLN,RCVK

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

VHDL File Name: stepper_motor.vhd --stepper_motor.vhd -- stepper_motor Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity stepper_motor is Port ( d_out : out std_logic_vector(3 downto 0); C_A : in std_logic; clk_4M: in std_logic); end stepper_motor; architecture Behavioral of stepper_motor is signal clk_div: std_logic_vector ( 21 downto 0 ); signal clk_Hz: std_logic; type step_type is array (natural range <>) of std_logic_vector ( 3 downto 0); constant step_aclk : step_type( 0 to 3):=("0110","1010","1001","0101"); constant step_clk : step_type( 0 to 3):=("0101","1001","1010","0110"); begin process(clk_4M) begin if rising_edge(clk_4M) then clk_div <= clk_div + 1; end if; clk_Hz <= clk_div(18); end process; process(clk_Hz) variable a : integer range 0 to 3:=0; begin

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

if rising_edge(clk_Hz) then if (C_A = '1') then d_out <= step_clk(a); else d_out <= step_aclk(a); end if; a := a + 1; end if; end process; end Behavioral; UCF File Name: stepper_motor.ucf #stepper_motor.ucf NET "C_A" LOC = "p79" ; NET "clk_4M" LOC = "p9" ; NET "d_out<0>" LOC = "p3" ; NET "d_out<1>" LOC = "p2" ; NET "d_out<2>" LOC = "p1" ; NET "d_out<3>" LOC = "p84" ;

PART-B: INTERFACING

50

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

4.

DC Motor Speed and Direction Control

PC

JTAG

Power Supply

CPLD J6 XC9572

BUS/STRIP CABLE

J3

KEY1

KEY2

KEY3

KEY4

RELAY1

RELAY2

J5 CPLD Board Stepper/DC Motor Interface Card

To DC Motor

Figure 7: Interface Diagram of CPLD Board and DC Motor Interface Card

spd_cnt

4 inputs

cl

DC MOTOR

outputs acl

clk

Figure 8: Block Diagram of DC Motor

PART-B: INTERFACING 51 SKLN,RCVK

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

VHDL File Name: dcmotor.vhd -- dcmotor.vhd -- DC motor Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dcmotor is Port ( clk : spd_cnt : cl : acl : end dcmotor;

in STD_LOGIC; in STD_LOGIC_vector(3 downto 0); out STD_LOGIC; out STD_LOGIC);

architecture Behavioral of dcmotor is signal clk_div : std_logic_vector(21 downto 0); begin process(clk) begin if(rising_edge(clk)) then clk_div <= clk_div + '1' ; end if; end process;

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52

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

process(clk_div(19)) begin case (spd_cnt) is when "0001" => cl <= clk_div(19) and clk_div(15); acl <= '0'; when "0010" => cl <= clk_div(19) and clk_div(16); acl <= '0'; when "0100" => cl <= clk_div(19) and clk_div(18); acl <= '0'; when "1000" => cl <= '1'; acl <= '0'; when "0000" => cl <= '0'; acl <= '1'; when others => null; end case; end process; end Behavioral; UCF File Name: DCmotor.ucf #DCmotor.ucf NET "clk" LOC = "p9" ; NET "spd_cnt<0>" LOC = "p79" ; NET "spd_cnt<1>" LOC = "p75" ; NET "spd_cnt<2>" LOC = "p72" ; NET "spd_cnt<3>" LOC = "p71" ; NET "cl" LOC = "p5" ; NET "acl" LOC = "p4" ;

PART-B: INTERFACING

53

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

5.

External Lights Switching using Relay

PC

JTAG

Power Supply

CPLD XC9572

J6

BUS/STRIP CABLE

J2

RELAY3

RELAY1

RELAY4

RELAY2

CPLD Board

DAC/Relay Interface Card

Figure 9: Interface Diagram of CPLD Board and Relay Interface Card

Relay Interface

4 outputs

relay_out

Figure 10: Block Diagram of Relay Interface

PART-B: INTERFACING 54 SKLN,RCVK

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

VHDL File Name: relay_drive.vhd -- relay_drive.vhd -- relay_drive DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity relay_drive is Port ( relay_out : out STD_LOGIC_vector(3 downto 0)); end relay_drive; architecture DataFlow of relay_drive is begin relay_out(0) <= '0'; --relay1 device(led) relay_out(1) <= '1'; --relay2 device(led) relay_out(2) <= '1'; --relay3 device(led) relay_out(3) <= '0'; --relay4 device(led) end DataFlow; UCF File Name: relay_drive.ucf #relay_drive.ucf NET "relay_out<0>" LOC = "p5" ; NET "relay_out<1>" LOC = "p4" ; NET "relay_out<2>" LOC = "p3" ; NET "relay_out<3>" LOC = "p2" ;

is is is is

off on on off

PART-B: INTERFACING

55

SKLN,RCVK

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

6.

Signal Generator Using DAC

J5
To CRO

PC

JTAG

Power Supply

CPLD J6 XC9572

BUS/STRIP CABLE

J2

RELAY3

RELAY1

RELAY4

RELAY2

CPLD Board

DAC/Relay Interface Card

Figure 11: Interface Diagram of CPLD Board and DAC Interface Card

rst inputs clk

Signal Generator using DAC

8 outputs

dac_out

Figure 12: Block Diagram of Sine/Triangular/Square/Ramp Wave Generator using DAC The DAC interface consists of 8 bit Digital to Analog Converter (DAC 0800). The outputs of which are converted to Voltages using OPAMP (LM324). The Voltage Outputs terminated at J6 (Vout) and corresponding 4mA-20mA at J7 Connector
PART-B: INTERFACING 56 SKLN,RCVK

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

VHDL File Name: DAC_Sine.vhd -- DAC_Sine.vhd -- DAC_Sine Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DAC_Sine is Port ( clk : in STD_LOGIC; -- 4MHz XTL_CLK rst : in STD_LOGIC; dac_out : out STD_LOGIC_VECTOR ( 7 downto 0 )); end DAC_Sine;

architecture Behavioral of DAC_Sine is signal c1 : std_logic_vector (3 downto 0); signal i : integer range 31 downto 0; type sine is array (0 to 31) of integer range 0 to 255; constant value : sine := ( 128, 146, 164, 182, 200, 218,236, 246, 255, 246, 236, 218,200, 182, 164, 146, 128, 110, 92, 74, 56, 38, 20, 06, 00,06, 20, 38, 56, 74, 92, 110); begin (=2,4,6,) degree of sine using the equation process (clk, rst) V=5V +5V Sin begin Eg: =0 if(rst='1') then c1 <=(others => '0'); +5V Sin = 5V 1. V=5V elsif (clk'event and clk = '1') then 2. Resolution of the DAC: 8-bit (2pow8=256) Steps c1 <= c1 + 4; end if; V:10V(p.p) Full Scale Voltages end process; So, 256 Steps/10V = 25.6 Steps per Volt.
The Value Sent to DAC is (25.6 * 5)V=128.

PART-B: INTERFACING

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

process (c1(3)) begin if rising_edge (c1(3)) then dac_out <= conv_std_logic_vector ( value (i), 8 ); i <= i + 1; if (i = 31) then i <= 0; end if; end if; end process; end Behavioral; UCF File Name: DAC_Sine.ucf #DAC_Sine.ucf NET "clk" LOC = "p9" NET "rst" LOC = "p12" NET "dac_out<0>" LOC = "p81" NET "dac_out<1>" LOC = "p80" NET "dac_out<2>" LOC = "p79" NET "dac_out<3>" LOC = "p75" NET "dac_out<4>" LOC = "p72" NET "dac_out<5>" LOC = "p71" NET "dac_out<6>" LOC = "p70" NET "dac_out<7>" LOC = "p69"

; ; ; ; ; ; ; ; ; ;

PART-B: INTERFACING

58

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

VHDL File Name: DAC_Square.vhd -- DAC_Square.vhd -- DAC_Square Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DAC_Square is Port ( clk : in STD_LOGIC; -- 4MHz XTL_CLK rst : in STD_LOGIC; dac_out : out STD_LOGIC_VECTOR ( 7 downto 0 )); end DAC_Square; architecture Behavioral of DAC_Square is signal count : std_logic_vector (7 downto 0); begin process (clk, rst, count) begin if(rst='1') then count <=(others => '0'); elsif (clk'event and clk = '1') then count <= count + 1; end if; if (count(7) = '1') then dac_out <= "11111111"; else dac_out <= "00000000"; end if; end process; end Behavioral;

PART-B: INTERFACING

59

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

UCF File Name: DAC_Square.ucf #DAC_Square.ucf NET "clk" LOC = "p9" NET "rst" LOC = "p12" NET "dac_out<0>" LOC = "p81" NET "dac_out<1>" LOC = "p80" NET "dac_out<2>" LOC = "p79" NET "dac_out<3>" LOC = "p75" NET "dac_out<4>" LOC = "p72" NET "dac_out<5>" LOC = "p71" NET "dac_out<6>" LOC = "p70" NET "dac_out<7>" LOC = "p69"

; ; ; ; ; ; ; ; ; ;

PART-B: INTERFACING

60

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

VHDL File Name: DAC_Triangular.vhd -- DAC_Triangular.vhd -- DAC_Triangular Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DAC_Triangular is Port ( clk : in STD_LOGIC; -- 4MHz XTL_CLK rst : in STD_LOGIC; dac_out : out STD_LOGIC_VECTOR ( 7 downto 0 )); end DAC_Triangular; architecture Behavioral of DAC_Triangular is signal count : std_logic_vector (7 downto 0); signal ud : std_logic := '0'; begin process (clk, rst) begin if(rst='1') then count <=(others => '0'); elsif (clk'event and clk = '1') then if (ud='0') then count <= count + 1; elsif (ud='1') then count <= count - 1; end if; end if; end process; dac_out <= count; -- Output the count value
PART-B: INTERFACING 61

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

process (clk) begin if (clk'event and clk = '1') then if (count = "11111110") then ud <= '1'; elsif (count = "00000001") then ud <= '0'; end if; end if; end process; end Behavioral; UCF File Name: DAC_Triangular.ucf #DAC_Triangular.ucf NET "clk" LOC = "p9" ; NET "rst" LOC = "p12" ; NET "dac_out<0>" LOC = "p81" ; NET "dac_out<1>" LOC = "p80" ; NET "dac_out<2>" LOC = "p79" ; NET "dac_out<3>" LOC = "p75" ; NET "dac_out<4>" LOC = "p72" ; NET "dac_out<5>" LOC = "p71" ; NET "dac_out<6>" LOC = "p70" ; NET "dac_out<7>" LOC = "p69" ;

PART-B: INTERFACING

62

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

VHDL File Name: DAC_Pos_Ramp.vhd -- DAC_Pos_Ramp.vhd -- DAC_Pos_Ramp - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DAC_Pos_Ramp is Port ( clk : in STD_LOGIC; -- 4MHz XTL_CLK rst : in STD_LOGIC; dac_out : out STD_LOGIC_VECTOR ( 7 downto 0 )); end DAC_Pos_Ramp; architecture Behavioral of DAC_Pos_Ramp is signal count : std_logic_vector (7 downto 0); begin process (clk, rst, count) begin if(rst='1') then count <=(others => '0'); elsif (clk'event and clk = '1') then count <= count + 1; end if; end process; dac_out <= count; end Behavioral;

PART-B: INTERFACING

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

UCF File Name: DAC_Pos_Ramp.ucf #DAC_Pos_Ramp.ucf NET "clk" LOC = "p9" ; NET "rst" LOC = "p12" ; NET "dac_out<0>" LOC = "p81" ; NET "dac_out<1>" LOC = "p80" ; NET "dac_out<2>" LOC = "p79" ; NET "dac_out<3>" LOC = "p75" ; NET "dac_out<4>" LOC = "p72" ; NET "dac_out<5>" LOC = "p71" ; NET "dac_out<6>" LOC = "p70" ; NET "dac_out<7>" LOC = "p69" ;

PART-B: INTERFACING

64

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

VHDL File Name: DAC_Neg_Ramp.vhd -- DAC_Neg_Ramp.vhd -- DAC_Neg_Ramp Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DAC_Neg_Ramp is Port ( clk : in STD_LOGIC; -- 4MHz XTL_CLK rst : in STD_LOGIC; dac_out : out STD_LOGIC_VECTOR ( 7 downto 0 )); end DAC_Neg_Ramp; architecture Behavioral of DAC_Neg_Ramp is signal count : std_logic_vector (7 downto 0); begin process (clk, rst, count) begin if(rst='1') then count <=(others => '0'); elsif (clk'event and clk = '1') then count <= count - 1; end if; end process; dac_out <= count; end Behavioral;

PART-B: INTERFACING

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4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

UCF File Name: DAC_Neg_Ramp.ucf #DAC_Neg_Ramp.ucf NET "clk" LOC = "p9" ; NET "rst" LOC = "p12" ; NET "dac_out<0>" LOC = "p81" ; NET "dac_out<1>" LOC = "p80" ; NET "dac_out<2>" LOC = "p79" ; NET "dac_out<3>" LOC = "p75" ; NET "dac_out<4>" LOC = "p72" ; NET "dac_out<5>" LOC = "p71" ; NET "dac_out<6>" LOC = "p70" ; NET "dac_out<7>" LOC = "p69" ;

PART-B: INTERFACING

66

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