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Pipeline Eng

This document describes a computer organization project to design and implement a pipelined processor. Students have the option of either a pipelined processor without considering data hazards or one that does consider data hazards. The score for the second option is 150% of the first. The document provides initialization information for the program counter, instruction memory, register file, and data memory. It also provides expected output results for the register file and data memory for each option. Requirements for the project include demonstrating the final project, including an architecture explanation, waveforms, and a 200 word feedback section in the report.

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Paul Quiachon
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46 views2 pages

Pipeline Eng

This document describes a computer organization project to design and implement a pipelined processor. Students have the option of either a pipelined processor without considering data hazards or one that does consider data hazards. The score for the second option is 150% of the first. The document provides initialization information for the program counter, instruction memory, register file, and data memory. It also provides expected output results for the register file and data memory for each option. Requirements for the project include demonstrating the final project, including an architecture explanation, waveforms, and a 200 word feedback section in the report.

Uploaded by

Paul Quiachon
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Computer Organization Project 5

Pipelined Processor
Deadline: 1/17 to EC615

︰
Introduction︰
Design and implement a pipelined processor , with single-cycle processor in former projects. And
you may add other necessary units. (ex: pipeline register)
In this project, you have two options:
1. pipelined processor without considering data hazard
2. pipelined processor with considering data hazard
You just choose one to do it, and the score of 2 is 150% of the score of 1.

︰
Initialization︰
PC (Program Counter)︰
Value︰0
Instruction memory︰
Size︰8 * 32 (8 32-bit words)
Value︰
Option 1
Address Content
0 01000000 00000001 00000000 00000000 (LOAD M1 R0)
1 01000000 00000110 00000001 00000000 (LOAD M6 R1)
2 01000000 00000100 00000010 00000000 (LOAD M4 R2)
3 00000010 00000000 00000011 00000101 (SL R0 R3 5)
4 00000001 00000001 00000001 00000010 (SR R1 R1 2)
5 00001000 00000010 00000010 00000010 (ADD R2 R2 R2)
6 00100000 00000010 00000011 00000000 (STORE M2 R3)
7 00100000 00000111 00000001 00000000 (STORE M7 R1)
Option 2
Address Content
0 01000000 00000001 00000000 00000000 (LOAD M1 R0)
1 01000000 00000110 00000001 00000000 (LOAD M6 R1)
2 00001000 00000000 00000001 00000010 (ADD R0 R1 R2)
3 00000010 00000010 00000011 00000101 (SL R2 R3 5)
4 00000100 00000011 00000001 00000001 (SUB R3 R1 R1)
5 00000001 00000000 00000010 00000010 (SR R0 R2 2)
6 00100000 00000011 00000010 00000000 (STORE M3 R2)
7 00100000 00000101 00000001 00000000 (STORE M5 R1)
Register file︰
Size︰4 * 32 (4 32-bit registers)
Value︰all is 0

Data memory︰
Size︰8 * 32 (8 32-bit words)
Value︰0, 1, 2, 3, 4, 5, 6, 7 in order

︰
Result︰
Option 1
Register file︰
R0 R1 R2 R3
1 1 8 32

Data memory︰
M0 M1 M2 M3 M4 M5 M6 M7
0 1 32 3 4 5 6 1

Option 2
Register file︰
R0 R1 R2 R3
1 218 0 224

Data memory︰
M0 M1 M2 M3 M4 M5 M6 M7
0 1 2 0 4 218 6 7

︰
Requirement︰
1. No limitation for developing environment. Just to make sure that you can demo the final project
(lab 5) in your environment.
2. Need to demo this project.
3. Please attach items below in your report (Code not required)
(1) Architecture (explain functions for each unit)
(2) Waveforms (just run instructions in instruction memory, and comment what is done in each
cycle)
(3) Feedback and what you learned (about 200 words)

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