A MATLAB TO VHDL CONVERSION TOOLBOX FOR DIGITAL CONTROL

I.A. Grout and K. Keane

Department of Electronic and Computer Engineering,

University of Limerick, Limerick, Ireland

Abstract: This paper will describe the development of a prototype software toolbox
that can analyze and process a Simulink block diagram model in order to produce a
VHDL representation of the model. The derived VHDL model will consist of a
combination of behavioural, RTL and structural definitions mapped directly from the
Simulink model. This approach may enable a user to develop and simulate a digital
control algorithm using Matlab and once complete, convert this to VHDL code. This
would then be synthesized into digital logic hardware for implementation on devices
such as FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific
Integrated Circuits). Copyright 2000 ? IFAC

Keywords: Closed-loop controllers, Computer-aided control system design,

Conversion, Digital control, Hardware

1. INTRODUCTION A hardware design Application Specific Integrated

Circuit (ASIC) (Winsby A., et al., 1998) may also be
Many automatic control systems utilise a digital considered to replace a hardware-software approach
control algorithm (IEE, 1998) for the control of a in scenarios where the advantages that an ASIC
desired plant. In many cases, the digital control solution may provide benefit the final design
technique is based on Z–transform algorithms, and solution. Where the solution is considered for an
allows for standard (e.g. digital PID (Astrom K. and ASIC or FPGA/PLD device, dedicated hardware may
Wittenmark B., 1990)) and novel control techniques be considered as a cell within the overall distributed
to be employed. Fuzzy logic (Chang H. and Gau J., control system that will operate under its own set of
1997) techniques, for example, have also been instructions, but under the supervision of a suitable
successfully developed and are used in many host processor system, either on- or off-chip.
applications. These utilise digital logic Hardware Description Languages (HDLs) are utilised
circuits/systems in order to implement the required within the design process for these digital circuits
algorithms and may be implemented as either a and systems.
hardware-software or hardware only based system. In
addition to this, the hardware may be dedicated or re- The approaches taken in creating the control system
programmable (e.g. with an FPGA (Field and controller implementations can take a number of
Programmable Gate Array) or PLD (Programmable forms, from an ad-hoc design approach which is
Logic Device)). Both the software (Texas essentially re-invented on each new design problem
Instruments, 1991) and re-programmable logic encountered, through to formalised approaches which
approaches allow for flexibility in the ability to have the ability to provide repeatable results.
readily modify the algorithm for different plant types. Formalised approaches may provide a solution whose
effectiveness can be analysed and where automatically to VHDL code for logic simulation and
improvements to both the design approach and synthesis.
chosen implementation architectures can be
predicted. The approaches that may be adopted will The paper is presented as follows. Section 1, this
in many cases be realised by a software suite, or section, provides an introduction for the design
toolbox. approach adopted. Section 2 will provide an
overview of relevant aspects of the VHDL language
As an example, figure 1 identifies a simplified used for simulation and synthesis of the resulting
closed-loop control system in which such a digital digital system. The conversion toolbox will be
device is to operate. Here, the digital controller is at introduced in Section 3 and this is utilised in a simple
the core of a mixed-technology system that is case study in section 4. Section 5 provides a set of
analogue in nature. In many cases, the topology of conclusions to the paper and identifies future work.
the control system would contain more complexity,
with additional command input and feedback sensor
signals to process within a set time. 2. VHDL FOR DIGITAL CIRCUITS/SYSTEMS
Command The VHSIC Hardware Description Language
input Synthesized (VHDL) is an industry standard language used within
VHDL model the design of digital circuits and systems. Toolsets
based on the language allow the designer to model,
Analogue simulate and ultimately synthesise into hardware
signal
conditioning
logic complex digital designs commonly encountered
ADC Digital core in modern electronic devices. Figure 2 identifies how
(Algorithm) VHDL is utilised in a typical approach to the design
Analogue process.
signal
conditioning Simulation
System/algorithm
to
DAC specification and
ensure
correct simulation Design
functionality entry
Analogue and
signal
conditioning RTL code verification
Simulation
Plant
and
Power results
Sensor RTL code
amplifier comparison
synthesis

Fig. 1. Simplified example system utilising a

custom digital core Place & Physical
This paper will describe the development of a Route layout Design
prototype software toolbox that can analyze and
process a Simulink (The MathWorks Inc.) block
diagram model in order to produce a VHDL (Sjoholm Design to
S. and Lindh L., 1997) representation of the original ASIC vendor
model. The toolbox is considered as a prototype as it
allows for future development to be undertaken. This
Fig. 2. Design using VHDL: ASIC Design Route
is considered integral to the creation of a larger
development platform, for use in the development of Using a top-down design methodology and starting
custom silicon hardware solutions for digital control from a high level description at the system/algorithm
applications. Simulink is a software tool integrated level, the models are analysed for functional
within Matlab (The MathWorks Inc.) for modeling, correctness. More detailed models are generated,
simulating and analyzing dynamical systems. VHDL, increasing the description detail and considering the
the VHSIC Hardware Description Language (IEEE hardware implementation aspects. These models are
Standard 1076-1993), is used in the modeling, developed to be suited for synthesis, by typically
simulation and synthesis of digital circuits and developing RTL (Register Transfer Level) code. The
systems. functionally correct code, describing the Entities and
Architectures, may then be synthesised into actual
The overall intention is to enable the behaviour of a hardware. This paper considers the above basic steps,
digital algorithm to be modeled in Simulink and, with taking the system/algorithm from the Simulink block
given user-defined parameters, convert this diagram and converting this to synthesisable VHDL
code based on mapping model blocks to pre-defined
entity/architecture constructs. Where required, these At each stage in the creation/conversion process,
constructs are parameterisable for the particular simulation is used to ensure that the models function
design scenario. correctly. In figure 3, stage 1 models of the
behaviour of the overall system and defines a
In the final circuit, adequate consideration must also behavioural model of the controller core. The
be given to the testability aspects of the circuit (a simulation for this is in terms of the system’s
design-for-test (DfT) approach). Whilst testability is dynamics and response to a range of test stimuli
considered from the outset of the design process, (step, sinusoidal, ramp, etc.). In stages 2 and 3, on
detailed implementation and optimisation of the the other hand, the simulation is in terms of the
circuit architecture and test structures would be a digital logic behaviour and the flow of logic signals
process of circuit enhancement, both pre- and post- (logic 0 and 1, along with propagation delays)
synthesis. This would be required to ensure an through the controller core. Care must be taken to
adequate test coverage whilst minimising the impact ensure that the viewed data flow is as expected.
on circuit performance and cost. The entities and
architectures are by default generated with ports to Although only a small sub-set of blocks may
enable scan-path testing, but not the actual hardware currently be processed, the toolbox has been arranged
to enable this. If required, the designer may, with a to allow for additional blocks to be added at a later
small modification to the final design, realise scan stage. The resulting data will be a model (.mdl) file
path testing. for the complete system, and a second model file for
the blocks for processing. It is this second model file
that is processed to create the VHDL code: described
3. CONVERSION TOOLBOX OVERVIEW in terms of VHDL entities and architectures. Two
stages in the conversion are considered. The first,
The conversion routine is to be considered as part of primarily described here, shows the first stage in
a larger design flow and development system. An conversion that maps Simulink blocks to VHDL
overview of the design process is shown in figure 3. entities and architectures. The second, performs an
Here, the main steps from initial modelling through optimization routine to map the functions to a
to design data output for design realisation are predefined architecture. Both solutions may be
shown. considered in order to determine a solution that
attains the required functionality whilst occupying
1 Digital part for a small silicon area. The toolbox has been set-up
System
conversion to operate in one of two ways. Firstly, directly
from the UNIX command line where the user will
Simulink model Simulink model be prompted to enter configuration information
(.mdl file) (.mdl file) from the keyboard. This would allow for the
program to be integrated into other toolsets.
Secondly, the toolbox may be called from the
Matlab command line as a Matlab function.
2
Conversion VHDL models Once conversion and optimization have been
utility (.vhd files) completed, the VHDL (.vhd) files are used within
a suitable design flow to compile the entities and
architectures into VHDL design units, to simulate
Optimisation the digital logic behaviour of the hardware design
and, if conversion and the simulation results
provide a design that has been verified through
digital logic simulation, to synthesize this code
Logic
VHDL models Synthesis into a netlist for producing:
simulation
(.vhd files)
? A target FPGA configuration data
? The mask data to fabricate a semi-custom
ASIC: silicon foundry Netlist/schematic: (digital, cell based) ASIC for a suitable target
interface simulation fabrication process: this may be integrated into a
3 mixed-signal ASIC containing also analogue
signal conditioning, ADC and DAC macros
FPGA/PLD: configuration Layout place &
data route The choice of whether to target an FPGA or ASIC
could be made at any point within the initial
design stages, provided that the resulting
Fig. 3. Overview of conversion routine within a hardware was to meet the design requirements.
design process Additionally, prior to synthesis, it may also be a
requirement for the user to intervene and modify
the VHDL architecture code in order to guide the clock (currently user-set to either 1MHz, 2MHz and
synthesis of certain circuit architecture styles that 4MHz). The control unit VHDL template entity and
could be required. Therefore, an integral part of the architecture are automatically developed to provide
overall approach is to allow, where necessary, the timing signals for the internal data routing,
user to have control over the process adopted. manipulation and storage. However, in the final
However, this may result in several versions of a logic hardware, additional timing propagation delays
design where modifications are undertaken. Although from cell and interconnect loading must be taken into
consideration for this has not been explicitly built account. The control unit template is developed to
into the approach, this would warrant further take into account delays measured from case study
consideration. It could also be envisaged that an designs and is aimed to minimise the potential for
essentially push-button, automated approach may be timing errors in the final design.
adopted for prototyping purposes on re-
programmable devices.
4. CASE STUDY
The conversion program may be operated directly
from the UNIX command prompt, or via a Matlab The case study design is based around an ASIC
Graphical User Interface (GUI), see figure 4. This design consisting of a digital core and analogue I/O
allows the user to set-up the conversion parameters for closed-loop motor control. This interfaces to
(I/O wordlength, serial/parallel conversion, external sensor and actuator signal conditioning and
optimisation requirements, internal arithmetic type power amplifier circuits to the mechanical drive.
(2’s complement is currently the only numbering Figure 5 shows the top-level model with the
system supported) and the target synthesis tool). The controller device defined within a sub-system block.
sampling frequency and master clock frequency are
also set in order to generate the code for a default
timing controller block.

Fig. 5. Simulink model for the control system

The intention is to process the sub-system block

Fig. 4. Matlab GUI model in order to target an ASIC solution. Equally,
an FPGA solution may be considered and for either
The user then runs the conversion program and may prototyping a final ASIC solution, or in itself
view the output files, along with log files (in providing the end product. The core model is shown
text/HTML formats). The final GUI button allows in figure 6. It contains two independent digital PID
the user to run an optional optimisation program that controllers, for the X and Y-axes.
is aimed to convert the directly mapped VHDL code
to a design that should require less silicon area. This
facility has not yet been fully implemented.

In the initial conversion stage, the internal

wordlength for signal processing is set to be a
multiple of the input wordlength. The default internal
wordlength is twice that of the input. The input block
itself converts a binary count to 2’s complement
values for internal calculations. So, a 10-bit
resolution input is set internally to 20 bits, with the
most-significant bit acting as the sign. This is
propagated through the design and in a block where
the potential for overflow/underflow occurs, the
VHDL code contains limiting of the signal value to
the maximum/minimum allowed values. The output
Fig. 6. Simulink model for the digital core for
from the core has the internal wordlength input and
conversion
output wordlength output. Again, signal value
limiting and conversion from 2’s complement values The model contains basic Simulink blocks: Inport,
back to binary is provided. All blocks are under the Outport, Unit Delay, Gain and Sum. Each of
control of a global (master) reset (active low) and these is parameterised in relation to the I/O
wordlength, number of block inputs (Sum) and gain terms of layout placement to maintain certain
value (Gain). These are placed within a new library boundaries to keep track lengths as short as practical.
that enables additional attributes to be incorporated
without any modifications to the original blocks.
Consideration must also be given to the mapping of 5. CONCLUSIONS AND FUTURE WORK
functions from the original block diagram to be final
code for synthesis. In figure 6, there are 6 This paper has described the development and use of
multiplication blocks used. The direct mapping a toolbox capable of converting a Simulink block
converts these to six individual hardware multiplier diagram into a VHDL representation of the model.
blocks. In hardware, this would result in a design that The use of this was demonstrated in the development
performed its operations in a minimum time, but of a digital hardware controller core for a closed-loop
would be excessively large in terms of the number of X-Y position control system.
logic cells required, hence size. The speed benefit
would not necessarily be of use, except in scenarios To-date, simple case study designs have been
requiring a high sampling rate. In many scenarios, a successfully converted into VHDL code and
single, multiplexed multiplier cell would be sufficient synthesised into digital logic. The study design here
and this is an aspect incorporated in the optimised considered only a direct mapping of a Simulink block
VHDL code. into a VHDL entity/architecture pair which performs
the required function in code that is structured for
Figure 7 shows the schematic view of the synthesis.
synthesised code, prior to layout. Post-synthesis logic
simulation here was performed using Verilog (Golze Future work is to consider the optimisation of the
U., 1996). code which will perform the required functions
whilst intending to reduce the required number of
required gates (and silicon area, hence costs in an
ASIC solution). Once this is complete, the case study
design will be fabricated and the hardware evaluated.

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