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Experiment:2: ABC C S

The document describes an experiment to implement a full adder circuit using VHDL. [1] The aim is to write VHDL code for a full adder circuit and implement it on an FPGA/CPLD chip. [2] A full adder is a combinational circuit that performs the arithmetic sum of three input bits and produces two outputs, sum and carry. [3] The VHDL code for the full adder is written, simulated, and successfully implemented on a CPLD chip, verifying the truth table.

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Shivratan Gupta
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54 views

Experiment:2: ABC C S

The document describes an experiment to implement a full adder circuit using VHDL. [1] The aim is to write VHDL code for a full adder circuit and implement it on an FPGA/CPLD chip. [2] A full adder is a combinational circuit that performs the arithmetic sum of three input bits and produces two outputs, sum and carry. [3] The VHDL code for the full adder is written, simulated, and successfully implemented on a CPLD chip, verifying the truth table.

Uploaded by

Shivratan Gupta
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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EXPERIMENT :2

AIM:- Write an HDL code for full adder circuit and implement on FPGA/CPLD chip.

EDA Tool:- Project Navigator 6.1i, Modelsim SE 5.5c, Xilinx CPLD –XC9572fpc84

THEORY:-
A digital system consists of two types of circuits namely
1) Combinational logic circuit
2) Sequential logic circuit

In a combinational circuit, the output at any time depends only on the input values at that
time.In a sequential circuit, the output at anytime depends on the present input values as
well as the past output values.

A full adder is a combinational circuit which performs the arithmetic sum of three input
bits and produces 2 outputs sum and carry. From the truth table one can understand that
binary variable s gives the value of LSB of sum and Cout gives the output carry.

Inputs Outputs
A B Cin Cout S
0 0 0 0 0
1 0 0 0 1
0 1 0 0 1
1 1 0 1 0
0 0 1 0 1
1 0 1 1 0
0 1 1 1 0
1 1 1 1 1

VHDL CODE:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fullader is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
s : out std_logic;
cr : out std_logic);
end fullader;

architecture behavioral of fullader is

begin
process ( a,b,c)
begin
s<= a xor b xor c ;
cr <= (a and b ) or ( b and c) or (c and a);
end process ;

end behavioral;

User Constraint File(UCF):-

net "a" loc="p71";


net "b" loc="p70';
net "c" loc="p69";
net "s" loc="p34";
net "cr" loc="p33";

RTL SCHEMATIC OF FULL ADDER


SIMULATION OF FULL ADDER

RESULT:- The truth table for full adder is verified on simulator and HDL code being
implemented on CPLD successfully.

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