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The document describes a VLSI chip design project that involves characterizing and recompiling multiple modules (adder, comparator, cascade) and integrating them into a top-level chip design. It provides instructions for characterizing individual modules, writing characterization scripts, linking the modules together, and recompiling the integrated chip design using standard cell placement and routing tools.

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phanithekrrish
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© Attribution Non-Commercial (BY-NC)
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33 views

Lists and Hashes

The document describes a VLSI chip design project that involves characterizing and recompiling multiple modules (adder, comparator, cascade) and integrating them into a top-level chip design. It provides instructions for characterizing individual modules, writing characterization scripts, linking the modules together, and recompiling the integrated chip design using standard cell placement and routing tools.

Uploaded by

phanithekrrish
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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1.

LISTS AND HASHES:


LOOPS PROGRAMS
SUBROTEINS:
PROJECT2: current_design ChipLevel
characterize u2
current_design CascadeMod
COMPARATOR write_script -format dctcl -output "CascadeMod.wtcl"

current_design Comparator current_design ChipLevel


source {/gaia/class/student/syedat/274proj2/defaults.con} characterize u3
current_design Comparator
set_load 2.5 {cp_out} write_script -format dctcl -output "Comparator.wtcl"
set_driving_cell -no_design_rule -lib_cell FD1 [all_inputs]
set_wire_load_model -name "05x05" RUN:
set_wire_load_mode enclosed
set_input_delay 1.35 -clock $clk_name  [get_ports ain] read_file -format ddc
set_input_delay 1.35 -clock $clk_name  [get_ports bin] "/gaia/class/student/syedat/274proj2/ChipLevel.ddc"
set_output_delay 5.1 -clock $clk_name  [get_ports cp_out]
set_max_area 0 source {/gaia/class/student/syedat/274proj2/defaults.con}
source {/gaia/class/student/syedat/274proj2/Adder16.scr}
compile source {/gaia/class/student/syedat/274proj2/CascadeMod.scr}
write -hierarchy -f ddc -out "Comparator.ddc" source {/gaia/class/student/syedat/274proj2/Comparator.scr}

report_area > "Comparator_area.rpt" write -hierarchy -f ddc -out "ChipLevel_Final_all.ddc"


report_timing > "Comparator_timing.rpt" source {/gaia/class/student/syedat/274proj2/characterize.scr}
remove_design -all
DEFAULT: read_file -format ddc
"/gaia/class/student/syedat/274proj2/ChipLevel.ddc"
set clk_period 20 source {/gaia/class/student/syedat/274proj2/recompile.scr}
# Create real clock if clock port is found write -hierarchy -f ddc -out "ChipLevel_final.ddc"
if {[sizeof_collection [get_ports clk]] > 0} {
set clk_name clk
create_clock -period $clk_period clk RECOMPILE:
}
link
# Create virtual clock if clock port is not found current_design ChipLevel
if {[sizeof_collection [get_ports clk]] == 0} {
set clk_name vclk source "/gaia/class/student/syedat/274proj2/defaults.con"
create_clock -period $clk_period -name vclk source "/gaia/class/student/syedat/274proj2/Adder16.wtcl"
} compile
write -format ddc -output "Adder16_wtcl.ddc"
# Apply default drive strengths and typical loads report_area > "Adder16_wtcl_area.rpt"
# for I/O ports report_timing > "Adder16_wtcl_timing.rpt"
set_load 1.5 [all_outputs]
set_driving_cell -lib_cell IV [all_inputs] source "/gaia/class/student/syedat/274proj2/CascadeMod.wtcl"
# If real clock, set infinite drive strength set_dont_touch u12
if {[sizeof_collection [get_ports clk]] > 0} { uniquify
set_drive 0 clk compile
} write -format ddc -output "CascadeMod_wtcl.ddc"
report_area > "CascadeMod_wtcl_area.rpt"
# Apply default timing constraints for modules report_timing > "CascadeMod_wtcl_timing.rpt"
set_input_delay 1.2 [all_inputs] -clock $clk_name
set_output_delay 1.5 [all_outputs] -clock $clk_name source "/gaia/class/student/syedat/274proj2/Comparator.wtcl"
set_clock_uncertainty -setup 0.45 $clk_name compile
write -format ddc -output "Comparator_wtcl.ddc"
# Set operating conditions report_area > "Comparator_wtcl_area.rpt"
set_operating_conditions WCCOM report_timing > "Comparator_wtcl_timing.rpt"
set auto_wire_load_selection true

CHARACTERIZE:

read_file -format ddc 


"/gaia/class/student/syedat/274proj2/ChipLevel.ddc"
current_design ChipLevel
characterize u1
current_design Adder16
write_script -format dctcl -output "Adder16.wtcl"

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