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COCOCribzv 3

- Number systems can be converted between decimal, binary, and hexadecimal by dividing or multiplying by the base and reading remainders or results in reverse order. Fractions can be represented in binary and hexadecimal by repeatedly dividing the numerator by the denominator. - Digital circuits use Boolean algebra and logic gates like AND, OR, NAND, and NOR to perform arithmetic operations and implement functions. Common components include adders, decoders, encoders, multiplexers, and flip-flops. - Hardware description languages like VHDL are used to model and test digital designs hierarchically from signals to components. Physical devices like PLDs, CMOS gates, and FPGAs can then realize the designed logic.

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Miguel N.
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65 views4 pages

COCOCribzv 3

- Number systems can be converted between decimal, binary, and hexadecimal by dividing or multiplying by the base and reading remainders or results in reverse order. Fractions can be represented in binary and hexadecimal by repeatedly dividing the numerator by the denominator. - Digital circuits use Boolean algebra and logic gates like AND, OR, NAND, and NOR to perform arithmetic operations and implement functions. Common components include adders, decoders, encoders, multiplexers, and flip-flops. - Hardware description languages like VHDL are used to model and test digital designs hierarchically from signals to components. Physical devices like PLDs, CMOS gates, and FPGAs can then realize the designed logic.

Uploaded by

Miguel N.
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Number Systems

Decimal  Hex – divide by 16 until 0, remainders in reverse // Decimal  Binary – divide by 2 until 0, remainders in reverse
FRACTIONS  Binary and Hex-- n-1 etc // From Decimal – multiply by base instead of divide
Arithmetic
Add Negate Subtract
Unsigned Add –OOR if MSB carry occurs N/A Subtract – OOR if MSB borrow
occurs
Signed Mag (same sign)— Change Sign Change sign of subtracted number
See unsigned result has sign of bit and add
(diff sign) –
Subtract smaller from larger result has sign of
larger
Two’s Comp Add—Overflow occurs only if carries into and out Complemen Negate subtracted number
of MSB are different t and add 1

Boolean Algebra Rules

Circuit Implementation
NAND-NAND form SOP (negate groups/AND the groups/negate whole thing) NOR-NOR (negate groups/OR groups/negate )
XOR = AB’ + A’B – XNOR = AB + A’B’

KMAPS and Hazards


Any unnecessary implicant in a KMAP is a hazard cover – For POS use 0’s for SOP use 1’s
Static-1 Hazard (unexpected 0, SOP) Static-0 Hazard (unexpected 1, POS)

CMOS
NMOS (no bubble – HIGH=ON) PMOS (bubble – LOW=ON) – come in pairs, always
NAND is PMOS in parallel Vcc, NMOS series GND – NOR is PMOS in series near Vcc, NMOS parallel GND

Quine McKlusky
The top row labels (aka columns) represent each MINTERM of the function (the SOP numbers)
The left column labes (aka rows) represent each prime implicants (XXX1) from the third/second columns

Codes – mindist = 2c+1 to CORRECT cbits – mindist = 2c+d+1 to CORRECT cbits and DETECT dbits
VHDL
Hierarchy of signals  Uninit(U) >> Unknown(X) >> ( 0,1) >> (Z) >> Weak(W) >> (H,L) >> dontcare(-)

PLDs
 PLDs can realize arbitrary logic functions as sums of products
 Primarily for combinational circuits (some have sequential configurations)
 Fuses can be permanent, controlled by RAM, or electrically programmable/erasable
 Implementation of choice for low volume (prototyping)

Decoders/Encoders
Take a binary number and output to the corresponding pin
74x138 – 3to8 Binary decoder – 2 lowenables 1 high enable, 3 input, 8 low outputs (LEFTBELOW)
74x148 – 8to3 Binary encoder – 8 low inputs, 1 low enable, 3 low outputs, gotsomething low (RIGHT BELOW)

 Encoders map one of 2^n signals to an n-bit signal, binary decoders map an nbit signal to one of 2^n outputs
 Note: 74x245 bidirectional 3 state transceiver (enablelow, 8I/O buffers, directionbit)

Multiplexers
 Digital switch that connects one of n-inputs to a single output
 inputs can be one or more bits wide
 control signal selects output, enable bit
 Demux is the opposite

Adders
 Addition and subtraction are performed by the same circuit
 Propagating carries and borrows takes time, precompute
 Adders can be chained

Flip Flops and Latches


 "Set/Reset Latch" – No clock, 1 on R is reset, 1 on S is set, 00 is hold
 "D-Latch" only changes on enable high – next state =
 "Edge triggered D-FF" triggered by a positive change in the clock
o Useful in converting asynchronous input into sync system
o best choice in VLSI and storage registers
 "Master/Slave SR-FF" set/reset the master FF while C=1 and then on
the falling edge of C (c=0) outputs. (delayed output )
o issue occurs when S and R are asserted, output could be worthless
 "Master/Slave JK-FF" Solves the issue of asserting S and R at the same time (NEVER USE – 1s and 0s catching suck)
 "Edge Triggered JK FF" Solves the issue of 1s and 0s catching – 74x109 – JK' FF – uses a D flipflop instead of an SR
master/slave set up – best JK flipflop – Dflipflops are still most widely used – Least amount of logic, most wiring,
very versatile
 "T-FlopFLop" Toggle flip flop, toggles on every tick of clock, output usually half the frequency of the T input –
usually constructed from JK flipflops, good for implementing counters
 KEEP IN MIND  Latches are Level Sensitive, FlipFlops are Edge Sensitive
States and such

Notes:
 To obtain the limit for 2s compliment – overflow – 2^n / 2 – 2^n is the total number of values to be used (neg+pos)
o A n-bit 2's comp number has 2^n represented values, therefore max pos value is 2^n/2 -1
 For sign mag – an nbit number can go up to 2^(n-1)-1 example: 9bit sign mag  2^8-1 = 255
 Use KMAPs, everywhere. EVERYWHERE
 When assigning content to ROM addresses – if one bit is not specified, make an assumption and declare it
 Each block in an adder (one bit) has inputs: An, Bn, Carryin and outputs: Carryout, sum
 SDRAM setup – in a 1024x1024 array with 8 bit words –
o Address bus is 10+7
o Row decoder is 10 address bits
o 1024 column latches, 1024 row latches
o 7 select signals necessary for the mux/demux
 Every state in a state diagram must have an arrow representing every possibility
 CMOS NAND gate uses four transistors (2pchan 2nchan) an AND gate would use 6 – NAND + Inverter
 Boolean duals are derived by (ANDOR) (01) represented by a *
 FOR CPLDs – A Macrocell is an SOP with a FF, 18 in each function block, AND ArrayPTAllocatorsFunctionblocks
 High noise margin is the difference between High mins, low noise margin is the difference between low maxs

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